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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: util/cbfstool: Make sure to only compare PT_LOAD stages
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84140/comment/15cb18f7_f3000174?us… :
PS2, Line 7: stages
*segments*?
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84144?usp=email )
Change subject: soc/intel/alderlake: Prevent overlapping boot screens
......................................................................
soc/intel/alderlake: Prevent overlapping boot screens
Previously, `early_graphics_stop()` was skipped unconditionally if
`CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` was enabled. This led
to overlapping screens when CSE sync was not triggered in ramstage,
as both the eSOL message and the firmware splash screen would be
displayed.
This change refactors the condition for calling `early_graphics_stop()`
to ensure it is only skipped if a CSE firmware update is actually
required *and* `CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` is set.
This allows eSOL to display its message during CSE sync, but tears
down early graphics programming in other cases to prevent overlapping
screens.
Additionally, this change ensures that `early_graphics_stop()` is the
last function called by the romstage to guarantee proper cleanup.
BUG=b:362895813
TEST=Able to boot google/tivviks_ufs without overlapping screens.
Change-Id: Idc01bfc8963d65fcb0441300e7c9267eaaefefb9
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/alderlake/romstage/romstage.c
1 file changed, 8 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/84144/1
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index b577e32..ff600db 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -215,16 +215,18 @@
if (!s3wake)
save_dimm_info();
+ if (CONFIG(ENABLE_EARLY_DMA_PROTECTION))
+ vtd_enable_dma_protection();
+
+ /* Keep eSOL active if CSE sync is pending at ramstage */
+ if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required())
+ return;
+
/*
* Turn-off early graphics configuration with two purposes:
* - Clear any potentially still on-screen message
* - Allow PEIM graphics driver to smoothly execute in ramstage if
* RUN_FSP_GOP is selected
*/
- if (!CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE))
- /* Keep eSOL active if CSE sync in ramstage config is enabled */
- early_graphics_stop();
-
- if (CONFIG(ENABLE_EARLY_DMA_PROTECTION))
- vtd_enable_dma_protection();
+ early_graphics_stop();
}
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Change subject: drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_info
......................................................................
Patch Set 16: Code-Review+2
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Change subject: util/cbfstool: Make sure to only compare PT_LOAD stages
......................................................................
Patch Set 2: Code-Review+2
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Change subject: util/cbfstool: Deal with how lld organizes loadable segments
......................................................................
Patch Set 13: Code-Review+1
(1 comment)
File util/cbfstool/cbfs-mkstage.c:
https://review.coreboot.org/c/coreboot/+/84043/comment/f6ef54ae_e34c4292?us… :
PS7, Line 301: prev = cur
> > Maybe I'm confusing myself too much. What do we actually try to assert? […]
Done
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Change subject: drivers/spi: Stop using a variable-length array, 2nd try
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS1:
> Let's wait for the release and try to test it better this time...
Done
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Change subject: drivers/spi: Stop using a variable-length array, 2nd try
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84059/comment/9118cd97_ec8bd339?us… :
PS2, Line 22: in
> nit: if you move `in` to the next line, this paragraph would have the same line length as the other two
Everything just has the max len allowed for a line.
https://review.coreboot.org/c/coreboot/+/84059/comment/898fa1bd_9abc70c1?us… :
PS2, Line 27: https://review.coreboot.org/c/coreboot/+/50480
> I'd reference the commit hash instead
Done
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Hello Angel Pons, Elyes Haouas, Felix Held, Julius Werner, Nico Huber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: drivers/spi: Stop using a variable-length array, 2nd try
......................................................................
drivers/spi: Stop using a variable-length array, 2nd try
Only the call in `spi_flash_cmd_write_page_program` uses non-constant
values for the array length. However, the value for `data_len` has an
upper bound: `flash->page_size` is set to `1U << vi->page_size_shift`
which depends on the flash chip vendor info, and the largest value it
can currently have is 8. Thus, the maximum page size is currently 256.
Define the `MAX_FLASH_CMD_DATA_SIZE` macro to place an upper bound on
the amount of data that can be written in one command. Then, use this
value to allocate a fixed-size buffer in `spi_flash_cmd_write`. Also,
add a check to prevent buffer overflow problems. Finally, ensure that
the `spi_flash_cmd_write_page_program` function always writes no more
than 256 bytes of data when using the `spi_flash_cmd_write` function.
The buffer is placed in .bss so that it does not increase stack usage in
some use cases.
Tested on Asrock B85M Pro4 (Winbond W25Q64FV), MRC cache still works.
Repost of 59626b86 with 'static' so that the buffer is in bss.
Change-Id: I157ecec69c049ead06467b0328efd7d1a09bd268
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/spi/spi_flash.c
M src/drivers/spi/spi_flash_internal.h
2 files changed, 9 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/84059/3
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Hello Angel Pons, Nico Huber, build bot (Jenkins),
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The following approvals got outdated and were removed:
Code-Review+1 by Nico Huber
Change subject: drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_info
......................................................................
drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_info
GCC LTO found this.
Change-Id: I2d5a9a86dbb91a5505891a30c6e9072b1b4dfc92
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/intel/gma/gma-gfx_init.ads
M src/drivers/intel/gma/hires_fb/gma-gfx_init.adb
M src/include/framebuffer_info.h
M src/lib/edid_fill_fb.c
4 files changed, 15 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/84056/16
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Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83322?usp=email )
Change subject: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
......................................................................
Patch Set 19:
(1 comment)
File src/mainboard/intel/frost_creek/board.fmd:
https://review.coreboot.org/c/coreboot/+/83322/comment/e85023d4_b9e08dea?us… :
PS19, Line 2: BIOS@0x01400000 0x00C00000 {
> can you define the first 20M as a place holder (e.g. […]
should be okay as is, close the open here.
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