coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
by Shuo Liu (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83322?usp=email ) Change subject: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge ...................................................................... Patch Set 19: (1 comment) File src/mainboard/intel/frost_creek/board.fmd: https://review.coreboot.org/c/coreboot/+/83322/comment/e85023d4_b9e08dea?us… : PS19, Line 2: BIOS@0x01400000 0x00C00000 { > can you define the first 20M as a place holder (e.g. […] should be okay as is, close the open here. -- To view, visit https://review.coreboot.org/c/coreboot/+/83322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013 Gerrit-Change-Number: 83322 Gerrit-PatchSet: 19 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 30 Aug 2024 12:04:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: mb/google/brox/jubilant: I2C signal tuning
by Subrata Banik (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Bob Moragues, Karthik Ramasubramanian, Kenneth Chan, Nick Vaccaro, Ren Kuo. Subrata Banik has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84143?usp=email ) Change subject: mb/google/brox/jubilant: I2C signal tuning ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84143?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42a60edc0b361bfabacf5376ef89f436efedb356 Gerrit-Change-Number: 84143 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 11:37:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Subrata Banik (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 65: (13 comments) File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/691cbf3e_d98834f9?us… : PS50, Line 138: map > If the configuration is static, we can use below code. > > const acpi_cstate_t *soc_get_cstate_map(size_t *entries) > { > static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), > ARRAY_SIZE(cstate_set_non_s0ix))]; > static int initialized = 0; /* Flag to check if map has been initialized */ > size_t i; > > if (!initialized) { > config_t *config = config_of_soc(); > if (config == NULL) { > printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); > return NULL; > } > > int *set; > if (config->s0ix_enable) { > *entries = ARRAY_SIZE(cstate_set_s0ix); > set = cstate_set_s0ix; > } else { > *entries = ARRAY_SIZE(cstate_set_non_s0ix); > set = cstate_set_non_s0ix; > } > > for (i = 0; i < *entries; i++) { > map[i] = cstate_map[set[i]]; > map[i].ctype = i + 1; > } > > initialized = 1; /* Set the flag to indicate initialization is done */ > } > > return map; > } > > Let me know, if that's the ask? why would this function get called more than one? ``` c_state_map = soc_get_cstate_map(&entries); ``` the data type is static, ideally we should return this function if called more than once. but that is a kind of safety method. I don't see any reason for this function required to be protected against multiple call. File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/f0f3a517_63312c3a?us… : PS55, Line 238: PCI_DEVFN_IGD > In the case when igpu is disabled using fatcat variant device tree, this will gaurd the inclusion of DMAR. As this is a client product, I am curious as to what someone would build if they are disabling the IGD. This is why I am asking if checking if the IGD is enabled or not seems redundant if the PTL SOC chipset.cb itself makes this internal GFX enabled. https://review.coreboot.org/c/coreboot/+/83798/comment/49ebcd85_99b7b869?us… : PS55, Line 247: (is_devfn_enabled(PCI_DEVFN_DPTF) || : is_devfn_enabled(PCI_DEVFN_IPU) || : is_devfn_enabled(PCI_DEVFN_NPU) || : is_devfn_enabled(PCI_DEVFN_IAA)) > Hi Subrata, this check is introduced to check if none of the IPs (i.e., DPTF, IPU, NPU, IAA) are enabled, then it should not create the drhd table for nongfxvt. what you think about this suggestion ``` bool is_ipu_enabled = is_devfn_enabled(PCI_DEVFN_IPU); bool is_dptf_enabled = is_devfn_enabled(PCI_DEVFN_DPTF); bool is_npu_enabled = is_devfn_enabled(PCI_DEVFN_NPU); bool is_iaa_enabled = is_devfn_enabled(PCI_DEVFN_IAA); if ((is_ipu_enabled || is_dptf_enabled || is_npu_enabled || is_iaa_enabled) && (vtd_engine_enabled & NONGFXVT_ENABLED)) { const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, (uint64_t)VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE); if (is_ipu_enabled) current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IPU, 0); if (is_dptf_enabled) current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_DPTF, 0); if (is_npu_enabled) current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_NPU, 0); if (is_iaa_enabled) current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IAA, 0); acpi_dmar_drhd_fixup(tmp, current); } ``` https://review.coreboot.org/c/coreboot/+/83798/comment/b2bd0a28_4605427c?us… : PS55, Line 330: 0x7 > As per PTL FAS, which refers to LNL FAS #733648, section 11.5 […] Acknowledged File src/soc/intel/pantherlake/chip.h: https://review.coreboot.org/c/coreboot/+/83798/comment/352166db_ad5e2c6d?us… : PS65, Line 339: bool enable_c6dram; I don't see any usage.please drop https://review.coreboot.org/c/coreboot/+/83798/comment/24d621dc_71b0ad8f?us… : PS65, Line 340: bool pm_timer_disabled; same File src/soc/intel/pantherlake/chip.h: https://review.coreboot.org/c/coreboot/+/83798/comment/03c9deca_d3f4dfa0?us… : PS55, Line 47: PTL_H_484_12_25W_CORE > Looks good to me. > Hi Subrata, please advise? I agree File src/soc/intel/pantherlake/cpu.c: https://review.coreboot.org/c/coreboot/+/83798/comment/4bf0d3f3_2dace154?us… : PS50, Line 143: disable_three_strike_error > Thank you, i have gone through the bug, corrected in MTL EDS. "Ideally 3-strike disable bit 11 should never have been placed in MSR 0x1A4 which is used for disabling prefetchers." is correct. > In PTL EDS, we see the 1ab bit 0 as (DISABLE_SIGNALING_THREE_STRIKE_EVENT) which prevents the signaling of the three-strike event once the counter has expired. > > The function, "disable_signaling_three_strike_event" should be the corrected one to be used. > I am currently validating the read MSR status using iotools of 0x1ab, while using "disable_signaling_three_strike_event" > I will update soon on this. I thought you said previously `disable_signaling_three_strike_event` is the correct API to call for PTL? File src/soc/intel/pantherlake/cpu.c: https://review.coreboot.org/c/coreboot/+/83798/comment/725a52d1_d6bc6a72?us… : PS65, Line 59: BIT(0) FAST_STRINGS_ENABLE_BIT https://review.coreboot.org/c/coreboot/+/83798/comment/2cd4b86f_8acec68f?us… : PS65, Line 60: BIT(3) can u please implement a macro for the required bit-field under the MSR definition ? for example ``` #define IA32_MISC_ENABLE 0x1a0 #define FAST_STRINGS_ENABLE_BIT (1 << 0) #define TM1_TM2_EMTTM_ENABLE_BIT (1 << 3) #define SPEED_STEP_ENABLE_BIT (1 << 16) ``` https://review.coreboot.org/c/coreboot/+/83798/comment/0f8fbbae_e8718783?us… : PS65, Line 72: = BIT(4); same applies here https://review.coreboot.org/c/coreboot/+/83798/comment/10b7cc37_b068df81?us… : PS65, Line 78: msr.lo |= BIT(0); /* Enable Bi-directional PROCHOT as an input*/ : msr.lo |= BIT(23); /* Lock it */ : msr.lo |= BIT(18); /* Power Performance Platform Override */ same File src/soc/intel/pantherlake/include/soc/systemagent.h: https://review.coreboot.org/c/coreboot/+/83798/comment/c9a41276_e24535cf?us… : PS65, Line 32: #define GFXVT_ENABLED BIT(0) : #define NONGFXVT_ENABLED BIT(1) : #define IOCVT_ENABLED BIT(2) if there is no consumer outside ACPI.c file then no harm to define it inside local .c file -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 65 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 11:30:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Modify FP IRQ pin
by Ren Kuo (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Karthik Ramasubramanian, Marx Wang, Marx Wang, Nick Vaccaro, Subrata Banik. Ren Kuo has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84124?usp=email ) Change subject: mb/google/brox/jubilant: Modify FP IRQ pin ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/brox/variants/jubilant/overridetree.cb: https://review.coreboot.org/c/coreboot/+/84124/comment/85538f8b_842e1806?us… : PS6, Line 22: > remove empty line fixed. -- To view, visit https://review.coreboot.org/c/coreboot/+/84124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 Gerrit-Change-Number: 84124 Gerrit-PatchSet: 7 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marx Wang <marx.wang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 11:27:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_info
by Nico Huber (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Angel Pons, Arthur Heymans. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84056?usp=email ) Change subject: drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_info ...................................................................... Patch Set 15: Code-Review+1 (4 comments) File src/drivers/intel/gma/gma-gfx_init.ads: https://review.coreboot.org/c/coreboot/+/84056/comment/e0d6b209_e6fcb11a?us… : PS14, Line 25: size_t > `int` now Done File src/drivers/intel/gma/hires_fb/gma-gfx_init.adb: https://review.coreboot.org/c/coreboot/+/84056/comment/b0e34a7f_02c7b6b7?us… : PS14, Line 42: size_t > dito Done File src/drivers/intel/gma/hires_fb/gma-gfx_init.adb: https://review.coreboot.org/c/coreboot/+/84056/comment/88fc579a_aa345c94?us… : PS15, Line 29: size_t last spot, hopefully File src/lib/edid_fill_fb.c: https://review.coreboot.org/c/coreboot/+/84056/comment/e3139bdd_da4cd12d?us… : PS14, Line 151: ADA > nit, *Ada* Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84056?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d5a9a86dbb91a5505891a30c6e9072b1b4dfc92 Gerrit-Change-Number: 84056 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 30 Aug 2024 11:23:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[S] Change in coreboot[main]: mb/google/brox/jubilant: I2C signal tuning
by Ren Kuo (Code Review) 30 Aug '24

30 Aug '24

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84143?usp=email ) Change subject: mb/google/brox/jubilant: I2C signal tuning ...................................................................... mb/google/brox/jubilant: I2C signal tuning I2C2 signal tuning: Set falling time to 250ns from 400ns to meet HW requirement. BUG=b:362685374 TEST= Build jubilant firmware Measure the i2c signal on jubilant to meet spec Change-Id: I42a60edc0b361bfabacf5376ef89f436efedb356 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/overridetree.cb 1 file changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/84143/1 diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 6d7c3f8..73d1a72 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -37,6 +37,45 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type A port A0(DCI) register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | Audio codec & Sar sensor | + #| I2C4 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 330, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 350, + .data_hold_time_ns = 50, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 250, + .data_hold_time_ns = 50, + }, + .i2c[4] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/84143?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42a60edc0b361bfabacf5376ef89f436efedb356 Gerrit-Change-Number: 84143 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 65: (2 comments) File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83798/comment/523494ac_d1a1e8cb?us… : PS50, Line 69: SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 > Sure. We are working on common code change for 21.0 spec. File src/soc/intel/pantherlake/chipset.cb: https://review.coreboot.org/c/coreboot/+/83798/comment/b8015aa2_7336d197?us… : PS50, Line 15: > can you please gather `tcc_offset` value as well and keep it here ? I am checking this data from PNP team. -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 65 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 11:13:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 65: (1 comment) File src/soc/intel/pantherlake/include/soc/pmc.h: https://review.coreboot.org/c/coreboot/+/83798/comment/d2c29915_41c83dcb?us… : PS38, Line 26: (1 << 18) > Fix: https://review.coreboot. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 65 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 11:08:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC
by Subrata Banik (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email ) Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ...................................................................... Patch Set 49: (7 comments) File src/soc/intel/pantherlake/include/soc/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/83789/comment/a3fa5a6b_54ec19d1?us… : PS49, Line 260: GPP_E_OFFSET I don't see GPP_E0 in the EDS at offset 0x9a0. may be worth passing this feedback for EDS maintainer https://review.coreboot.org/c/coreboot/+/83789/comment/7c7f131b_6142d7f6?us… : PS49, Line 261: GPP_CPUJTAG_OFFSET do we need this macro? File src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h: https://review.coreboot.org/c/coreboot/+/83789/comment/3bc5bf6d_6594c826?us… : PS49, Line 15: 0x1 INC(GPP_V) https://review.coreboot.org/c/coreboot/+/83789/comment/8fb133c0_057f2891?us… : PS49, Line 31: 1 INC(GPP_COMM0_ID) https://review.coreboot.org/c/coreboot/+/83789/comment/d4575783_78e5792d?us… : PS49, Line 36: #define GPP_COMM0_NAME "Community0" : #define GPP_COMM1_NAME "Community1" : #define GPP_COMM3_NAME "Community3" : #define GPP_COMM4_NAME "Community4" : #define GPP_COMM5_NAME "Community5" : : #define GPP_V_NAME "GPP_V" : #define GPP_C_NAME "GPP_C" : #define GPP_F_NAME "GPP_F" : #define GPP_E_NAME "GPP_E" : #define GPP_CPUJTAG_NAME "GPUJTAG" : #define GPP_H_NAME "GPP_H" : #define GPP_A_NAME "GPP_A" : #define GPP_VGPIO3_NAME "vGPIO_3" : #define GPP_S_NAME "GPP_S" : #define GPP_B_NAME "GPP_B" : #define GPP_D_NAME "GPP_D" : #define GPP_VGPIO_NAME "vGPIO" : move macro definition into GPIO.h https://review.coreboot.org/c/coreboot/+/83789/comment/96a32b5c_9462f4db?us… : PS49, Line 58: 1 INC(COMM_0) https://review.coreboot.org/c/coreboot/+/83789/comment/4b1e3369_fa50aac1?us… : PS49, Line 250: #define NUM_COM1_GPP_GROUPS 2 I don't see any consumer for NUM_COMx_GPP_GROUPS macro -- To view, visit https://review.coreboot.org/c/coreboot/+/83789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Gerrit-Change-Number: 83789 Gerrit-PatchSet: 49 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 30 Aug 2024 11:01:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/common/block/pmc: Fix compilation error with MS4V=BIT(18)
by Ashish Kumar Mishra (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Saurabh Mishra, Subrata Banik. Ashish Kumar Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: soc/intel/common/block/pmc: Fix compilation error with MS4V=BIT(18) ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84142/comment/8f22f68b_bc24b0b8?us… : PS1, Line 9: If MS4V is defined using the BIT macro such in as in BIT(18) for : instance, it is replaced with (1ul << 18) > > A better solution would be to add a BIT_U macro for (1u << x), instead of typecasting. […] yes, I was suggesting adding a new 32-bit macro BIT_U() or BIT_32() and handling it's usage based on the 64-bit KConfig. -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 2 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 11:01:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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