coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/common/gpio: support 16-bit CPU Port ID
by Subrata Banik (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email ) Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID ...................................................................... Patch Set 8: (3 comments) Patchset: PS7: > 8.13.1 and 8.13.2 has 16-bit Port ID info. We are also working on vw info for external. Acknowledged Commit Message: https://review.coreboot.org/c/coreboot/+/83981/comment/735655d0_7b11d8b9?us… : PS4, Line 13: vw_index and position are not continuous in between groups within a : community. > > I've asked this morning. waiting for response. […] Acknowledged File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/c/coreboot/+/83981/comment/7a15a519_d59fda9f?us… : PS4, Line 1071: } > In fact, in MTL, community 3 GPP_H starts from vw 16h. This can be fixed using: > .vw_base = 0x16, > > currently, it is: > .vw_base = DEFAULT_VW_BASE we shall discuss this as part of CB:83997 -- To view, visit https://review.coreboot.org/c/coreboot/+/83981?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d Gerrit-Change-Number: 83981 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 30 Aug 2024 09:47:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/gpio: support 16-bit CPU Port ID
by Subrata Banik (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email ) Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83981?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d Gerrit-Change-Number: 83981 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 30 Aug 2024 09:41:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: payloads/depthcharge: Add default 64-bit libpayload config
by Subrata Banik (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Martin L Roth, Paul Menzel, Wonkyu Kim. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84107?usp=email ) Change subject: payloads/depthcharge: Add default 64-bit libpayload config ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac07cf9e3c11e49955c69553407be76ef4f8c060 Gerrit-Change-Number: 84107 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 30 Aug 2024 09:35:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: drivers/spi: Stop using a variable-length array
by Angel Pons (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Arthur Heymans, Elyes Haouas, Felix Held, Julius Werner. Angel Pons has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84059?usp=email ) Change subject: drivers/spi: Stop using a variable-length array ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84059/comment/8e799788_a8dfec2a?us… : PS2, Line 7: drivers/spi: Stop using a variable-length array I'd add a `, 2nd try` suffix to help differentiate between the original and reverted commit. https://review.coreboot.org/c/coreboot/+/84059/comment/18930118_0cf01315?us… : PS2, Line 22: in nit: if you move `in` to the next line, this paragraph would have the same line length as the other two https://review.coreboot.org/c/coreboot/+/84059/comment/43e1a058_3b9360e5?us… : PS2, Line 27: https://review.coreboot.org/c/coreboot/+/50480 I'd reference the commit hash instead -- To view, visit https://review.coreboot.org/c/coreboot/+/84059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I157ecec69c049ead06467b0328efd7d1a09bd268 Gerrit-Change-Number: 84059 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 30 Aug 2024 09:34:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Subrata Banik (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 7: (10 comments) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/3e19191d_60628e63?us… : PS3, Line 406: pmc_clear_gpi_gpe0_status > gpi_gpe0 means the general GPI event in GPE0. GPE1 only contains Intel's std events. ideally you have to clean event status register for all GPEs (irrespective of if it's GPE0 and GPE1). This is required to avoid a fake wake during system sleep or S5 entry. Additionally, you are not cleaning the Enable bit hence, it should be okay. Status bit is asserted by the hardware and only be cleared upon writing 1 to it. The idea to clear the GPE status to avoid fake wake due to persistent status bit (which often due to poor hardware) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/a6c86904_4df4a535?us… : PS7, Line 25: #if !CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1) : : /* NOTE: For platform doesn't have support for GPE1, adding dummy entries here for common code : */ : #ifndef GPE1_STS : #define GPE1_STS(x) (0x0 + ((x) * 4)) : #endif : #ifndef GPE1_REG_MAX : #define GPE1_REG_MAX 0 : #endif : : #endif we should avoid defining it across multiple files. Please find a file in common code and implement it once. https://review.coreboot.org/c/coreboot/+/84104/comment/f12b9950_9aca6023?us… : PS7, Line 306: 0 this should be NULL ? as you are returning `char *` https://review.coreboot.org/c/coreboot/+/84104/comment/2af0f75f_c39193c1?us… : PS7, Line 341: pmc_clear_gpi_gpe0_status can I request you to perform this renaming as part of the base CL and mention the motivation about why are you changing the GPE to GPE0 https://review.coreboot.org/c/coreboot/+/84104/comment/d262a2c9_188d8864?us… : PS7, Line 379: gpe_sts check the NULL pointer at line 381 https://review.coreboot.org/c/coreboot/+/84104/comment/6fb2799a_3581cc98?us… : PS7, Line 381: int i; drop https://review.coreboot.org/c/coreboot/+/84104/comment/bdab28f7_9c847597?us… : PS7, Line 383: i ```int i``` https://review.coreboot.org/c/coreboot/+/84104/comment/71a5b78f_9b9b9232?us… : PS7, Line 393: int i; same https://review.coreboot.org/c/coreboot/+/84104/comment/84dfcf5b_6839ebb9?us… : PS7, Line 396: sts_arr = missing NULL check ? https://review.coreboot.org/c/coreboot/+/84104/comment/1f4d14fc_79017452?us… : PS7, Line 406: if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) { WDYT ``` if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) return; uint32_t gpe1_sts[GPE1_REG_MAX]; reset_std_gpe1_status(gpe1_sts); print_std_gpe1_sts(gpe1_sts); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 09:31:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Jamie Ryu <jamie.m.ryu(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: drivers/spi: Stop using a variable-length array
by Nico Huber (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Arthur Heymans, Elyes Haouas, Felix Held, Julius Werner. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84059?usp=email ) Change subject: drivers/spi: Stop using a variable-length array ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: @jwerner@chromium.org remember this todo? :D We suspect an earlier reverted version of this patch had only problems with SMM, but would be nice to have it tested on something non-x86 as well. Do you have anything at hand? -- To view, visit https://review.coreboot.org/c/coreboot/+/84059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I157ecec69c049ead06467b0328efd7d1a09bd268 Gerrit-Change-Number: 84059 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 30 Aug 2024 09:29:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: drivers/spi: Stop using a variable-length array
by Nico Huber (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Arthur Heymans, Elyes Haouas, Felix Held. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84059?usp=email ) Change subject: drivers/spi: Stop using a variable-length array ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: @felix-coreboot@felixheld.de could you give this a shot on a modern AMD system? -- To view, visit https://review.coreboot.org/c/coreboot/+/84059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I157ecec69c049ead06467b0328efd7d1a09bd268 Gerrit-Change-Number: 84059 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 30 Aug 2024 09:25:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Update verb table
by Subrata Banik (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Jian Tong, Karthik Ramasubramanian, Shelley Chen. Subrata Banik has posted comments on this change by Jian Tong. ( https://review.coreboot.org/c/coreboot/+/83920?usp=email ) Change subject: mb/google/brox/var/lotso: Update verb table ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83920/comment/b9b8f16b_98ffd112?us… : PS1, Line 9: Update verb table provided by Realtek on 20240710 : for SPK SNR adjustment. : can you please reflow the commit msg to meet < 72 char -- To view, visit https://review.coreboot.org/c/coreboot/+/83920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4f03d09010efa7e32713b2697d5832255f64317 Gerrit-Change-Number: 83920 Gerrit-PatchSet: 1 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 09:19:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/fatcat: Add Panther Lake SOC support
by Saurabh Mishra (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Ashish Kumar Mishra, Cliff Huang, Felix Held, Jérémy Compostella, Paul Menzel, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email ) Change subject: mb/google/fatcat: Add Panther Lake SOC support ...................................................................... Patch Set 133: (1 comment) File src/mainboard/google/fatcat/mainboard.c: https://review.coreboot.org/c/coreboot/+/83419/comment/47526f92_b8bdb1b9?us… : PS118, Line 19: struct soc_intel_pantherlake_config > Hi Subrata, sure. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Gerrit-Change-Number: 83419 Gerrit-PatchSet: 133 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Aug 2024 09:19:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Shuo Liu (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 17: (3 comments) File src/soc/intel/snowridge/acpi/ith.asl: https://review.coreboot.org/c/coreboot/+/83321/comment/908cd94b_46a8e677?us… : PS17, Line 2: if this is not referred, clean it? maybe to clean to a minimal asl set? File src/soc/intel/snowridge/acpi/uncore.asl: https://review.coreboot.org/c/coreboot/+/83321/comment/18ec163e_dd82e4b0?us… : PS17, Line 10: #include "pch_irqs.asl" can you put pch_irq.asl to southcluster.asl? https://review.coreboot.org/c/coreboot/+/83321/comment/44c32595_01e094c1?us… : PS17, Line 14: Scope (\_SB.PC00) { can you put this to dsdt.asl? -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 17 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 30 Aug 2024 09:04:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit August 2024