coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
by Shuo Liu (Code Review) 30 Aug '24

30 Aug '24

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[L] Change in coreboot[main]: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
by Shuo Liu (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83322?usp=email ) Change subject: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge ...................................................................... Patch Set 19: (7 comments) File src/mainboard/intel/frost_creek/acpi/mainboard.asl: https://review.coreboot.org/c/coreboot/+/83322/comment/294c57b7_b50ec74a?us… : PS19, Line 10: Name(_PRW, Package(){0x1d, 0x05}) S3 is supported? File src/mainboard/intel/frost_creek/acpi/platform.asl: https://review.coreboot.org/c/coreboot/+/83322/comment/1768bfb7_a4e14e0e?us… : PS19, Line 3: // IO-Trap at 0x800. This is the ACPI->SMI communication interface. the scope is \SB? File src/mainboard/intel/frost_creek/board.fmd: https://review.coreboot.org/c/coreboot/+/83322/comment/1227fd27_aef7169a?us… : PS19, Line 2: BIOS@0x01400000 0x00C00000 { can you define the first 20M as a place holder (e.g. IFD, ME, acc firmware)? https://review.coreboot.org/c/coreboot/+/83322/comment/9392709c_9837b9f9?us… : PS19, Line 7: COREBOOT(CBFS)@0x51200 0x00baee00 bases could be omitted here if no explicit alignment reqs. File src/mainboard/intel/frost_creek/gpio.inc: https://review.coreboot.org/c/coreboot/+/83322/comment/27d94368_4803c419?us… : PS19, Line 112: SNR_PAD_CFG_STRUCT0( update the alignments? File src/mainboard/intel/frost_creek/romstage.c: https://review.coreboot.org/c/coreboot/+/83322/comment/a5720af6_7d3005ed?us… : PS19, Line 20: uint32_t boardid = board_id(); do we still need board_id here? https://review.coreboot.org/c/coreboot/+/83322/comment/d56fb308_344e9761?us… : PS19, Line 51: for (lane = 0; lane < BL_MAX_FIA_LANES; lane++) { can you comment here? -- To view, visit https://review.coreboot.org/c/coreboot/+/83322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013 Gerrit-Change-Number: 83322 Gerrit-PatchSet: 19 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 30 Aug 2024 08:57:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Update GPE0 routing
by Ren Kuo (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Karthik Ramasubramanian, Marx Wang, Marx Wang, Nick Vaccaro, Subrata Banik. Ren Kuo has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84124?usp=email ) Change subject: mb/google/brox/jubilant: Update GPE0 routing ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brox/variants/jubilant/overridetree.cb: https://review.coreboot.org/c/coreboot/+/84124/comment/eb163547_d590fb59?us… : PS4, Line 25: register "pmc_gpe0_dw1" = "GPP_F" > > > if wake sources are scattered across more than 3 GPIO bank then you can use GPIO Tier 1 register […] File a bug to discussion: https://partnerissuetracker.corp.google.com/issues/362692376 -- To view, visit https://review.coreboot.org/c/coreboot/+/84124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 Gerrit-Change-Number: 84124 Gerrit-PatchSet: 5 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marx Wang <marx.wang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 08:53:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Update GPE0 routing
by Ren Kuo (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Karthik Ramasubramanian, Marx Wang, Marx Wang, Nick Vaccaro. Hello Bob Moragues, Karthik Ramasubramanian, Kenneth Chan, Marx Wang, Marx Wang, Nick Vaccaro, Subrata Banik, Tyler Wang, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84124?usp=email to look at the new patch set (#5). Change subject: mb/google/brox/jubilant: Update GPE0 routing ...................................................................... mb/google/brox/jubilant: Update GPE0 routing Update GPE0 routing for FP wake up source. BUG=b:363166664 TEST= Build jubilant firmware Check event log of FP wake up source $ elogtool list Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/overridetree.cb 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/84124/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 Gerrit-Change-Number: 84124 Gerrit-PatchSet: 5 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marx Wang <marx.wang(a)intel.com> Gerrit-Attention: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_info
by Arthur Heymans (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Angel Pons, Nico Huber. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84056?usp=email ) Change subject: drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_info ...................................................................... Patch Set 13: (1 comment) Patchset: PS6: > 100% agree Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84056?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d5a9a86dbb91a5505891a30c6e9072b1b4dfc92 Gerrit-Change-Number: 84056 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 08:51:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_info
by Arthur Heymans (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Angel Pons, Arthur Heymans, Nico Huber. Hello Angel Pons, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84056?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_info ...................................................................... drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_info GCC LTO found this. Change-Id: I2d5a9a86dbb91a5505891a30c6e9072b1b4dfc92 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/gma/gma-gfx_init.ads M src/include/framebuffer_info.h M src/lib/edid_fill_fb.c 3 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/84056/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/84056?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d5a9a86dbb91a5505891a30c6e9072b1b4dfc92 Gerrit-Change-Number: 84056 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: arch/x86/bootblock.ld: Simplify the linker script
by Arthur Heymans (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella. Hello Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84045?usp=email to look at the new patch set (#22). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/x86/bootblock.ld: Simplify the linker script ...................................................................... arch/x86/bootblock.ld: Simplify the linker script Instead of doing arithmetic operations to optimize out a few bytes in the linker script, hardcode most sections. This might increase program size a little. Change-Id: I278c7199a25b7af77247c0e4fe52fe1c81c17a2a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/bootblock.ld 1 file changed, 14 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/84045/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/84045?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I278c7199a25b7af77247c0e4fe52fe1c81c17a2a Gerrit-Change-Number: 84045 Gerrit-PatchSet: 22 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[XS] Change in coreboot[main]: [IS_THIS_NEEDED?]arch/x86/Kconfig: Fix LTO linking
by Arthur Heymans (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Angel Pons, Arthur Heymans, Jérémy Compostella. Hello Angel Pons, Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84049?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: [IS_THIS_NEEDED?]arch/x86/Kconfig: Fix LTO linking ...................................................................... [IS_THIS_NEEDED?]arch/x86/Kconfig: Fix LTO linking Somehow the trick for older binutils is also needed for LTO linking. Change-Id: I1a6a5ef9dc6d824fa108681689a69df3faefd3c6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/84049/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/84049?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a6a5ef9dc6d824fa108681689a69df3faefd3c6 Gerrit-Change-Number: 84049 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 64: (1 comment) File src/soc/intel/pantherlake/include/soc/pmc.h: https://review.coreboot.org/c/coreboot/+/83798/comment/0cbf3333_82661bc4?us… : PS38, Line 26: (1 << 18) > Error ref. : https://qa.coreboot. […] Fix: https://review.coreboot.org/c/coreboot/+/84142/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 64 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 08:38:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Subrata Banik (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 7: (4 comments) File src/soc/intel/common/block/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/84103/comment/6af78459_cda92e90?us… : PS5, Line 87: devices. > sure. will do this. thx. Acknowledged File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/9e0c716b_9344f78c?us… : PS5, Line 29: GPE1_STS > Subrata, > > One thing left is the case when GPE1 is support but we intend to use GPE0 with this Kconfig not selected, the defines here is duplicated. I add the #ifndef to support this case in the next patchset. Pls let me know what you think. thx. > > I also run into the same GPE1 defines issue on the next CL https://review.coreboot.org/c/coreboot/+/84104. I am doing the same for pmclib.c there. if you don't intend to use GPE1 then ideally you don't select `SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1` there could be two config - SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1 - SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 where `_USE_GPE1` should be dependent on `_HAVE_GPE1`. Assume a case, when PTL SoC selects `SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1` and Main board can still choose not to use GPE1 hence, main board won't be choosing `_USE_GPE1`. Does that make sense to you ? to support this design, please use below logic. ``` #if !CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1) /* NOTE: For SoCs that don't have support for GPE1, add a dummy entry here for common code */ #define GPE1_STS(x) (0x0 + ((x) * 4)) #define GPE1_REG_MAX 0 #endif ``` File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/50a29b42_1e50c3d7?us… : PS7, Line 121: if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) { ``` fadt->gpe1_blk = GPE1_STS(0) ? (pmbase + GPE1_STS(0)) : GPE1_STS(0); ``` we don't need redundant guarding using if/else around Kconfig. Therefore, the suggested above code changes. Also, it's better to assign gpe1_blk to zero for SoC platform that doesn't have support for GPE1. https://review.coreboot.org/c/coreboot/+/84103/comment/ea58f07b_39278535?us… : PS7, Line 128: 8 can you please explain why this is `8` I assume this is like `GPE1_REG_MAX` aka 4 and then two sets like STATUS and ENABLE bits? -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 08:35:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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coreboot-gerrit August 2024