coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Shuo Liu (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 17: (7 comments) File src/soc/intel/snowridge/Kconfig: https://review.coreboot.org/c/coreboot/+/83321/comment/70467ac5_0d6f6afc?us… : PS15, Line 42: select FSP_T_XIP > Should FSP_S_XIP be selected as well? Close this, in this SoC, FSP_S is put at fixed location in flash but still relocatable. File src/soc/intel/snowridge/chip.c: https://review.coreboot.org/c/coreboot/+/83321/comment/b168d107_dfa82a4b?us… : PS15, Line 418: } will the common pci codes do this again? File src/soc/intel/snowridge/sriov.c: https://review.coreboot.org/c/coreboot/+/83321/comment/0fde3d77_e8cfcf8d?us… : PS15, Line 13: void pciexp_vf_read_resources(struct device *dev) if coreboot only enables PF, can the OS still work? https://review.coreboot.org/c/coreboot/+/83321/comment/02c19b57_df091187?us… : PS15, Line 76: resource->flags |= IORESOURCE_ABOVE_4G; is this VF req or RCiEP req? File src/soc/intel/snowridge/systemagent.c: https://review.coreboot.org/c/coreboot/+/83321/comment/0ee754a8_75ee264e?us… : PS15, Line 17: *size = CONFIG_ECAM_MMCONF_LENGTH; > Shouldn't be probed by BAR access? CONFIG_ECAM_MMCONF_LENGTH => should be aligned with the probed value https://review.coreboot.org/c/coreboot/+/83321/comment/e15ee06b_b0f80e9d?us… : PS15, Line 32: void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt) resource_cnt -> resource_index? https://review.coreboot.org/c/coreboot/+/83321/comment/538fb3df_1f550413?us… : PS15, Line 56: I PCIe MMCFG BAR? -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 17 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 30 Aug 2024 07:45:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/teliks: Force audio mute to avoid screen flick
by Eric Lai (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Jianeng Ceng, Kapil Porwal, Nick Vaccaro, Rishika Raj. Eric Lai has posted comments on this change by Jianeng Ceng. ( https://review.coreboot.org/c/coreboot/+/84137?usp=email ) Change subject: mb/google/nissa/var/teliks: Force audio mute to avoid screen flick ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff488f6844c717ef24069c7176e7b8dfb07d8abc Gerrit-Change-Number: 84137 Gerrit-PatchSet: 2 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 07:43:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/teliks: Add fw_config fields for rtl8852be
by Eric Lai (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Jianeng Ceng, Kapil Porwal, Nick Vaccaro, Rishika Raj. Eric Lai has posted comments on this change by Jianeng Ceng. ( https://review.coreboot.org/c/coreboot/+/84138?usp=email ) Change subject: mb/google/nissa/var/teliks: Add fw_config fields for rtl8852be ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84138?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6ba641c23cce7f1253022c9bb78b986b323bcaa Gerrit-Change-Number: 84138 Gerrit-PatchSet: 2 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 07:43:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: drivers/spi: Stop using a variable-length array
by Arthur Heymans (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Elyes Haouas, Nico Huber. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84059?usp=email ) Change subject: drivers/spi: Stop using a variable-length array ...................................................................... Patch Set 2: (2 comments) File src/drivers/spi/spi_flash.c: https://review.coreboot.org/c/coreboot/+/84059/comment/23fc0876_09460d2e?us… : PS1, Line 136: strain the stack > strain *on* the stack Done https://review.coreboot.org/c/coreboot/+/84059/comment/9af3ea86_50644e93?us… : PS1, Line 137: static u8 buff[4 + MAX_FLASH_CMD_DATA_SIZE]; > `+ ADDR_MOD` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I157ecec69c049ead06467b0328efd7d1a09bd268 Gerrit-Change-Number: 84059 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 30 Aug 2024 07:41:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[S] Change in coreboot[main]: drivers/spi: Stop using a variable-length array
by Arthur Heymans (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Arthur Heymans, Elyes Haouas, Nico Huber. Hello Angel Pons, Elyes Haouas, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84059?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Code-Review+2 by Elyes Haouas, Verified+1 by build bot (Jenkins) Change subject: drivers/spi: Stop using a variable-length array ...................................................................... drivers/spi: Stop using a variable-length array Only the call in `spi_flash_cmd_write_page_program` uses non-constant values for the array length. However, the value for `data_len` has an upper bound: `flash->page_size` is set to `1U << vi->page_size_shift` which depends on the flash chip vendor info, and the largest value it can currently have is 8. Thus, the maximum page size is currently 256. Define the `MAX_FLASH_CMD_DATA_SIZE` macro to place an upper bound on the amount of data that can be written in one command. Then, use this value to allocate a fixed-size buffer in `spi_flash_cmd_write`. Also, add a check to prevent buffer overflow problems. Finally, ensure that the `spi_flash_cmd_write_page_program` function always writes no more than 256 bytes of data when using the `spi_flash_cmd_write` function. The buffer is placed in .bss so that it does not increase stack usage in some use cases. Tested on Asrock B85M Pro4 (Winbond W25Q64FV), MRC cache still works. Repost of https://review.coreboot.org/c/coreboot/+/50480 with 'static' so that the buffer is in bss. Change-Id: I157ecec69c049ead06467b0328efd7d1a09bd268 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/spi/spi_flash.c M src/drivers/spi/spi_flash_internal.h 2 files changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/84059/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I157ecec69c049ead06467b0328efd7d1a09bd268 Gerrit-Change-Number: 84059 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add MCUPM firmware v1.0
by Jarried Lin (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Yidi Lin. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/84029?usp=email ) Change subject: soc/mediatek/mt8196: Add MCUPM firmware v1.0 ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/blobs/+/84029/comment/734485c4_d2bd2134?usp=e… : PS4, Line 9: Add mcupm.bin initial version > nit: Missing `.` at the end. Done -- To view, visit https://review.coreboot.org/c/blobs/+/84029?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I639eb495e3499e0ed886368e6581031baaec0b9d Gerrit-Change-Number: 84029 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 07:38:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add MCUPM firmware v1.0
by Jarried Lin (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Jarried Lin, Yidi Lin. Hello Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/84029?usp=email to look at the new patch set (#5). Change subject: soc/mediatek/mt8196: Add MCUPM firmware v1.0 ...................................................................... soc/mediatek/mt8196: Add MCUPM firmware v1.0 Add mcupm.bin initial version. TEST=NA BUG=b:317009620 Change-Id: I639eb495e3499e0ed886368e6581031baaec0b9d Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md A soc/mediatek/mt8196/mcupm.bin A soc/mediatek/mt8196/mcupm.bin.md5 A soc/mediatek/mt8196/mcupm_release_notes.txt 4 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/29/84029/5 -- To view, visit https://review.coreboot.org/c/blobs/+/84029?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I639eb495e3499e0ed886368e6581031baaec0b9d Gerrit-Change-Number: 84029 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add dpm.pm and dpm.dm version 1.0
by Yidi Lin (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/84028?usp=email ) Change subject: soc/mediatek/mt8196: Add dpm.pm and dpm.dm version 1.0 ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/blobs/+/84028?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I91c34f105992f38aa42521f7e11f42a4ccb81856 Gerrit-Change-Number: 84028 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 07:37:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: nb/intel/sandybridge: Fix uninitialised variable
by Arthur Heymans (Code Review) 30 Aug '24

30 Aug '24

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84055?usp=email ) Change subject: nb/intel/sandybridge: Fix uninitialised variable ...................................................................... nb/intel/sandybridge: Fix uninitialised variable GCC with LTO caught this. Change-Id: I9f78b9973729bdedb40bd63b8989e94c9c498814 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84055 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 8a8bd83..d5e1a7c 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -340,7 +340,7 @@ int me_uma_size, cbmem_was_inited, fast_boot, err; ramctr_timing ctrl; spd_ddr3_raw_data spds[4]; - size_t mrc_size; + size_t mrc_size = 0; ramctr_timing *ctrl_cached = NULL; timestamp_add_now(TS_INITRAM_START); -- To view, visit https://review.coreboot.org/c/coreboot/+/84055?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f78b9973729bdedb40bd63b8989e94c9c498814 Gerrit-Change-Number: 84055 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: arch/x86/car.ld: Fix overlapping regions
by Arthur Heymans (Code Review) 30 Aug '24

30 Aug '24

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84048?usp=email ) Change subject: arch/x86/car.ld: Fix overlapping regions ...................................................................... arch/x86/car.ld: Fix overlapping regions The fspm_rc_heap is already accounted for inside .car.data. Some linkers like LLD do not like overlapping regions so remove this. Change-Id: I058bd6790afc313e06f1888e5b783d97b7e93b1e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84048 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/arch/x86/car.ld 1 file changed, 0 insertions(+), 5 deletions(-) Approvals: Shuo Liu: Looks good to me, but someone else must approve build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index f99304f..9d54037 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -113,11 +113,6 @@ _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start) - CONFIG_FSP_T_RESERVED_SIZE; -. = _car_region_start; -.car.fspm_rc_heap . (NOLOAD) : { - . += CONFIG_FSP_M_RC_HEAP_SIZE; -} - . = _car_region_end; .car.mrc_var . (NOLOAD) : { . += CONFIG_DCACHE_RAM_MRC_VAR_SIZE; -- To view, visit https://review.coreboot.org/c/coreboot/+/84048?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I058bd6790afc313e06f1888e5b783d97b7e93b1e Gerrit-Change-Number: 84048 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit August 2024