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Change subject: soc/intel/common/block/imc: Add Integrated Memory Controller driver
......................................................................
Patch Set 15:
(2 comments)
File src/soc/intel/common/block/smbus/smbuslib.c:
https://review.coreboot.org/c/coreboot/+/83320/comment/e7a5c4d8_4ed18b98?us… :
PS15, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
maybe you can add a separate patch to rename smbuslib.c to spdlib.c, and to rename spd.c to spd_access.c
https://review.coreboot.org/c/coreboot/+/83320/comment/bbad2b99_9f502af0?us… :
PS15, Line 9: __weak int spd_read_byte(u8 slave_addr, u8 bus_addr)
no need to have week here
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Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email )
Change subject: soc/intel/common/block/pmc: Fix compilation error with MS4V=BIT(18)
......................................................................
soc/intel/common/block/pmc: Fix compilation error with MS4V=BIT(18)
If MS4V is defined using the BIT macro such in as in BIT(18) for
instance, it is replaced with (1ul << 18). When the
pmc_clear_pmcon_sts_pci() function performs the binary not operation
on MS4V, it turns a value fitting in 32-bit into a value requiring a
64-bit. This commit cast ~MS4V to uint32_t to resolve the following
compilation error observed with pantherlake code.
Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/common/block/pmc/pmclib.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84142/1
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index 7650fe4..557e90e 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -688,7 +688,7 @@
if (!dev)
return;
- pci_and_config32(dev, GEN_PMCON_A, ~MS4V);
+ pci_and_config32(dev, GEN_PMCON_A, (uint32_t)~MS4V);
}
/*
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Change subject: soc/intel/common/block/imc: Add Integrated Memory Controller driver
......................................................................
Patch Set 15:
(2 comments)
File src/soc/intel/common/block/smbus/smbuslib.c:
https://review.coreboot.org/c/coreboot/+/83320/comment/914d690e_2d951411?us… :
PS15, Line 70: if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) {
if (!IMC && ...) and comment that IMC doesn't support i2c eeprom
File src/southbridge/intel/common/smbus.c:
https://review.coreboot.org/c/coreboot/+/83320/comment/195c1dd1_cc7bbfa8?us… :
PS15, Line 465: if (CONFIG(SOUTHBRIDGE_INTEL_I82371EB) || CONFIG(SOUTHBRIDGE_INTEL_I82801DX) ||
this is for pch smbus and we should not change here.
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Change subject: mb/google/nissa/var/riven: Update GPIO pins for 3rd dmic support
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84141/comment/838778d9_4c1d2b55?us… :
PS1, Line 13: TEST=Boot to OS and verify 3rd dmic working properly.
> google/riven to OS and ...
Done. Thanks
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Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84141?usp=email
to look at the new patch set (#2).
Change subject: mb/google/nissa/var/riven: Update GPIO pins for 3rd dmic support
......................................................................
mb/google/nissa/var/riven: Update GPIO pins for 3rd dmic support
When world-facing camera is absent, coreboot need to enable
GPP_R6(DMIC_WCAM_CLK) and GPP_R7(DMIC_WCAM_DATA) for 3rd dmic support
BUG=b:333973512
TEST=Boot google/riven to OS and verify 3rd dmic working properly.
Change-Id: I6c8780ce37b5d3987f5cdf6e6e6d0b4896b33230
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/riven/fw_config.c
1 file changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/84141/2
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Change subject: soc/intel/common/block/imc: Add Integrated Memory Controller driver
......................................................................
Patch Set 15:
(4 comments)
File src/soc/intel/common/block/imc/Kconfig:
https://review.coreboot.org/c/coreboot/+/83320/comment/1fc0e855_22d4709f?us… :
PS3, Line 4: bool
> IMC is originally added by commit f377fafd941a44252c4c7527ba08f798d222e7ff to support Intel Xeon Pro […]
IMO this is the 1st active IMC implementation, we can postpone the consideration of being reused by others now.
File src/soc/intel/common/block/include/intelblocks/imc.h:
https://review.coreboot.org/c/coreboot/+/83320/comment/cae172f7_700e4b14?us… :
PS15, Line 10:
can these be static? or to static what ever could be?
File src/soc/intel/common/block/smbus/smbuslib.c:
https://review.coreboot.org/c/coreboot/+/83320/comment/530d04a0_6974586e?us… :
PS3, Line 10: {
> Sorry for the typo, I mean in `coreboot/src/soc/intel/common/block/smbus/Makefile. […]
sure, let us remove the weak here
https://review.coreboot.org/c/coreboot/+/83320/comment/2752a7a4_d5cb61dc?us… :
PS3, Line 96: if (!CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) && blk->addr_map[i] == 0) {
> The addr_map[i] is finally used as the address of the slave. […]
add a common block here might be helpful
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Change subject: mb/google/nissa/var/riven: Update GPIO pins for 3rd dmic support
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84141/comment/0756f037_8a534a1f?us… :
PS1, Line 13: TEST=Boot to OS and verify 3rd dmic working properly.
google/riven to OS and ...
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Change subject: mb/google/nissa/var/riven: Update GPIO pins for 3rd dmic support
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/ovis/var/deku: Remove DSP setting
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84139/comment/dcd8b4f3_8cd244d5?us… :
PS1, Line 14: TEST=emerge-ovis coreboot
: check dev beep works
> Normally Chromebox devices have audio, Deku is a special device which does not have codec and amplifier. In this case, shall we keep it enabled in Ovis baseboard and just disable it in Deku.
that make sense but as we know that Ovis specifically designed for Deku and not a general reference design. Hence, it makes more sense to drop DSP UPD from both Ovis/Deku.
WDYT?
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