coreboot-gerrit August 2024

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[XS] Change in coreboot[main]: soc/intel/apl: Fix building with clang & LTO
by Arthur Heymans (Code Review) 30 Aug '24

30 Aug '24

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84047?usp=email ) Change subject: soc/intel/apl: Fix building with clang & LTO ...................................................................... soc/intel/apl: Fix building with clang & LTO LTO does not like that assert on a constant, so use the more appropriate static assertion. Change-Id: I52094ec825fcec56a9b9fb6b9abc58644c2bf9cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84047 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/apollolake/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index f710883..d8d11a0 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -319,7 +319,7 @@ mrc_cache_current_mmap_leak(MRC_VARIABLE_DATA, version, NULL); - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + _Static_assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED), "Boot device not memory mapped"); fsp_version = version; } -- To view, visit https://review.coreboot.org/c/coreboot/+/84047?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52094ec825fcec56a9b9fb6b9abc58644c2bf9cb Gerrit-Change-Number: 84047 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/pmclib.c: Work around compiler bug -Werror=stringop-overread
by Arthur Heymans (Code Review) 30 Aug '24

30 Aug '24

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84042?usp=email ) Change subject: soc/intel/pmclib.c: Work around compiler bug -Werror=stringop-overread ...................................................................... soc/intel/pmclib.c: Work around compiler bug -Werror=stringop-overread On xeon-sp this is a zero length array. With GCC LTO this triggers the stringop-overread warning. To work around this change the signature of the function from an array to a pointer. Change-Id: Ieee6e9bddc4e738eb560dd0e69dc3087ac9f5da6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84042 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/pmc/pmclib.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Nico Huber: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 7650fe4..0b3863a 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -94,7 +94,7 @@ CBMEM_CREATION_HOOK(migrate_power_state); static void print_num_status_bits(int num_bits, uint32_t status, - const char *const bit_names[]) + const char *const *bit_names) { int i; -- To view, visit https://review.coreboot.org/c/coreboot/+/84042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieee6e9bddc4e738eb560dd0e69dc3087ac9f5da6 Gerrit-Change-Number: 84042 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Configure DDR5 Physical channel width to 64
by Arthur Heymans (Code Review) 30 Aug '24

30 Aug '24

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84085?usp=email ) Change subject: soc/intel/meteorlake: Configure DDR5 Physical channel width to 64 ...................................................................... soc/intel/meteorlake: Configure DDR5 Physical channel width to 64 A DDR5 DIMM internally has two channels each of width 32 bit. But the total physical channel width is 64 bit. This is the same fix as be5dc3daa "soc/intel/alderlake: Configure DDR5 Physical channel width to 64" Building with GCC LTO cought this buffer overflow when assigning SPD addresses to a buffer. Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84085 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/meminit.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/meteorlake/meminit.c b/src/soc/intel/meteorlake/meminit.c index 32ab358..dae175f 100644 --- a/src/soc/intel/meteorlake/meminit.c +++ b/src/soc/intel/meteorlake/meminit.c @@ -8,7 +8,7 @@ #define LPX_PHYSICAL_CH_WIDTH 16 #define LPX_CHANNELS CHANNEL_COUNT(LPX_PHYSICAL_CH_WIDTH) -#define DDR5_PHYSICAL_CH_WIDTH 32 +#define DDR5_PHYSICAL_CH_WIDTH 64 /* 32*2 */ #define DDR5_CHANNELS CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH) static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg) -- To view, visit https://review.coreboot.org/c/coreboot/+/84085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545 Gerrit-Change-Number: 84085 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: ext_stage_cache: Make sure variables are initialized
by Arthur Heymans (Code Review) 30 Aug '24

30 Aug '24

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84040?usp=email ) Change subject: ext_stage_cache: Make sure variables are initialized ...................................................................... ext_stage_cache: Make sure variables are initialized GCC LTO incorrectly warns about this it seems. This also exits gracefully from stage-cache code if no smm region is found. Change-Id: Ib1851295646258e97c489dc7402b9df3fcf092c1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84040 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/smm/tseg_region.c M src/lib/ext_stage_cache.c 2 files changed, 7 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c index 413d5fc..90e61dc 100644 --- a/src/cpu/x86/smm/tseg_region.c +++ b/src/cpu/x86/smm/tseg_region.c @@ -53,8 +53,6 @@ sub_size = ied_size; break; default: - *start = 0; - *size = 0; return -1; } @@ -65,11 +63,10 @@ void stage_cache_external_region(void **base, size_t *size) { - if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) { + *base = NULL; + *size = 0; + if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) printk(BIOS_ERR, "No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } } void smm_list_regions(void) diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 462a635..427c9c3 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -16,6 +16,8 @@ imd = &imd_stage_cache; stage_cache_external_region(&base, &size); + if (base == NULL || size == 0) + return; imd_handle_init(imd, (void *)(size + (uintptr_t)base)); printk(BIOS_DEBUG, "External stage cache:\n"); @@ -32,6 +34,8 @@ imd = &imd_stage_cache; stage_cache_external_region(&base, &size); + if (base == NULL || size == 0) + return; imd_handle_init(imd, (void *)(size + (uintptr_t)base)); if (imd_recover(imd)) printk(BIOS_DEBUG, "Unable to recover external stage cache.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/84040?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1851295646258e97c489dc7402b9df3fcf092c1 Gerrit-Change-Number: 84040 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/cavium: Fix non matching types
by Arthur Heymans (Code Review) 30 Aug '24

30 Aug '24

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84084?usp=email ) Change subject: soc/cavium: Fix non matching types ...................................................................... soc/cavium: Fix non matching types There is no struct device *dev equivalent of this function. Clang LTO warns about mismatching types. Change-Id: I22c8c9b9f350c53469a5d386db211969c8a41cf0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84084 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/cavium/cn81xx/ecam0.c M src/soc/cavium/common/include/soc/ecam.h 2 files changed, 1 insertion(+), 7 deletions(-) Approvals: Nico Huber: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index ff3e709..db5090f 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -181,7 +181,7 @@ dev_path(dev)); return -1; } - bar = ecam0_get_bar_val(dev, bar_idx); + bar = ecam0_get_bar_val(pcidev_bdf(dev), bar_idx); if (!bar) { printk(BIOS_ERR, "%s: Failed to find MSI-X bar\n", dev_path(dev)); diff --git a/src/soc/cavium/common/include/soc/ecam.h b/src/soc/cavium/common/include/soc/ecam.h index b0f10dc..534c165 100644 --- a/src/soc/cavium/common/include/soc/ecam.h +++ b/src/soc/cavium/common/include/soc/ecam.h @@ -3,14 +3,8 @@ #ifndef __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM_H #define __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM_H -#ifdef __SIMPLE_DEVICE__ #include <device/pci_type.h> uint64_t ecam0_get_bar_val(pci_devfn_t dev, u8 bar); -#else -#include <device/device.h> - -uint64_t ecam0_get_bar_val(struct device *dev, u8 bar); -#endif #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/84084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22c8c9b9f350c53469a5d386db211969c8a41cf0 Gerrit-Change-Number: 84084 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add SSPM firmware v1.0
by Yidi Lin (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/84027?usp=email ) Change subject: soc/mediatek/mt8196: Add SSPM firmware v1.0 ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/blobs/+/84027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I180421be4077198edd4bcabc2d25ed52a3abedda Gerrit-Change-Number: 84027 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 07:05:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/cherry: Complete PCIe reset in romstage
by Yidi Lin (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang. Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/84118?usp=email ) Change subject: mb/google/cherry: Complete PCIe reset in romstage ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84118/comment/03d13de9_ba71518c?us… : PS6, Line 13: [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now > Let's break the long lines for readability. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Gerrit-Change-Number: 84118 Gerrit-PatchSet: 7 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 07:03:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mb/google/cherry: Complete PCIe reset in romstage
by Yidi Lin (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yidi Lin. Hello Hung-Te Lin, Jianjun Wang, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84118?usp=email to look at the new patch set (#7). Change subject: mb/google/cherry: Complete PCIe reset in romstage ...................................................................... mb/google/cherry: Complete PCIe reset in romstage De-assert PERST# at romstage to reduce the waiting time in ramstage. Before ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` After ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST# [DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries) ``` BUG=none TEST=boot from NVMe Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/cherry/romstage.c M src/soc/mediatek/mt8195/Makefile.mk 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/84118/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/84118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Gerrit-Change-Number: 84118 Gerrit-PatchSet: 7 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com>

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[XS] Change in coreboot[main]: mb/google/cherry: Complete PCIe reset in romstage
by Yu-Ping Wu (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/84118?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/cherry: Complete PCIe reset in romstage ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84118/comment/a2347640_abc7cfcd?us… : PS6, Line 13: [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now Let's break the long lines for readability. -- To view, visit https://review.coreboot.org/c/coreboot/+/84118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Gerrit-Change-Number: 84118 Gerrit-PatchSet: 6 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 06:56:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add MCUPM firmware v1.0
by Yu-Ping Wu (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/84029?usp=email ) Change subject: soc/mediatek/mt8196: Add MCUPM firmware v1.0 ...................................................................... Patch Set 4: Code-Review+2 Verified+1 (1 comment) Commit Message: https://review.coreboot.org/c/blobs/+/84029/comment/2fc54f10_402d842f?usp=e… : PS4, Line 9: Add mcupm.bin initial version nit: Missing `.` at the end. -- To view, visit https://review.coreboot.org/c/blobs/+/84029?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I639eb495e3499e0ed886368e6581031baaec0b9d Gerrit-Change-Number: 84029 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 06:54:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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coreboot-gerrit August 2024