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Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
......................................................................
soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block.
This will include GPE1 blocks to FADT with their info.
BUG=362310295
TEST=boot to OS and check that FADT table include GPE1.
FADT should have:
GPE1 Block Address : 00001810
GPE1 Block Length : 18
GPE1 Base Offset : 80
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e
---
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/include/intelblocks/pmclib.h
3 files changed, 34 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/84103/10
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Change subject: soc/intel/mtl: Hook up GMA ACPI brightness controls
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/meteorlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/82729/comment/76098397_a501cf46?us… :
PS2, Line 398: INTEL_GMA_BCLV_OFFSET
I'm curious, where exactly are these backlight offset configs used? Are there any subsequent changes planned?
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Change subject: mb/google/brox/jubilant: Modify FP IRQ pin
......................................................................
Patch Set 8:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84124/comment/a4d40445_ff4116a5?us… :
PS8, Line 7: Modify FP IRQ pin
… to GPP_D13
https://review.coreboot.org/c/coreboot/+/84124/comment/22fe0d03_256ef293?us… :
PS8, Line 9: from HW change
Add some revision (from the schematics?)?
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Change subject: mb/google/brox/jubilant: I2C signal tuning
......................................................................
Patch Set 1:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84143/comment/48179bb9_6fded4b8?us… :
PS1, Line 7: I2C signal tuning
Please look through `git log --oneline` on how to write the summary (also for I2C tuning).
https://review.coreboot.org/c/coreboot/+/84143/comment/3485ccdc_a05c0f5c?us… :
PS1, Line 10: HW requirement
… of ….
https://review.coreboot.org/c/coreboot/+/84143/comment/f1d1c662_d9b27fa2?us… :
PS1, Line 10: 250ns
The diff does more than this?
https://review.coreboot.org/c/coreboot/+/84143/comment/b2adb135_62c5ae3f?us… :
PS1, Line 14: Measure the i2c signal on jubilant to meet spec
Please include your measurements.
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Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
......................................................................
Patch Set 9:
(3 comments)
File src/soc/intel/common/block/acpi/Kconfig:
https://review.coreboot.org/c/coreboot/+/84103/comment/882ba0c5_7af80620?us… :
PS9, Line 83: Requires define GPE1_STS(0) and GPE1_REG_MAX from the SOC header.
Please add a blank line above.
https://review.coreboot.org/c/coreboot/+/84103/comment/d905b4d4_e5ca9a3c?us… :
PS9, Line 89: for
to
https://review.coreboot.org/c/coreboot/+/84103/comment/2a970817_e0418e86?us… :
PS9, Line 90: that publishes
… that publish … or … publishing …
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Change subject: drivers/smmstore: add ability to write to whole flash
......................................................................
Patch Set 6:
(1 comment)
File src/include/smmstore.h:
https://review.coreboot.org/c/coreboot/+/83424/comment/f4c64c83_fb746b32?us… :
PS6, Line 25: SMMSTORE_CMD_USE_FULL_FLASH
Is that an official name? Should it be `…ALLOW_ACCESS_TO_FULL_FLASH` or so?
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Change subject: Documentation/drivers/smmstorev2.md: describe capsule update API
......................................................................
Patch Set 6:
(1 comment)
File Documentation/drivers/smmstorev2.md:
https://review.coreboot.org/c/coreboot/+/83426/comment/4799ce0f_05a078f4?us… :
PS6, Line 227: but because coreboot has no way of enforcing it being used might
: as well leave it to a reboot
I do not fully parse “enforcing it being used might as well”.
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Change subject: vendorcode/intel: allow selecting EDK headers manually
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83738/comment/40bc7db0_d641ab84?us… :
PS3, Line 7: vendorcode/intel
Why is this Intel specific?
https://review.coreboot.org/c/coreboot/+/83738/comment/0ee79579_85678dee?us… :
PS3, Line 10: This prevents enabling those options
: for boards which don't require EDK bindings.
Please elaborate and give examples.
File src/vendorcode/intel/Kconfig:
https://review.coreboot.org/c/coreboot/+/83738/comment/50bf8125_f9f96a46?us… :
PS3, Line 37: Set of UEFI headers to use
Maybe:
> Select UEFI header version
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Change subject: tree: Use boolean for "eist_enable"
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/83575/comment/e4f478fa_221095ee?us… :
PS5, Line 470: true:Enabled, false:Disabled
> since `bool` is self-explanatory, this could be dropped
Thx
Please see https://review.coreboot.org/c/coreboot/+/84152
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