coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

1 participants
3528 discussions

[L] Change in coreboot[main]: include/commonlib/sot.h: Add SOT structs
by Lean Sheng Tan (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Benjamin Doron, Elyes Haouas, Martin L Roth, Maximilian Brune, Patrick Rudolph, Sean Rhodes. Lean Sheng Tan has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/77882?usp=email ) Change subject: include/commonlib/sot.h: Add SOT structs ...................................................................... Patch Set 14: (1 comment) File src/commonlib/include/commonlib/sot.h: https://review.coreboot.org/c/coreboot/+/77882/comment/e5cea76b_054b6f9c?us… : PS13, Line 7: <commonlib/bsd/compiler.h> > any thoughts @ehaouas@noos. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/77882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f006318a15556f97da286dc032c58ccb7993e4 Gerrit-Change-Number: 77882 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 27 Jun 2024 13:41:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[main]: include/commonlib/sot.h: Add SOT structs
by Lean Sheng Tan (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Benjamin Doron, Elyes Haouas, Martin L Roth, Maximilian Brune, Patrick Rudolph, Sean Rhodes. Lean Sheng Tan has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/77882?usp=email ) Change subject: include/commonlib/sot.h: Add SOT structs ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f006318a15556f97da286dc032c58ccb7993e4 Gerrit-Change-Number: 77882 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 27 Jun 2024 13:40:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/cmn/cse: Conditionally disable ME status reporting
by Subrata Banik (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Eric Lai, Nick Vaccaro, Pranava Y N. Hello Eric Lai, Nick Vaccaro, Pranava Y N, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83233?usp=email to look at the new patch set (#2). Change subject: soc/intel/cmn/cse: Conditionally disable ME status reporting ...................................................................... soc/intel/cmn/cse: Conditionally disable ME status reporting This patch disables the ME status reporting functionality (dump_me_status, print_me_fw_version) in the CSE driver when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is defined. This is likely intended for platforms or configurations where the CSE communication is only limited to payload. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5e360408a7847968117df475ff244d79ceafa23f Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_spec.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/83233/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83233?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e360408a7847968117df475ff244d79ceafa23f Gerrit-Change-Number: 83233 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: Introduce a coreboot Control Block (CCB)
by Simon Glass (Code Review) 27 Jun '24

27 Jun '24

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[XS] Change in coreboot[main]: soc/intel/cmn/cse: Conditionally disable ME status reporting
by Subrata Banik (Code Review) 27 Jun '24

27 Jun '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83233?usp=email ) Change subject: soc/intel/cmn/cse: Conditionally disable ME status reporting ...................................................................... soc/intel/cmn/cse: Conditionally disable ME status reporting This patch introduces a build-time configuration option to disable the ME status reporting functionality (dump_me_status, print_me_fw_version) in the CSE driver when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is defined. This is likely intended for platforms or configurations where the CSE communication is only limited to payload. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5e360408a7847968117df475ff244d79ceafa23f Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/cse/cse_spec.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/83233/1 diff --git a/src/soc/intel/common/block/cse/cse_spec.c b/src/soc/intel/common/block/cse/cse_spec.c index 74155cd..d3c611d 100644 --- a/src/soc/intel/common/block/cse/cse_spec.c +++ b/src/soc/intel/common/block/cse/cse_spec.c @@ -115,5 +115,7 @@ #endif } +#if !CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD) BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/83233?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e360408a7847968117df475ff244d79ceafa23f Gerrit-Change-Number: 83233 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: Introduce a coreboot Control Block (CCB)
by Arthur Heymans (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Angel Pons, Felix Held, Julius Werner, Jérémy Compostella, Karthik Ramasubramanian, Paul Menzel, Simon Glass, Simon Glass. Arthur Heymans has posted comments on this change by Simon Glass. ( https://review.coreboot.org/c/coreboot/+/77712?usp=email ) Change subject: Introduce a coreboot Control Block (CCB) ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: > My objection is the -2. I am happy to address comments but there is no point if the whole thing is blocked. > > The tricky thing here is reading the CCB early enough that it can affect the first console output. Putting the CCB in the bootblock is simpler on some boards since it doesn't require reading the SPI flash very early in bootblock (before console). So reading SPI flash is basically free on x86. On others ofc it isn't, changing the bootblock post boot on other ARCH is often tricky as there is some header with checksum that needs updating. So I can't speak for Julius but it looks like the problem is that there are already quite a few mechanism for configuration post build and that adding a new one fragments the ecosystem. Your problem with those existing ones is that they happen too late in the boot process and that some messages get printed before that code is reached. Do I assume correct that the slowness of uart for those first few messages is the main problem? It looks like it's more a problem with defaults and how the codeflow works and not so much with configuration mechanisms. So the rationale behind setting up console first, before other mechanisms can be used/reached for setting options is that you want a console to debug those mechanism. Maybe the solution is not a simpler mechanism like CBB but a buildtime (Kconfig) option to move console init a bit later? Setting up a SPI controller to use for instance VPD is not that much more complicated than setting up uart. Alternatively and maybe better: Only print to memory initially. Other (slow) consoles are disabled at the start. Once existing mechanisms for post build configuration can be reached and the config options is to enable those slow uarts, print out what is inside the memory buffer to uart. -- To view, visit https://review.coreboot.org/c/coreboot/+/77712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e946b33035a493e833500351a0483761252613 Gerrit-Change-Number: 77712 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Jun 2024 11:52:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Simon Glass <sjg(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[L] Change in coreboot[main]: Introduce a coreboot Control Block (CCB)
by Simon Glass (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Julius Werner, Jérémy Compostella, Karthik Ramasubramanian, Paul Menzel, Simon Glass. Simon Glass has posted comments on this change by Simon Glass. ( https://review.coreboot.org/c/coreboot/+/77712?usp=email ) Change subject: Introduce a coreboot Control Block (CCB) ...................................................................... Patch Set 10: (7 comments) Patchset: PS10: > > -- here is where CBFS turns up I suppose: […] The goal of CCB (for console) is to allow all output to be produced, or none. It isn't trying to suppress just 'some' output, or allow some output, but not other output. I understand about keeping things simple, but we can't really use this feature if it doesn't work for all output. It would just be a half-baked solution and people would not use it. Commit Message: https://review.coreboot.org/c/coreboot/+/77712/comment/1fa39094_6cf68bf8?us… : PS2, Line 7: Post-build control of serial > This change adds the CCB subsystem, *and* it also uses the CCB subsystem to allow post-build control […] I split these into two commits File src/arch/x86/car.ld: https://review.coreboot.org/c/coreboot/+/77712/comment/6df06943_8b057bba?us… : PS10, Line 45: CCB(., 0x10) > This file only affects x86 devices (excluding AMD). […] Do timestamps suffer from the same issue? What is the solution to resolve this? File src/console/Kconfig: https://review.coreboot.org/c/coreboot/+/77712/comment/0be5523f_046abcd0?us… : PS10, Line 433: default y > Any feature for runtime control of console behavior should probably be based on loglevel as it was s […] I have a plan to expand this to allow loglevel to be changed at runtime. But this CL is the smallest useful implementation, so I am starting here. File src/console/init.c: https://review.coreboot.org/c/coreboot/+/77712/comment/5b1179db_55af4420?us… : PS5, Line 45: return CONSOLE_LOG_FAST; > Could we leave that until later? Yes, I believe we could add something to control that too Acknowledged File src/lib/ccb.c: https://review.coreboot.org/c/coreboot/+/77712/comment/8037e9ed_fc923005?us… : PS3, Line 8: struct ccb ccb_static __attribute__((section(".init"))) = { > Not that I can see. […] Acknowledged File src/lib/hardwaremain.c: https://review.coreboot.org/c/coreboot/+/77712/comment/4a5ba60a_521e98a9?us… : PS10, Line 449: cbmem_initialize(); > Moving cbmem_initialize() above console_init() makes it impossible to debug CBMEM initialization han […] But in that case you wouldn't set the console to silent, would you? -- To view, visit https://review.coreboot.org/c/coreboot/+/77712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e946b33035a493e833500351a0483761252613 Gerrit-Change-Number: 77712 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Jun 2024 11:32:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Simon Glass <sjg(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Simon Glass <sjg(a)chromium.org>

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[S] Change in coreboot[main]: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space
by Patrick Rudolph (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82264?usp=email ) Change subject: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space ...................................................................... Patch Set 8: (1 comment) File src/cpu/x86/mtrr/mtrr.c: https://review.coreboot.org/c/coreboot/+/82264/comment/1e045bc6_d8c128e5?us… : PS3, Line 203: soc_update_physical_address_space > Yes, exactly. […] There seem to be no specification when it comes to MTRRs. In theory you could not only fill UC holes, but grow the memory ranges to optimize the MTRRs. Growing is possible when not limited by another region. It should allow to minimize MTRR usage as well as you could align base and size to the next power of two. -- To view, visit https://review.coreboot.org/c/coreboot/+/82264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b4be85e79007fd1ccf5882de4dfeaeacd98a4db Gerrit-Change-Number: 82264 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 27 Jun 2024 11:27:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[L] Change in coreboot[main]: Introduce a coreboot Control Block (CCB)
by Simon Glass (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Jérémy Compostella, Karthik Ramasubramanian, Paul Menzel. Simon Glass has posted comments on this change by Simon Glass. ( https://review.coreboot.org/c/coreboot/+/77712?usp=email ) Change subject: Introduce a coreboot Control Block (CCB) ...................................................................... Patch Set 10: (3 comments) Patchset: PS10: > > So long as you can access the flash early in the bootblock, then that can work. […] My objection is the -2. I am happy to address comments but there is no point if the whole thing is blocked. The tricky thing here is reading the CCB early enough that it can affect the first console output. Putting the CCB in the bootblock is simpler on some boards since it doesn't require reading the SPI flash very early in bootblock (before console). File src/arch/x86/postcar.c: https://review.coreboot.org/c/coreboot/+/77712/comment/22bcf9dc_d2a401a8?us… : PS10, Line 21: console_init(); > This is done with a reason: so you can debug cbmem init. Right...so how should we proceed? cbmem_initialize() does produce console output. CCB won't affect that unless you manually ask it to be silent by updating the CCB in the ROM File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/77712/comment/7852857c_b5a6d4fe?us… : PS10, Line 112: const char *value; > is this used? Yes, see: param.value = optarg -- To view, visit https://review.coreboot.org/c/coreboot/+/77712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e946b33035a493e833500351a0483761252613 Gerrit-Change-Number: 77712 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Jun 2024 11:25:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Simon Glass <sjg(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[L] Change in coreboot[main]: Introduce a coreboot Control Block (CCB)
by Arthur Heymans (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Angel Pons, Felix Held, Jérémy Compostella, Karthik Ramasubramanian, Paul Menzel, Simon Glass. Arthur Heymans has posted comments on this change by Simon Glass. ( https://review.coreboot.org/c/coreboot/+/77712?usp=email ) Change subject: Introduce a coreboot Control Block (CCB) ...................................................................... Patch Set 10: (3 comments) Patchset: PS10: > So long as you can access the flash early in the bootblock, then that can work. Reading the FMAP is not trivial and takes a small amount of time. > > We discussed making a 'fixed offset' in the flash an option. > > I would like to move forward with this...can someone perhaps persuade Julius to remove the -2 ? Maybe address his comments? I'm confused. FMAP is basically a fixed offset in the flash. How is it more complicated than having a different data structure in at a fixed offset? File src/arch/x86/postcar.c: https://review.coreboot.org/c/coreboot/+/77712/comment/97c9ca06_1d7a0538?us… : PS10, Line 21: console_init(); This is done with a reason: so you can debug cbmem init. File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/77712/comment/ba6a2083_e4413811?us… : PS10, Line 112: const char *value; is this used? -- To view, visit https://review.coreboot.org/c/coreboot/+/77712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e946b33035a493e833500351a0483761252613 Gerrit-Change-Number: 77712 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Jun 2024 11:16:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Simon Glass <sjg(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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coreboot-gerrit June 2024