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Change subject: mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flash
......................................................................
Patch Set 8: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82555/comment/f3c9255c_998b471c?us… :
PS4, Line 18: 8
> Apparently this is configurable in newer QEMU. […]
Done
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Change subject: mb/qemu-{i440fx,q35}: reduce default ROM size to 8 MiB
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Patch Set 5: Code-Review+2
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Change subject: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space
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Patch Set 8: Code-Review+2
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Change subject: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space
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Patch Set 8:
(1 comment)
File src/cpu/x86/mtrr/mtrr.c:
https://review.coreboot.org/c/coreboot/+/82264/comment/f38808f4_9ed60f32?us… :
PS3, Line 203: soc_update_physical_address_space
> Raised https://review.coreboot.org/c/coreboot/+/82974, but still with opens. […]
Sorry, this snipped is hard to understand.
It sounds like the MTRR code should honour the MMIO window as reported by the domain:
```
[0m[SPEW ] DOMAIN: 00000000 resource base 200000000000 size 0 align 0 gran 0 limit 200fffffffff flags 40080200 index 3[0m
```
but it does not since it doesn't have IORESOURCE_ASSIGNED set.
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Change subject: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space
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Patch Set 8:
(1 comment)
Patchset:
PS8:
let us try to move ahead for this as well?
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Change subject: acpi: Add support for DRHD size reporting
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Patch Set 17:
(1 comment)
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/82429/comment/129344c2_d4c79d5c?us… :
PS16, Line 1855: u32
> Just to match size_t which could be 64bit when coreboot is 64bit, though there are asserts to make s […]
Let us go with this if not too confusing :-)?
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Change subject: acpi: Add support for DRHD size reporting
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Patch Set 17:
(1 comment)
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/82429/comment/4f7c9406_7ba99219?us… :
PS16, Line 1855: u32
> I mean the change to `_64`.
Just to match size_t which could be 64bit when coreboot is 64bit, though there are asserts to make sure a meaningful size will not exceeding 32bits, a.k.a., a double safe setting.
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Change subject: Makefile.mk: Use one line per *_common flag
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Set Ready For Review
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Change subject: drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC
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Patch Set 5:
(1 comment)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/81790/comment/00dd7725_825d3b98?us… :
PS5, Line 561: wbem->revision
do we need similar revision check implemented for BT in previous CL ?
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Change subject: drivers/wifi: Support Bluetooth Regulator Domain Settings
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Patch Set 4:
(2 comments)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/83200/comment/75ca8508_43fcd779?us… :
PS4, Line 528: package_size = 1 + 1 + 1 + table_size;
nit: a comment here to explain why `1+1+1+table_size`
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PS4, Line 535: i
nit: int i
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