coreboot-gerrit June 2024

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[XS] Change in coreboot[main]: [TEST PATCH] Skip all CSE communication for Rex/MTL
by Subrata Banik (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83232?usp=email ) Change subject: [TEST PATCH] Skip all CSE communication for Rex/MTL ...................................................................... Patch Set 1: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4dc96e2e400ebed81a3750a471b0f6df1e7c5023 Gerrit-Change-Number: 83232 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Jun 2024 11:03:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: [TEST PATCH] Skip all CSE communication for Rex/MTL
by Subrata Banik (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83232?usp=email ) Change subject: [TEST PATCH] Skip all CSE communication for Rex/MTL ...................................................................... [TEST PATCH] Skip all CSE communication for Rex/MTL Change-Id: I4dc96e2e400ebed81a3750a471b0f6df1e7c5023 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/Kconfig M src/soc/intel/meteorlake/Kconfig 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/83232/1 diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 9ee0bc0..9447e1e 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -29,8 +29,6 @@ select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT select SOC_INTEL_CSE_LITE_SKU - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 - select SOC_INTEL_CSE_SEND_EOP_ASYNC config BOARD_GOOGLE_BASEBOARD_OVIS def_bool n diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 622d35f..e8d33a8 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -91,7 +91,7 @@ select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_IOC select SOC_INTEL_CRASHLOG - select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_CSE_LITE_PSR if !MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_IOE_DIE_SUPPORT @@ -107,6 +107,8 @@ select X86_CLFLUSH_CAR select X86_INIT_NEED_1_SIPI select INTEL_KEYLOCKER + select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD + select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD help Intel Meteorlake support. Mainboards should specify the SoC type using the `SOC_INTEL_METEORLAKE_*` options instead -- To view, visit https://review.coreboot.org/c/coreboot/+/83232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4dc96e2e400ebed81a3750a471b0f6df1e7c5023 Gerrit-Change-Number: 83232 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[XS] Change in coreboot[main]: drivers/intel/ish: Skip ISH version call if CSE sync is done by payload
by Subrata Banik (Code Review) 27 Jun '24

27 Jun '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83231?usp=email ) Change subject: drivers/intel/ish: Skip ISH version call if CSE sync is done by payload ...................................................................... drivers/intel/ish: Skip ISH version call if CSE sync is done by payload This patch skips the ISH firmware version print when CSE sync is done by payload. The payload is responsible to dump the ISH version as ISH version resides into the CSE boot partition table. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I1895a4d3c44838a9cc6380912f09aa4f0e6687bd Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/ish/ish.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/83231/1 diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index 7d332e1..1ab6a0a 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -50,6 +50,9 @@ static void intel_ish_get_version(void) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + struct cse_specific_info *info = cbmem_find(CBMEM_ID_CSE_INFO); if (info == NULL) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/83231?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1895a4d3c44838a9cc6380912f09aa4f0e6687bd Gerrit-Change-Number: 83231 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/cmn/cse: Skip CSE version call if sync is done by payload
by Subrata Banik (Code Review) 27 Jun '24

27 Jun '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83230?usp=email ) Change subject: soc/intel/cmn/cse: Skip CSE version call if sync is done by payload ...................................................................... soc/intel/cmn/cse: Skip CSE version call if sync is done by payload This patch skips the CSE firmware version print when CSE sync is done by payload. The payload is responsible to dump the CSE version. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I1a9e5583c79ebd81291a4b3ae24529b4582502cb Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/83230/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d78b8a0..32ca399 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1418,6 +1418,9 @@ static void intel_cse_get_rw_version(void) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + struct cse_specific_info *info = cbmem_find(CBMEM_ID_CSE_INFO); if (info == NULL) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/83230?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a9e5583c79ebd81291a4b3ae24529b4582502cb Gerrit-Change-Number: 83230 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/cmn/cse: Modify dependency on CSE EOP configs
by Subrata Banik (Code Review) 27 Jun '24

27 Jun '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83229?usp=email ) Change subject: soc/intel/cmn/cse: Modify dependency on CSE EOP configs ...................................................................... soc/intel/cmn/cse: Modify dependency on CSE EOP configs Refactor CSE lite End-of-Post (EOP) configs to support the alternative of sending CSE communication from the payload. When the SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD config is selected, coreboot will skip initiating CSE EOP operations and rely on the payload CSE driver implementation. The following configs are modified to ensure coreboot skips CSE communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled: - SOC_INTEL_CSE_SEND_EOP_EARLY - SOC_INTEL_CSE_SEND_EOP_LATE - SOC_INTEL_CSE_SEND_EOP_ASYNC - SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD BUG=b:305898363 TEST=Able to build google/rex. Change-Id: Ia6b616163d02be8d637b134fd3728c391fc63c90 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 3 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/83229/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 966726e..d8d2456 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -97,7 +97,7 @@ config SOC_INTEL_CSE_SEND_EOP_EARLY bool "CSE send EOP early" - depends on SOC_INTEL_COMMON_BLOCK_CSE + depends on SOC_INTEL_COMMON_BLOCK_CSE && !SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD help Use this config to send End Of Post (EOP) earlier through SoC code in order to reduce time required to send EOP and getting CSE response. @@ -106,7 +106,7 @@ config SOC_INTEL_CSE_SEND_EOP_LATE bool - depends on SOC_INTEL_COMMON_BLOCK_CSE + depends on SOC_INTEL_COMMON_BLOCK_CSE && !SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD help Use this config to send End Of Post (EOP) late (even after CSE `final` operation) using boot state either `BS_PAYLOAD_BOOT` or `BS_PAYLOAD_LOAD` from common code @@ -119,7 +119,7 @@ config SOC_INTEL_CSE_SEND_EOP_ASYNC bool - depends on SOC_INTEL_COMMON_BLOCK_CSE + depends on SOC_INTEL_COMMON_BLOCK_CSE && !SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD depends on !SOC_INTEL_CSE_SEND_EOP_LATE depends on !SOC_INTEL_CSE_SEND_EOP_EARLY help @@ -139,10 +139,6 @@ config SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD bool depends on SOC_INTEL_COMMON_BLOCK_CSE - depends on !SOC_INTEL_CSE_SEND_EOP_LATE - depends on !SOC_INTEL_CSE_SEND_EOP_EARLY - depends on !SOC_INTEL_CSE_SEND_EOP_ASYNC - depends on !DISABLE_HECI1_AT_PRE_BOOT help Use this config to specify that the payload will send the End Of Post (EOP) instead of coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/83229?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6b616163d02be8d637b134fd3728c391fc63c90 Gerrit-Change-Number: 83229 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: intelvbtupgrader: Add a tool to upgrade VBT files to newer versions
by Angel Pons (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Matt DeVillier, Nicholas Chin, Paul Menzel, Vladimir Serbinenko. Angel Pons has posted comments on this change by Vladimir Serbinenko. ( https://review.coreboot.org/c/coreboot/+/82722?usp=email ) Change subject: intelvbtupgrader: Add a tool to upgrade VBT files to newer versions ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82722/comment/a56ac16d_d998a2b3?us… : PS7, Line 8: > the latest TGL FSP update broke all pre-v250 VBTs, so any TGL boards in the tree not specifically up […] TL;DR same problem, different approach. -- To view, visit https://review.coreboot.org/c/coreboot/+/82722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie677403898b7b8ab9f57ad77668155bb55188769 Gerrit-Change-Number: 82722 Gerrit-PatchSet: 8 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Jun 2024 11:00:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Vladimir Serbinenko <phcoder(a)gmail.com>

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[M] Change in coreboot[main]: intelvbtupgrader: Add a tool to upgrade VBT files to newer versions
by Angel Pons (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Nicholas Chin, Paul Menzel, Vladimir Serbinenko. Angel Pons has posted comments on this change by Vladimir Serbinenko. ( https://review.coreboot.org/c/coreboot/+/82722?usp=email ) Change subject: intelvbtupgrader: Add a tool to upgrade VBT files to newer versions ...................................................................... Patch Set 8: (8 comments) File util/README.md: https://review.coreboot.org/c/coreboot/+/82722/comment/b41b6724_7eb03fda?us… : PS8, Line 67: * __intelvbtupgrader__ - Upgrade VBT to newer version Specify the language this tool is written in: ```suggestion * __intelvbtupgrader__ - Upgrade VBT to newer version `C` ``` File util/intelvbtupgrader/Makefile: https://review.coreboot.org/c/coreboot/+/82722/comment/1e70f240_48bc4d7b?us… : PS8, Line 1: ## nit: drop this line File util/intelvbtupgrader/intelvbtupgrader.c: https://review.coreboot.org/c/coreboot/+/82722/comment/7bfcbc41_94900560?us… : PS8, Line 92: VERSION Is this the input version or the output version? https://review.coreboot.org/c/coreboot/+/82722/comment/eb98dab5_85f9c63a?us… : PS8, Line 93: return 0; Return non-zero from error paths to indicate failure? https://review.coreboot.org/c/coreboot/+/82722/comment/a3642af0_1c2f3f31?us… : PS8, Line 108: fin = fopen(argv[1], "rb"); No error checking? I also see that not all paths close the files. https://review.coreboot.org/c/coreboot/+/82722/comment/5597a3b8_0e756cf0?us… : PS8, Line 113: printf("Head version not 1.00\n"); Why is this a problem? https://review.coreboot.org/c/coreboot/+/82722/comment/ef058bb4_00afc215?us… : PS8, Line 123: printf("invalid BDB offset\n"); Perhaps print the invalid value? ```suggestion printf("invalid BDB offset %u\n", head.bdb_offset); ``` https://review.coreboot.org/c/coreboot/+/82722/comment/99d3da69_e91d8fa0?us… : PS8, Line 138: printf("Already at target or higher. Nothing to do\n"); Could this check be done earlier? I would avoid writing a partial output file if there's no need. -- To view, visit https://review.coreboot.org/c/coreboot/+/82722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie677403898b7b8ab9f57ad77668155bb55188769 Gerrit-Change-Number: 82722 Gerrit-PatchSet: 8 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Jun 2024 10:59:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: Introduce a coreboot Control Block (CCB)
by Simon Glass (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Jérémy Compostella, Karthik Ramasubramanian, Paul Menzel. Simon Glass has posted comments on this change by Simon Glass. ( https://review.coreboot.org/c/coreboot/+/77712?usp=email ) Change subject: Introduce a coreboot Control Block (CCB) ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: > haven't really gotten around looking at the code, but thought a bit more about a possible clean impl […] So long as you can access the flash early in the bootblock, then that can work. Reading the FMAP is not trivial and takes a small amount of time. We discussed making a 'fixed offset' in the flash an option. I would like to move forward with this...can someone perhaps persuade Julius to remove the -2 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/77712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e946b33035a493e833500351a0483761252613 Gerrit-Change-Number: 77712 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Jun 2024 10:58:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/intel/cmn/cse: Modify dependency on CSE lite configs
by Subrata Banik (Code Review) 27 Jun '24

27 Jun '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83228?usp=email ) Change subject: soc/intel/cmn/cse: Modify dependency on CSE lite configs ...................................................................... soc/intel/cmn/cse: Modify dependency on CSE lite configs Refactor CSE lite configs (specifically CSE sync related) to support the alternative of sending CSE communication from the payload. When the SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD config is selected, coreboot will skip initiating CSE sync operations and rely on the payload CSE driver implementation. The following configs are modified to ensure coreboot skips CSE communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled: - SOC_INTEL_CSE_LITE_PSR - SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY - SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE - SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5ddaf6e29949231db84b14bf7ea2d34866bb8e6c Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/83228/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index edc7e23..966726e 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -169,7 +169,7 @@ config SOC_INTEL_CSE_LITE_PSR bool default n - depends on SOC_INTEL_CSE_LITE_SKU + depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE help Select this config if Platform Service Record(PSR) is supported by the platform. This @@ -298,7 +298,7 @@ config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY def_bool n - depends on SOC_INTEL_CSE_LITE_SKU + depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD help Mainboard user to select this Kconfig in order to capture pre-cpu reset boot performance telemetry data. @@ -320,13 +320,14 @@ config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE bool default !SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE - depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW + depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW && !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD help Use default flow of CSE FW Update in romstage when uncompressed ME_RW blobs are used. config SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE bool default n + depends on !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD help Use this option if CSE RW update needs to be triggered during RAMSTAGE. -- To view, visit https://review.coreboot.org/c/coreboot/+/83228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ddaf6e29949231db84b14bf7ea2d34866bb8e6c Gerrit-Change-Number: 83228 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space
by Shuo Liu (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82264?usp=email ) Change subject: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space ...................................................................... Patch Set 8: (1 comment) File src/cpu/x86/mtrr/mtrr.c: https://review.coreboot.org/c/coreboot/+/82264/comment/7ea869b4_b8ae6d0c?us… : PS3, Line 203: soc_update_physical_address_space > Sorry, this snipped is hard to understand. […] Yes, exactly. MTRR codes only covers the ASSIGNED resources instead of the whole window, it would satisfy coreboot's own usage but will leave segmentation. https://github.com/coreboot/coreboot/blob/main/src/device/device_util.c#L594 -- To view, visit https://review.coreboot.org/c/coreboot/+/82264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b4be85e79007fd1ccf5882de4dfeaeacd98a4db Gerrit-Change-Number: 82264 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 27 Jun 2024 08:42:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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coreboot-gerrit June 2024