coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: commonlib/device_tree: Improve node and property allocation speed
by Julius Werner (Code Review) 26 Jun '24

26 Jun '24

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83208?usp=email ) Change subject: commonlib/device_tree: Improve node and property allocation speed ...................................................................... commonlib/device_tree: Improve node and property allocation speed Now that the device tree code has been made available in libpayload, we should reintroduce the node and property allocation optimization for libpayload's memory allocator that was originally dropped when porting this code from depthcharge to coreboot. On a Qualcomm SC7180 unflattening a normal ChromeOS kernel device tree, this saves roughly ~145ms. The total scratch space used is about ~1350 nodes and ~5200 properties, so we leave a little room to grow with the constants hardcoded here. Change-Id: I0f4d80a8b750febfb069b32ef47304ccecdc35af Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83208 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/commonlib/device_tree.c 1 file changed, 41 insertions(+), 8 deletions(-) Approvals: Maximilian Brune: Looks good to me, approved build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c index f70aaf7..0ec6ea9 100644 --- a/src/commonlib/device_tree.c +++ b/src/commonlib/device_tree.c @@ -25,6 +25,41 @@ #define FDT_MAX_MEMORY_REGIONS 16 // should be a good enough upper bound /* + * libpayload's malloc() has a linear allocation complexity, which means that it + * degrades massively if we make a few thousand small allocations. Preventing + * that problem with a custom scratchpad is well-worth some increase in BSS + * size (64 * 2000 + 40 * 10000 = ~1/2 MB). + */ + +/* Try to give these a healthy margin above what the average kernel DT needs. */ +#define LP_ALLOC_NODE_SCRATCH_COUNT 2000 +#define LP_ALLOC_PROP_SCRATCH_COUNT 10000 + +static struct device_tree_node *alloc_node(void) +{ +#ifndef __COREBOOT__ + static struct device_tree_node scratch[LP_ALLOC_NODE_SCRATCH_COUNT]; + static int counter = 0; + + if (counter < ARRAY_SIZE(scratch)) + return &scratch[counter++]; +#endif + return xzalloc(sizeof(struct device_tree_node)); +} + +static struct device_tree_property *alloc_prop(void) +{ +#ifndef __COREBOOT__ + static struct device_tree_property scratch[LP_ALLOC_PROP_SCRATCH_COUNT]; + static int counter = 0; + + if (counter < ARRAY_SIZE(scratch)) + return &scratch[counter++]; +#endif + return xzalloc(sizeof(struct device_tree_property)); +} + +/* * Functions for picking apart flattened trees. */ @@ -625,14 +660,14 @@ return 0; offset += size; - struct device_tree_node *node = xzalloc(sizeof(*node)); + struct device_tree_node *node = alloc_node(); *new_node = node; node->name = name; struct fdt_property fprop; last = &node->properties; while ((size = fdt_next_property(blob, offset, &fprop))) { - struct device_tree_property *prop = xzalloc(sizeof(*prop)); + struct device_tree_property *prop = alloc_prop(); prop->prop = fprop; if (dt_prop_is_phandle(prop)) { @@ -1003,9 +1038,7 @@ if (!create) return NULL; - found = calloc(1, sizeof(*found)); - if (!found) - return NULL; + found = alloc_node(); found->name = strdup(*path); if (!found->name) return NULL; @@ -1333,7 +1366,7 @@ } } - prop = xzalloc(sizeof(*prop)); + prop = alloc_prop(); list_insert_after(&prop->list_node, &node->properties); prop->prop.name = name; prop->prop.data = data; @@ -1847,7 +1880,7 @@ continue; } } else { - dst_prop = xzalloc(sizeof(*dst_prop)); + dst_prop = alloc_prop(); list_insert_after(&dst_prop->list_node, &dst->properties); } @@ -1866,7 +1899,7 @@ } if (!dst_node) { - dst_node = xzalloc(sizeof(*dst_node)); + dst_node = alloc_node(); *dst_node = *src_node; list_insert_after(&dst_node->list_node, &dst->children); } else { -- To view, visit https://review.coreboot.org/c/coreboot/+/83208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f4d80a8b750febfb069b32ef47304ccecdc35af Gerrit-Change-Number: 83208 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: lib/string: use size_t for local variable in strncmp
by Matt DeVillier (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Felix Held. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/83224?usp=email ) Change subject: lib/string: use size_t for local variable in strncmp ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe35d3741bc6d8a16a3bad3ec27aafc30745d931 Gerrit-Change-Number: 83224 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Jun 2024 23:52:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: lib/string: change return types to match C standard
by Matt DeVillier (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Arthur Heymans, Felix Held, Martin L Roth. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/83223?usp=email ) Change subject: lib/string: change return types to match C standard ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83223?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ff612e2eee4f556f5c572b02cbc600ca411ae20 Gerrit-Change-Number: 83223 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Jun 2024 23:52:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: lib/string: change parameter types to match C standard
by Matt DeVillier (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Arthur Heymans, Felix Held, Martin L Roth. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/83222?usp=email ) Change subject: lib/string: change parameter types to match C standard ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83222?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I485e45e18232a0d1625d4d626f923ec66cfbe4a2 Gerrit-Change-Number: 83222 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Jun 2024 23:51:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/corsola/var/wugtrio: Add LCE_LMFBX101117480 MIPI panel
by Yu-Ping Wu (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Hung-Te Lin, Xuxin Xiong, Yang Wu, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/83221?usp=email ) Change subject: mb/google/corsola/var/wugtrio: Add LCE_LMFBX101117480 MIPI panel ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83221?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I863e172400ffb26b5c9c240a21d15c6a2240b4ad Gerrit-Change-Number: 83221 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 23:35:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/mipi: Add support for LCE_LMFBX101117480 panel
by Yidi Lin (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Xuxin Xiong, Yang Wu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/83220?usp=email ) Change subject: drivers/mipi: Add support for LCE_LMFBX101117480 panel ...................................................................... Patch Set 1: (1 comment) File src/drivers/mipi/panel-LCE_LMFBX101117480.c: https://review.coreboot.org/c/coreboot/+/83220/comment/24470d80_d0211c09?us… : PS1, Line 5: KD_KD101NE3_40TI this should be `LCE_LMFBX101117480` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83220?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60858109e4b07f720461e320212d7b197ec1130c Gerrit-Change-Number: 83220 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 23:20:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: src/lib: Add Kconfig variable for fw_config default value
by Jérémy Compostella (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Julius Werner, Subrata Banik, Wonkyu Kim. Jérémy Compostella has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83153?usp=email ) Change subject: src/lib: Add Kconfig variable for fw_config default value ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Could you add the motivation for this new Kconfig in the commit message ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9694433e01bdcd9ff1e550585c14ea7ccee020a3 Gerrit-Change-Number: 83153 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 26 Jun 2024 23:12:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC
by Jérémy Compostella (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Bob Moragues, Bora Guvendik, Cliff Huang, Eric Lai, Hannah Williams, Poornima Tom, Ravishankar Sarawadi, Subrata Banik, YH Lin, dinesh.sharma(a)intel.com. Jérémy Compostella has posted comments on this change by Poornima Tom. ( https://review.coreboot.org/c/coreboot/+/81790?usp=email ) Change subject: drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC ...................................................................... Patch Set 5: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81790/comment/05907e49_3710ca55?us… : PS2, Line 7: Wifi > driver/wifi? Done File src/drivers/wifi/generic/acpi.c: https://review.coreboot.org/c/coreboot/+/81790/comment/60555c4e_e479e572?us… : PS2, Line 486: WiFi320MHzPerMcc > avoid camelcase Done File src/include/sar.h: https://review.coreboot.org/c/coreboot/+/81790/comment/bb7ca870_9c68641f?us… : PS2, Line 58: enablement_11ax; > This CL is with respect to 320MHZ wifi bandwidth. So, is this relevant in this CL. […] Done https://review.coreboot.org/c/coreboot/+/81790/comment/05a3ef01_b5ff9bde?us… : PS2, Line 64: WiFi320MHzPerMcc > avoid camel case Done https://review.coreboot.org/c/coreboot/+/81790/comment/a4f40b9d_c2ba505a?us… : PS2, Line 65: __packed > any reason for using `packed`? The binary is packed and mixing uint8_t and uint32_t types. File src/vendorcode/google/chromeos/sar.c: https://review.coreboot.org/c/coreboot/+/81790/comment/3836c230_c65b94db?us… : PS2, Line 219: * > don't delete please Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Gerrit-Change-Number: 81790 Gerrit-PatchSet: 5 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dinesh.sharma(a)intel.com Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Dinesh Sharma <dinesh.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: dinesh.sharma(a)intel.com Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 22:56:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Poornima Tom <poornima.tom(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Bob Moragues <moragues(a)google.com>

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[L] Change in coreboot[main]: mb/google/fatcat: Add minimal code support for fatcat
by Felix Held (Code Review) 26 Jun '24

26 Jun '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83197?usp=email ) Change subject: mb/google/fatcat: Add minimal code support for fatcat ...................................................................... mb/google/fatcat: Add minimal code support for fatcat This patch adds initial code block required to build google/fatcat board with Intel Meteor Lake Silicon. Later after the initial board power-on is successful, we shall switch to Panther Lake silicon to build the google/fatcat reference design. BUG=b:347669091 TEST=Able to build the google/fatcat and able to hit power-on reset using Intel Meteor Lake SoC platform. Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- A src/mainboard/google/fatcat/Kconfig A src/mainboard/google/fatcat/Kconfig.name A src/mainboard/google/fatcat/Makefile.mk A src/mainboard/google/fatcat/board_info.txt A src/mainboard/google/fatcat/bootblock.c A src/mainboard/google/fatcat/chromeos-debug-fsp.fmd A src/mainboard/google/fatcat/chromeos.c A src/mainboard/google/fatcat/chromeos.fmd A src/mainboard/google/fatcat/dsdt.asl A src/mainboard/google/fatcat/ec.c A src/mainboard/google/fatcat/mainboard.c A src/mainboard/google/fatcat/romstage.c A src/mainboard/google/fatcat/smihandler.c A src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk A src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb A src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h A src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h A src/mainboard/google/fatcat/variants/baseboard/fatcat/memory.c A src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/fatcat/variants/fatcat/Makefile.mk A src/mainboard/google/fatcat/variants/fatcat/gpio.c A src/mainboard/google/fatcat/variants/fatcat/include/variant/ec.h A src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h 23 files changed, 710 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig new file mode 100644 index 0000000..2c6ddd2 --- /dev/null +++ b/src/mainboard/google/fatcat/Kconfig @@ -0,0 +1,108 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_GOOGLE_FATCAT_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_SPI_ACPI + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_SKUID + select GOOGLE_SMBIOS_MAINBOARD_VERSION + select HAVE_ACPI_TABLES + select I2C_TPM + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_DISABLE_STAGE_CACHE + select MAINBOARD_HAS_TPM2 + select MB_COMPRESS_RAMSTAGE_LZ4 + select PMC_IPC_ACPI_INTERFACE + select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT + select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 + select SOC_INTEL_CSE_SEND_EOP_ASYNC + +config BOARD_GOOGLE_BASEBOARD_FATCAT + def_bool n + select BOARD_GOOGLE_FATCAT_COMMON + select HAVE_SLP_S0_GATE + select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_IOE_DIE_SUPPORT + select SOC_INTEL_METEORLAKE_U_H + select SYSTEM_TYPE_LAPTOP + select TPM_GOOGLE_TI50 + +config BOARD_GOOGLE_MODEL_FATCAT + def_bool n + select BOARD_GOOGLE_BASEBOARD_FATCAT + +config BOARD_GOOGLE_FATCAT + select BOARD_GOOGLE_MODEL_FATCAT + select HAVE_X86_64_SUPPORT + select USE_X86_64_SUPPORT + +if BOARD_GOOGLE_FATCAT_COMMON + +config BASEBOARD_DIR + string + default "fatcat" + +config CHROMEOS + select EC_GOOGLE_CHROMEEC_SWITCHES + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_MANUAL_RECOVERY + select HAS_RECOVERY_MRC_CACHE + +config DEVICETREE + default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + default 512 + +# FIXME: update below code as per board schematics +config DRIVER_TPM_I2C_ADDR + hex + default 0x0 + +config DRIVER_TPM_I2C_BUS + hex + default 0x0 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS + +config HAVE_SLP_S0_GATE + def_bool n + +config MAINBOARD_DIR + default "google/fatcat" + +config MAINBOARD_FAMILY + string + default "Google_Fatcat" + +config MAINBOARD_PART_NUMBER + default "Fatcat" if BOARD_GOOGLE_FATCAT + +# FIXME: update as per board schematics +config TPM_TIS_ACPI_INTERRUPT + int + default 0 + +# FIXME: update as per board schematics +config UART_FOR_CONSOLE + int + default 0 + +config USE_PM_ACPI_TIMER + default n + +config VARIANT_DIR + string + default "fatcat" if BOARD_GOOGLE_MODEL_FATCAT + +config VBOOT + select VBOOT_LID_SWITCH + +endif # BOARD_GOOGLE_FATCAT_COMMON diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name new file mode 100644 index 0000000..ccf1f6d --- /dev/null +++ b/src/mainboard/google/fatcat/Kconfig.name @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +comment "Fatcat" + +config BOARD_GOOGLE_FATCAT + bool "-> Fatcat" diff --git a/src/mainboard/google/fatcat/Makefile.mk b/src/mainboard/google/fatcat/Makefile.mk new file mode 100644 index 0000000..11098e2 --- /dev/null +++ b/src/mainboard/google/fatcat/Makefile.mk @@ -0,0 +1,23 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-y += romstage.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-y += mainboard.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR)) + +subdirs-y += variants/baseboard/$(BASEBOARD_DIR) +subdirs-y += variants/$(VARIANT_DIR) + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/fatcat/board_info.txt b/src/mainboard/google/fatcat/board_info.txt new file mode 100644 index 0000000..3d09984 --- /dev/null +++ b/src/mainboard/google/fatcat/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Fatcat +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/fatcat/bootblock.c b/src/mainboard/google/fatcat/bootblock.c new file mode 100644 index 0000000..6ee655e --- /dev/null +++ b/src/mainboard/google/fatcat/bootblock.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <bootblock_common.h> + +void bootblock_mainboard_early_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd new file mode 100644 index 0000000..5b20f00 --- /dev/null +++ b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd @@ -0,0 +1,49 @@ +FLASH 32M { + SI_ALL 8M { + SI_DESC 16K + SI_ME + } + SI_BIOS 24M { + RW_SECTION_A 7680K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7680K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 3M + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/google/fatcat/chromeos.c b/src/mainboard/google/fatcat/chromeos.c new file mode 100644 index 0000000..5ed041f --- /dev/null +++ b/src/mainboard/google/fatcat/chromeos.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <bootmode.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <types.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { +#if CONFIG(VBOOT_LID_SWITCH) + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, +#else + /* fake LID open to avoid shutdown in depthcharge */ + {-1, ACTIVE_HIGH, 1, "lid"}, +#endif + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + return gpio_get(GPIO_PCH_WP); +} + +int get_ec_is_trusted(void) +{ + /* VB2_CONTEXT_EC_TRUSTED should be set according to the Ti50 boot mode. */ + return 0; +} diff --git a/src/mainboard/google/fatcat/chromeos.fmd b/src/mainboard/google/fatcat/chromeos.fmd new file mode 100644 index 0000000..77f5555 --- /dev/null +++ b/src/mainboard/google/fatcat/chromeos.fmd @@ -0,0 +1,49 @@ +FLASH 32M { + SI_ALL 8M { + SI_DESC 16K + SI_ME + } + SI_BIOS 24M { + RW_SECTION_A 7M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 4M + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/google/fatcat/dsdt.asl b/src/mainboard/google/fatcat/dsdt.asl new file mode 100644 index 0000000..2c714d7 --- /dev/null +++ b/src/mainboard/google/fatcat/dsdt.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <variant/ec.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + /* TODO: Add ACPI code as per board design */ +} diff --git a/src/mainboard/google/fatcat/ec.c b/src/mainboard/google/fatcat/ec.c new file mode 100644 index 0000000..f828bc5 --- /dev/null +++ b/src/mainboard/google/fatcat/ec.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <console/console.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <variant/ec.h> + +void mainboard_ec_init(void) +{ + static const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + printk(BIOS_DEBUG, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/google/fatcat/mainboard.c b/src/mainboard/google/fatcat/mainboard.c new file mode 100644 index 0000000..107ee8d --- /dev/null +++ b/src/mainboard/google/fatcat/mainboard.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <device/device.h> +#include <ec/ec.h> +#include <soc/ramstage.h> +#include <stdio.h> +#include <stdlib.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void __weak fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + /* default implementation does nothing */ +} + +void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +{ + variant_update_soc_chip_config(config); +} + +__weak void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +{ + /* default implementation does nothing */ +} + +static void mainboard_init(void *chip_info) +{ + struct pad_config *padbased_table; + const struct pad_config *base_pads; + size_t base_num; + + padbased_table = new_padbased_table(); + base_pads = variant_gpio_table(&base_num); + gpio_padbased_override(padbased_table, base_pads, base_num); + fw_config_gpio_padbased_override(padbased_table); + gpio_configure_pads_with_padbased(padbased_table); + free(padbased_table); + baseboard_devtree_update(); +} + +void __weak baseboard_devtree_update(void) +{ + /* Override dev tree settings per baseboard */ +} + +void __weak variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + /* Add board-specific MS0X entries */ + /* + if (s0ix_entry == S0IX_ENTRY) { + implement variant operations here + } + if (s0ix_entry == S0IX_EXIT) { + implement variant operations here + } + */ +} + +static void mainboard_dev_init(struct device *dev) +{ + mainboard_ec_init(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_dev_init; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c new file mode 100644 index 0000000..9e41d46 --- /dev/null +++ b/src/mainboard/google/fatcat/romstage.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <string.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + const struct pad_config *pads; + size_t pads_num; + const struct mb_cfg *mem_config = variant_memory_params(); + bool half_populated = variant_is_half_populated(); + struct mem_spd spd_info; + + pads = variant_romstage_gpio_table(&pads_num); + gpio_configure_pads(pads, pads_num); + + memset(&spd_info, 0, sizeof(spd_info)); + variant_get_spd_info(&spd_info); + + memcfg_init(memupd, mem_config, &spd_info, half_populated); +} diff --git a/src/mainboard/google/fatcat/smihandler.c b/src/mainboard/google/fatcat/smihandler.c new file mode 100644 index 0000000..9208d51 --- /dev/null +++ b/src/mainboard/google/fatcat/smihandler.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/smm.h> +#include <elog.h> +#include <intelblocks/smihandler.h> +#include <variant/ec.h> + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + return 0; +} + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); +} + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk new file mode 100644 index 0000000..be05cd4 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb new file mode 100644 index 0000000..9f4f3455 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -0,0 +1,3 @@ +chip soc/intel/meteorlake + device domain 0 on end +end diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h new file mode 100644 index 0000000..b9b4689 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <baseboard/gpio.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. AC Connect/Disconnect + * 3. Power button + * 4. Key press + * 5. Mode change + * 6. Low battery + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + MAINBOARD_EC_S5_WAKE_EVENTS) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) | \ + MAINBOARD_EC_S3_WAKE_EVENTS) +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN)) +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable Keyboard Backlight */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ +#define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */ + +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h new file mode 100644 index 0000000..67eb97f --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* FIXME: update below code as per board schematics */ +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI 0 +/* GPIO IRQ for tight timestamps / wake support */ +#define EC_SYNC_IRQ 0 +/* WP signal to PCH */ +#define GPIO_PCH_WP 0 + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/memory.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/memory.c new file mode 100644 index 0000000..4f621f3 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-3.0-or-later */ + +#include <baseboard/variants.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + /* TODO: Add Memory configuration */ + .ect = 1, /* Early Command Training */ +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + return 0; +} + +bool __weak variant_is_half_populated(void) +{ + return 0; +} + +void __weak variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..8a97d00 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <chip.h> +#include <soc/gpio.h> +#include <soc/meminit.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The next set of functions return the gpio table and fill in the number of entries for + * each table. + */ + +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_romstage_gpio_table(size_t *num); +void fw_config_gpio_padbased_override(struct pad_config *padbased_table); + +const struct mb_cfg *variant_memory_params(void); +void variant_get_spd_info(struct mem_spd *spd_info); +int variant_memory_sku(void); +bool variant_is_half_populated(void); +void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config); + +/* Get soc power limit config struct for current CPU sku */ +struct soc_power_limits_config *variant_get_soc_power_limit_config(void); + +enum s0ix_entry { + S0IX_EXIT, + S0IX_ENTRY, +}; + +void variant_generate_s0ix_hook(enum s0ix_entry entry); + +/* Modify devictree settings during ramstage by baseboard */ +void baseboard_devtree_update(void); +/* Modify devictree settings during ramstage by dedicated variant */ +void variant_devtree_update(void); + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk new file mode 100644 index 0000000..91f031e --- /dev/null +++ b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c new file mode 100644 index 0000000..ebb0120 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* This header block is used to supply information to arbitrage, a + * google-internal tool. Updating it incorrectly will lead to issues, + * so please don't update it unless a change is specifically required. + * BaseID: 3EC4CE58201758F4 + * Overrides: c826ba419f06f9df9cded8e60633253ddc7b60ff + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* TODO: Fill gpio configuration */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* TODO: Fill gpio configuration */ +}; + +static const struct pad_config romstage_gpio_table[] = { + /* TODO: Fill gpio configuration */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Create the stub for romstage gpio, typically use for power sequence */ +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/fatcat/variants/fatcat/include/variant/ec.h b/src/mainboard/google/fatcat/variants/fatcat/include/variant/ec.h new file mode 100644 index 0000000..4fc0622 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/fatcat/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h new file mode 100644 index 0000000..e468198 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +/* TODO: Add GPIO as per fatcat board */ + +#endif /* __MAINBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/83197?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e Gerrit-Change-Number: 83197 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: device/azalia_device.c: Always read-write GCAP
by Nico Huber (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Angel Pons, Arthur Heymans. Nico Huber has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/83218?usp=email ) Change subject: device/azalia_device.c: Always read-write GCAP ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: LGTM. I wouldn't mind keeping the Kconfig either. But given that selecting it was missed once, I guess something tries to tell us we shouldn't optimize too much. -- To view, visit https://review.coreboot.org/c/coreboot/+/83218?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id61e6976a455273e8c681dbeb4bad35d57b1a8a2 Gerrit-Change-Number: 83218 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 26 Jun 2024 22:00:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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