coreboot-gerrit June 2024

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[S] Change in coreboot[main]: src/lib: Add Kconfig variable for fw_config default value
by Cliff Huang (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Julius Werner, Jérémy Compostella, Subrata Banik, Wonkyu Kim. Hello Anil Kumar K, Bora Guvendik, Jérémy Compostella, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83153?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Jérémy Compostella, Verified-1 by build bot (Jenkins) Change subject: src/lib: Add Kconfig variable for fw_config default value ...................................................................... src/lib: Add Kconfig variable for fw_config default value This CONFIG_FW_CONFIG_DEFAULT_VALUE flag is default to UNDEFINED_FW_CONFIG and won't be used when retrieving fw_config value. Set this with different value in config.<board> file, and it will be used when fw_config is not able to read via Chrome EC, CBFS or VPD. TEST=boot and check fw_config value from coreboot log Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I9694433e01bdcd9ff1e550585c14ea7ccee020a3 --- M src/Kconfig M src/lib/fw_config.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/83153/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9694433e01bdcd9ff1e550585c14ea7ccee020a3 Gerrit-Change-Number: 83153 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: tree: Use pkgconf over pkg-config
by Julius Werner (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Elyes Haouas, Martin L Roth. Julius Werner has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/83157?usp=email ) Change subject: tree: Use pkgconf over pkg-config ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83157/comment/dc89fdf0_5c103e78?us… : PS5, Line 7: tree: Use pkgconf over pkg-config > Indeed, pkgconf does not bring new necessary functionalities for coreboot but […] pkgconf is supposed to be fully backwards-compatible to pkg-config. Does FreeBSD not provide a symlink from /usr/bin/pkg-config to /usr/bin/pkgconf? It should. -- To view, visit https://review.coreboot.org/c/coreboot/+/83157?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e9a92d019854214a5760f705b9cbe3cabe6d2e8 Gerrit-Change-Number: 83157 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 26 Jun 2024 19:57:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: payloads/depthcharge: support depthcharge build with local changes
by Cliff Huang (Code Review) 26 Jun '24

26 Jun '24

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83225?usp=email ) Change subject: payloads/depthcharge: support depthcharge build with local changes ...................................................................... payloads/depthcharge: support depthcharge build with local changes Allow building with local changes. Add dependency and target for generated static_fw_config.h. This ensures this file is geneerated prior to building depthcharge. Fix 'git fetch' for the repo other than origin/main. TEST=deptcharge should build with local changes Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I95c1f71ae149537a2191734a62f416b7b6f41fc6 --- M Makefile.mk M payloads/external/Makefile.mk M payloads/external/depthcharge/Makefile 3 files changed, 15 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/83225/1 diff --git a/Makefile.mk b/Makefile.mk index 301a3bc..d2025ba 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -708,7 +708,7 @@ DEVICETREE_FWCONFIG_H := $(obj)/static_fw_config.h SCONFIG_OPTIONS += --output_f=$(DEVICETREE_FWCONFIG_H) -$(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(CHIPSET_DEVICETREE_FILE) $(objutil)/sconfig/sconfig +$(DEVICETREE_STATIC_C) $(DEVICETREE_FWCONFIG_H): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(CHIPSET_DEVICETREE_FILE) $(objutil)/sconfig/sconfig @printf " SCONFIG $(subst $(src)/,,$(<))\n" mkdir -p $(dir $(DEVICETREE_STATIC_C)) $(objutil)/sconfig/sconfig $(SCONFIG_OPTIONS) diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index 4a17791..4c94e62 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -142,7 +142,7 @@ # Depthcharge -payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) +payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) $(DEVICETREE_FWCONFIG_H) $(MAKE) -C payloads/external/depthcharge \ BOARD=$(BOARD) \ MFLAGS= MAKEFLAGS= \ diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index af303da..7107a59 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -45,19 +45,27 @@ @cd $(project_dir); \ git show $(TAG-y) >/dev/null 2>&1; \ if [ $$? -ne 0 ] || \ - [ "$(TAG-y)" = "origin/main" ]; then \ + [ "$(TAG-y)" = $(DEPTHCHARGE_BRANCH) ]; then \ echo " Fetching new commits from the $(project_name) git repo"; \ git fetch; fi # Check out the requested version of the tree -# Don't write a file for main branch so the latest remote version is always used +# Don't write a file for main branch so the latest remote version is always used. +# If repo has local changes, The latest code of remote main branch won't be +# checked out and the existing code is used to build. $(project_dir)/.version_$(TAG-y): fetch echo " Checking out $(project_name) revision $(TAG-y)" rm -f $(project_dir)/.version_* cd $(project_dir); \ - git checkout main; \ - git branch -D coreboot 2>/dev/null; \ - git checkout -b coreboot $(TAG-y) + git diff-index --quiet HEAD -- ; \ + if [ $$? -eq 0 ] ; then \ + echo " Checking out branch"; \ + git checkout main ; \ + git branch -D coreboot 2>/dev/null ; \ + git checkout -b coreboot $(TAG-y); \ + else \ + echo " Contain local changes. Skip checking out latest code from $(TAG-y)"; \ + fi ifneq ($(DEPTHCHARGE_MASTER),y) touch $(project_dir)/.version_$(TAG-y) endif -- To view, visit https://review.coreboot.org/c/coreboot/+/83225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I95c1f71ae149537a2191734a62f416b7b6f41fc6 Gerrit-Change-Number: 83225 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>

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[XS] Change in coreboot[main]: lib/string: use size_t for local variable in strncmp
by Varshit Pandya (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Felix Held. Varshit Pandya has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/83224?usp=email ) Change subject: lib/string: use size_t for local variable in strncmp ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe35d3741bc6d8a16a3bad3ec27aafc30745d931 Gerrit-Change-Number: 83224 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Jun 2024 19:04:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: lib/string: use size_t for local variable in strncmp
by Marshall Dawson (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Felix Held. Marshall Dawson has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/83224?usp=email ) Change subject: lib/string: use size_t for local variable in strncmp ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe35d3741bc6d8a16a3bad3ec27aafc30745d931 Gerrit-Change-Number: 83224 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Jun 2024 18:43:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: lib/string: use size_t for local variable in strncmp
by Felix Held (Code Review) 26 Jun '24

26 Jun '24

Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/83224?usp=email ) Change subject: lib/string: use size_t for local variable in strncmp ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: or should i squash this into CB:83222 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe35d3741bc6d8a16a3bad3ec27aafc30745d931 Gerrit-Change-Number: 83224 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Jun 2024 18:43:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: lib/string: use size_t for local variable in strncmp
by Felix Held (Code Review) 26 Jun '24

26 Jun '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83224?usp=email ) Change subject: lib/string: use size_t for local variable in strncmp ...................................................................... lib/string: use size_t for local variable in strncmp Since the 'maxlen' parameter's type is changed to size_t, the type of the local variable 'i' which this is compared against should also be changed to size_t. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ibe35d3741bc6d8a16a3bad3ec27aafc30745d931 --- M src/lib/string.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/83224/1 diff --git a/src/lib/string.c b/src/lib/string.c index b1996ff..a7f8074 100644 --- a/src/lib/string.c +++ b/src/lib/string.c @@ -115,7 +115,7 @@ int strncmp(const char *s1, const char *s2, size_t maxlen) { - int i; + size_t i; for (i = 0; i < maxlen; i++) { if ((s1[i] != s2[i]) || (s1[i] == '\0')) -- To view, visit https://review.coreboot.org/c/coreboot/+/83224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe35d3741bc6d8a16a3bad3ec27aafc30745d931 Gerrit-Change-Number: 83224 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: acpi: Rename acpi_create_dmar_drhd
by Felix Held (Code Review) 26 Jun '24

26 Jun '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83202?usp=email ) Change subject: acpi: Rename acpi_create_dmar_drhd ...................................................................... acpi: Rename acpi_create_dmar_drhd For most of SoCs, DRHD is by default with the size of 4KB. However, larger sizes are allowed as well. Rename acpi_create_dmar_drhd to acpi_create_dmar_drhd_4k to support the default case while a later patch will re-add acpi_create_dmar_drhd with a size parameter. TEST=intel/archercity CRB Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/acpi/acpi_dmar.c M src/include/acpi/acpi.h M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/sandybridge/acpi.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/meteorlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/xeon_sp/uncore_acpi.c 16 files changed, 37 insertions(+), 37 deletions(-) Approvals: Nico Huber: Looks good to me, but someone else must approve build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/acpi/acpi_dmar.c b/src/acpi/acpi_dmar.c index 3853142..20a100d 100644 --- a/src/acpi/acpi_dmar.c +++ b/src/acpi/acpi_dmar.c @@ -36,7 +36,7 @@ header->checksum = acpi_checksum((void *)dmar, header->length); } -unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, +unsigned long acpi_create_dmar_drhd_4k(unsigned long current, u8 flags, u16 segment, u64 bar) { dmar_entry_t *drhd = (dmar_entry_t *)current; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 4a71aef..469d672 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1849,7 +1849,7 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, unsigned long (*acpi_fill_dmar)(unsigned long)); -unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, +unsigned long acpi_create_dmar_drhd_4k(unsigned long current, u8 flags, u16 segment, u64 bar); unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, u64 bar, u64 limit); diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index 246fe9a..70f0736 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -25,13 +25,13 @@ PCI_CLASS_REVISION); unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1); + current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE1); current += acpi_create_dmar_ds_pci(current, 0, 0x1b, 0); acpi_dmar_drhd_fixup(tmp, current); if (stepping != STEPPING_B2 && igd_active) { tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE2); + current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE2); current += acpi_create_dmar_ds_pci(current, 0, 0x2, 0); current += acpi_create_dmar_ds_pci(current, 0, 0x2, 1); acpi_dmar_drhd_fixup(tmp, current); @@ -39,7 +39,7 @@ if (me_active) { tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE3); + current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE3); current += acpi_create_dmar_ds_pci(current, 0, 0x3, 0); current += acpi_create_dmar_ds_pci(current, 0, 0x3, 1); current += acpi_create_dmar_ds_pci(current, 0, 0x3, 2); @@ -47,7 +47,7 @@ acpi_dmar_drhd_fixup(tmp, current); } - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE4); + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE4); /* TODO: reserve GTT for 0.2.0 and 0.2.1? */ return current; diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index f3c107b..bd2f719 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -28,7 +28,7 @@ if (emit_igd) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -37,7 +37,7 @@ /* VTVC0BAR has to be set, enabled, and in 32-bit space */ if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 8be161e..3ffab4d 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -34,14 +34,14 @@ if (igfx && igfx->enabled) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, GFXVT_BASE); + current += acpi_create_dmar_drhd_4k(current, 0, 0, GFXVT_BASE); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); } { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 7687f02..dcf8a7c 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -239,7 +239,7 @@ if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -251,7 +251,7 @@ if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar); current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IPU, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -265,7 +265,7 @@ if (tbtbar && tbten) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, tbtbar); current += acpi_create_dmar_ds_pci_br(current, 0, SA_DEV_SLOT_TBT, i); @@ -280,7 +280,7 @@ if (vtvc0bar && vtvc0en) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index b84e454..c9f76eb 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -126,7 +126,7 @@ if (emit_igd) { tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); } @@ -138,7 +138,7 @@ union p2sb_bdf hbdf = p2sb_get_hpet_bdf(); p2sb_hide(); - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, defvtbar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, ibdf.bus, ibdf.dev, ibdf.fn); diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 3fe574f..4c1cdf3 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -38,7 +38,7 @@ if (emit_igd) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -47,7 +47,7 @@ /* VTVC0BAR has to be set, enabled, and in 32-bit space */ if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index a58c4f0..1fd16e9 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -261,7 +261,7 @@ if (emit_igd) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -273,7 +273,7 @@ if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar); current += acpi_create_dmar_ds_pci(current, 0, 5, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -285,7 +285,7 @@ if (vtvc0bar && vtvc0en) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index d0fde3e..afda045 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -173,7 +173,7 @@ if (!vtbar) return current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtbar); current += acpi_create_dmar_ds_ioapic_from_hw(current, diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index f566ce5..8e9c9be 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -175,7 +175,7 @@ if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -187,7 +187,7 @@ if (vtvc0bar && vtvc0en) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 6cf7ef5..5e432a9 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -173,7 +173,7 @@ if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -185,7 +185,7 @@ if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar); current += acpi_create_dmar_ds_pci(current, 0, 5, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -197,7 +197,7 @@ if (vtvc0bar && vtvc0en) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index c8d1978..a3ee198 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -235,14 +235,14 @@ __func__, gfxvtbar, MCHBAR32(GFXVTBAR)); if (is_devfn_enabled(PCI_DEVFN_IGD) && gfxvtbar && gfxvten) { tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); acpi_dmar_drhd_fixup(tmp, current); } tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE_ADDRESS); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 6a56071..e0381e8 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -193,7 +193,7 @@ if (emit_igd) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfx_vtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -206,7 +206,7 @@ if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_IBDF_BUS, V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN); diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 5c4c838..c34b185 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -232,7 +232,7 @@ if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -244,7 +244,7 @@ if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar); current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IPU, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -257,7 +257,7 @@ if (tbtbar && tbten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, tbtbar); current += acpi_create_dmar_ds_pci_br(current, 0, SA_DEV_SLOT_TBT, i); @@ -271,7 +271,7 @@ if (vtvc0bar && vtvc0en) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index 6b6363d..a0bbbff 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -272,12 +272,12 @@ printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " "Register Base Address: 0x%x\n", DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); } else { printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd_4k(current, 0, pcie_seg, reg_base); } // Add PCH IOAPIC -- To view, visit https://review.coreboot.org/c/coreboot/+/83202?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91 Gerrit-Change-Number: 83202 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/trulo/var/orisa: Add STORAGE_NVME in fw_config storage field
by Felix Held (Code Review) 26 Jun '24

26 Jun '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83207?usp=email ) Change subject: mb/google/trulo/var/orisa: Add STORAGE_NVME in fw_config storage field ...................................................................... mb/google/trulo/var/orisa: Add STORAGE_NVME in fw_config storage field Follow nissa baseboard setting for storage field. option STORAGE_EMMC 0 option STORAGE_NVME 1 option STORAGE_UFS 2 BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I75b4b3037c245f7d517cb33d487f71da98f6c4e8 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83207 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/orisa/overridetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index 832e0c9..4540e62 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -5,7 +5,8 @@ end field STORAGE 30 31 option STORAGE_EMMC 0 - option STORAGE_UFS 1 + option STORAGE_NVME 1 + option STORAGE_UFS 2 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/83207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I75b4b3037c245f7d517cb33d487f71da98f6c4e8 Gerrit-Change-Number: 83207 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brox/lotso: Add Fn key scancode
by Felix Held (Code Review) 26 Jun '24

26 Jun '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83204?usp=email ) Change subject: mb/google/brox/lotso: Add Fn key scancode ...................................................................... mb/google/brox/lotso: Add Fn key scancode The Fn key on Lotso emits a scancode of 94 (0x5e). BUG=b:322721490 TEST=Flash Lotso, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: I999627f0ea9db1d79376150a04920ac877a48447 Signed-off-by: Wen Zhang <zhangwen6(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83204 Reviewed-by: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Dengwu Yu: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified Varshit Pandya: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 2637e89..380c84a 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config ACPI_FNKEY_GEN_SCANCODE + default 94 if BOARD_GOOGLE_LOTSO + config BOARD_GOOGLE_BROX_COMMON def_bool n select DRIVERS_GENERIC_GPIO_KEYS -- To view, visit https://review.coreboot.org/c/coreboot/+/83204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I999627f0ea9db1d79376150a04920ac877a48447 Gerrit-Change-Number: 83204 Gerrit-PatchSet: 2 Gerrit-Owner: wen zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com>

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