coreboot-gerrit June 2024

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[XS] Change in coreboot[main]: lib/string: change parameter types to match C standard
by Felix Held (Code Review) 26 Jun '24

26 Jun '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83222?usp=email ) Change subject: lib/string: change parameter types to match C standard ...................................................................... lib/string: change parameter types to match C standard The third parameter of strncpy and strncmp is supposed to be a size_t and not a signed int. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I485e45e18232a0d1625d4d626f923ec66cfbe4a2 --- M src/include/string.h M src/lib/string.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/83222/1 diff --git a/src/include/string.h b/src/include/string.h index e752f8f..dc301ea 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -16,10 +16,10 @@ size_t strnlen(const char *src, size_t max); size_t strlen(const char *src); char *strchr(const char *s, int c); -char *strncpy(char *to, const char *from, int count); +char *strncpy(char *to, const char *from, size_t count); char *strcpy(char *dst, const char *src); int strcmp(const char *s1, const char *s2); -int strncmp(const char *s1, const char *s2, int maxlen); +int strncmp(const char *s1, const char *s2, size_t maxlen); int strspn(const char *str, const char *spn); int strcspn(const char *str, const char *spn); char *strstr(const char *haystack, const char *needle); diff --git a/src/lib/string.c b/src/lib/string.c index d23ed1f..7553295 100644 --- a/src/lib/string.c +++ b/src/lib/string.c @@ -71,7 +71,7 @@ return p; } -char *strncpy(char *to, const char *from, int count) +char *strncpy(char *to, const char *from, size_t count) { char *ret = to; char data; @@ -113,7 +113,7 @@ return r; } -int strncmp(const char *s1, const char *s2, int maxlen) +int strncmp(const char *s1, const char *s2, size_t maxlen) { int i; -- To view, visit https://review.coreboot.org/c/coreboot/+/83222?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I485e45e18232a0d1625d4d626f923ec66cfbe4a2 Gerrit-Change-Number: 83222 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: include/device_tree.h: Fix function name fdt_node_name
by Yu-Ping Wu (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Eric Lai, Felix Singer, Julius Werner, Maximilian Brune. Yu-Ping Wu has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83084?usp=email ) Change subject: include/device_tree.h: Fix function name fdt_node_name ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I527146df26264a0c3af1ad01c21644d751b80236 Gerrit-Change-Number: 83084 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 26 Jun 2024 15:42:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: 3rdparty/arm-trusted-firmware: Update submodule to upstream master
by Julius Werner (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Felix Singer. Julius Werner has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83000?usp=email ) Change subject: 3rdparty/arm-trusted-firmware: Update submodule to upstream master ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icce3595fef3a844034e7cc76fc8480ed5b21618c Gerrit-Change-Number: 83000 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Wed, 26 Jun 2024 15:02:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: commonlib/device_tree: Improve node and property allocation speed
by Raul Rangel (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Julius Werner, Patrick Rudolph, Reka Norman. Raul Rangel has posted comments on this change by Julius Werner. ( https://review.coreboot.org/c/coreboot/+/83208?usp=email ) Change subject: commonlib/device_tree: Improve node and property allocation speed ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f4d80a8b750febfb069b32ef47304ccecdc35af Gerrit-Change-Number: 83208 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 26 Jun 2024 14:50:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: include/commonlib/sot.h: Add SOT structs
by Lean Sheng Tan (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Benjamin Doron, Elyes Haouas, Martin L Roth, Maximilian Brune, Patrick Rudolph, Sean Rhodes. Lean Sheng Tan has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/77882?usp=email ) Change subject: include/commonlib/sot.h: Add SOT structs ...................................................................... Patch Set 14: (1 comment) File src/commonlib/include/commonlib/sot.h: https://review.coreboot.org/c/coreboot/+/77882/comment/3637ac7b_ecc56475?us… : PS13, Line 7: <commonlib/bsd/compiler.h> > Not always. […] any thoughts @ehaouas@noos.fr? -- To view, visit https://review.coreboot.org/c/coreboot/+/77882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f006318a15556f97da286dc032c58ccb7993e4 Gerrit-Change-Number: 77882 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 26 Jun 2024 14:31:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: mb/google/brox: Disable Touchscreen for hardware board version 1
by Felix Held (Code Review) 26 Jun '24

26 Jun '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83199?usp=email ) Change subject: mb/google/brox: Disable Touchscreen for hardware board version 1 ...................................................................... mb/google/brox: Disable Touchscreen for hardware board version 1 On board version 1 and later, touchscreen is not stuffed. Hence configure the relevant GPIOs as not connected, disable the concerned I2C bus in the devicetree as well as SoC chip config for board version 1. BUG=b:347333500 TEST=Build Brox BIOS image and boot to OS. Ensure that there are no peripherals detected in I2C 1 bus through i2cdetect tool. Ensure that no touchscreen devices are exported through ACPI SSDT table. Ensure that other I2C peripherals - eg. Trackpad and Ti50 are functional. Ensure that the device is able to suspend and resume for 25 cycles. Change-Id: Ia0578b90b0e8158ae28bcc51add637844ba6acf6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83199 Reviewed-by: Shelley Chen <shchen(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brox/variants/brox/gpio.c M src/mainboard/google/brox/variants/brox/ramstage.c M src/mainboard/google/brox/variants/brox/variant.c 3 files changed, 40 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/mainboard/google/brox/variants/brox/gpio.c b/src/mainboard/google/brox/variants/brox/gpio.c index 5af3552..3f6767e 100644 --- a/src/mainboard/google/brox/variants/brox/gpio.c +++ b/src/mainboard/google/brox/variants/brox/gpio.c @@ -1,11 +1,34 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> #include <soc/gpio.h> +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> NC */ + PAD_NC(GPP_F7, NONE), + /* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI1_CS0# NF6: USB_C_GPP_F16] ==> NC */ + PAD_NC(GPP_F16, NONE), + /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> NC */ + PAD_NC(GPP_F17, NONE), + /* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> NC */ + PAD_NC(GPP_F18, NONE), + /* GPP_H6 : [NF1: I2C1_SDA NF6: USB_C_GPP_H6] ==> NC */ + PAD_NC(GPP_H6, NONE), + /* GPP_H7 : [NF1: I2C1_SCL NF6: USB_C_GPP_H7] ==> NC */ + PAD_NC(GPP_H7, NONE), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { + uint32_t board_version = board_id(); + *num = 0; + if (board_version >= 1) { + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; + } return NULL; } diff --git a/src/mainboard/google/brox/variants/brox/ramstage.c b/src/mainboard/google/brox/variants/brox/ramstage.c index 86418da..c81dd7e 100644 --- a/src/mainboard/google/brox/variants/brox/ramstage.c +++ b/src/mainboard/google/brox/variants/brox/ramstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <boardid.h> #include <device/pci_ids.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/power_limit.h> @@ -44,6 +45,7 @@ void __weak variant_devtree_update(void) { + uint32_t board_version = board_id(); printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); const struct cpu_power_limits *limits = performance_efficient_limits; @@ -51,4 +53,12 @@ variant_update_power_limits(limits, limits_size); variant_update_psys_power_limits(limits, sys_limits, limits_size, &psys_config); + + /* Disable I2C bus device for Touchscreen */ + if (board_version >= 1) { + struct device *i2c1_dev = DEV_PTR(i2c1); + + if (i2c1_dev) + i2c1_dev->enabled = false; + } } diff --git a/src/mainboard/google/brox/variants/brox/variant.c b/src/mainboard/google/brox/variants/brox/variant.c index e085a86..332d152 100644 --- a/src/mainboard/google/brox/variants/brox/variant.c +++ b/src/mainboard/google/brox/variants/brox/variant.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <boardid.h> #include <baseboard/variants.h> #include <chip.h> #include <fw_config.h> @@ -8,10 +9,16 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { + uint32_t board_version = board_id(); + if (fw_config_probe(FW_CONFIG(WIFI_BT, WIFI_BT_CNVI))) { printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); config->cnvi_bt_core = true; } + + /* Disable I2C bus device for Touchscreen for board version 1*/ + if (board_version >= 1) + config->serial_io_i2c_mode[PchSerialIoIndexI2C1] = PchSerialIoDisabled; } const char *get_wifi_sar_cbfs_filename(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/83199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia0578b90b0e8158ae28bcc51add637844ba6acf6 Gerrit-Change-Number: 83199 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brox: Add default ACPI brightness levels
by Felix Held (Code Review) 26 Jun '24

26 Jun '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83152?usp=email ) Change subject: mb/google/brox: Add default ACPI brightness levels ...................................................................... mb/google/brox: Add default ACPI brightness levels Kernel need the default brightness steps. Otherwise following error messages are observed in the kernel: [Firmware Bug]: ACPI(GFX0) defines _DOD but not _DOS ACPI BIOS Error (bug): Could not resolve symbol [^^XBCL], AE_NOT_FOUND ACPI Error: Aborting method \_SB.PCI0.GFX0.LCD0._BCL due to previous error (AE_NOT_FOUND) BUG=b:346807006 TEST=Build Brox BIOS image and boot to OS. Ensure that the concerned error messages are resolved. Ensure that the backlight controls are functional. Change-Id: Icd569b0efef31908edb1b7dc384e60a16fc5bd0c Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83152 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/brox/dsdt.asl 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Shelley Chen: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brox/dsdt.asl b/src/mainboard/google/brox/dsdt.asl index 6ae4694..30e9fe1 100644 --- a/src/mainboard/google/brox/dsdt.asl +++ b/src/mainboard/google/brox/dsdt.asl @@ -26,6 +26,7 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/alderlake/acpi/southbridge.asl> #include <soc/intel/alderlake/acpi/tcss.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } -- To view, visit https://review.coreboot.org/c/coreboot/+/83152?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd569b0efef31908edb1b7dc384e60a16fc5bd0c Gerrit-Change-Number: 83152 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/corsola/var/wugtrio: Add LCE_LMFBX101117480 MIPI panel
by Yang Wu (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Yang Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83221?usp=email ) Change subject: mb/google/corsola/var/wugtrio: Add LCE_LMFBX101117480 MIPI panel ...................................................................... mb/google/corsola/var/wugtrio: Add LCE_LMFBX101117480 MIPI panel Add LCE_LMFBX101117480 MIPI panel for Wugtrio. Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I863e172400ffb26b5c9c240a21d15c6a2240b4ad Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/panel_wugtrio.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83221/1 diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 6baaeac..41f9845 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -70,6 +70,7 @@ select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select MIPI_PANEL_KD_KD101NE3_40TI if BOARD_GOOGLE_WUGTRIO + select MIPI_PANEL_LCE_LMFBX101117480 if BOARD_GOOGLE_WUGTRIO select MIPI_PANEL_STA_ER88577 if BOARD_GOOGLE_WUGTRIO select MIPI_PANEL_STA_HIMAX83102_J02 if BOARD_GOOGLE_STARMIE select MIPI_PANEL_STA_ILI9882T if BOARD_GOOGLE_STARMIE diff --git a/src/mainboard/google/corsola/panel_wugtrio.c b/src/mainboard/google/corsola/panel_wugtrio.c index c8a8971..0603ce0 100644 --- a/src/mainboard/google/corsola/panel_wugtrio.c +++ b/src/mainboard/google/corsola/panel_wugtrio.c @@ -41,6 +41,14 @@ .disp_path = DISP_PATH_MIPI, .orientation = LB_FB_ORIENTATION_RIGHT_UP, }, + /* LCE Corporation panel with bias IC on it */ + [7] = { + .configure_backlight = backlight_control, + .power_on = mipi_panel_power_on, + .name = "LCE_LMFBX101117480", + .disp_path = DISP_PATH_MIPI, + .orientation = LB_FB_ORIENTATION_RIGHT_UP, + }, }; struct panel_description *get_panel_description(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/83221?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I863e172400ffb26b5c9c240a21d15c6a2240b4ad Gerrit-Change-Number: 83221 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: drivers/mipi: Add support for LCE_LMFBX101117480 panel
by Yang Wu (Code Review) 26 Jun '24

26 Jun '24

Yang Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83220?usp=email ) Change subject: drivers/mipi: Add support for LCE_LMFBX101117480 panel ...................................................................... drivers/mipi: Add support for LCE_LMFBX101117480 panel Add STA panel LCE_LMFBX101117480 serializable data to CBFS. Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf About the init code, we communicated with the vendor through the datasheet to confirm the writing method of each register value. BUG=b:331870701 TEST=build and check the CBFS includes the panel BRANCH=None Change-Id: I60858109e4b07f720461e320212d7b197ec1130c Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/drivers/mipi/Kconfig M src/drivers/mipi/Makefile.mk A src/drivers/mipi/panel-LCE_LMFBX101117480.c 3 files changed, 235 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/83220/1 diff --git a/src/drivers/mipi/Kconfig b/src/drivers/mipi/Kconfig index 4f3257f..d70e92d 100644 --- a/src/drivers/mipi/Kconfig +++ b/src/drivers/mipi/Kconfig @@ -48,6 +48,9 @@ config MIPI_PANEL_KD_KD101NE3_40TI bool +config MIPI_PANEL_LCE_LMFBX101117480 + bool + config MIPI_PANEL_STA_2081101QFH032011_53G bool diff --git a/src/drivers/mipi/Makefile.mk b/src/drivers/mipi/Makefile.mk index 3890917..a71cff6 100644 --- a/src/drivers/mipi/Makefile.mk +++ b/src/drivers/mipi/Makefile.mk @@ -25,6 +25,8 @@ panel-params-$(CONFIG_MIPI_PANEL_KD_KD101NE3_40TI) += panel-KD_KD101NE3_40TI +panel-params-$(CONFIG_MIPI_PANEL_LCE_LMFBX101117480) += panel-LCE_LMFBX101117480 + panel-params-$(CONFIG_MIPI_PANEL_STA_2081101QFH032011_53G) += panel-STA_2081101QFH032011_53G panel-params-$(CONFIG_MIPI_PANEL_STA_ER88577) += panel-STA_ER88577 panel-params-$(CONFIG_MIPI_PANEL_STA_HIMAX83102_J02) += panel-STA_HIMAX83102_J02 diff --git a/src/drivers/mipi/panel-LCE_LMFBX101117480.c b/src/drivers/mipi/panel-LCE_LMFBX101117480.c new file mode 100644 index 0000000..7f76ac8 --- /dev/null +++ b/src/drivers/mipi/panel-LCE_LMFBX101117480.c @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mipi/panel.h> + +struct panel_serializable_data KD_KD101NE3_40TI = { + .edid = { + .ascii_string = "LMFBX101117480", + .manufacturer_name = "LCE", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 70595, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 800, .hbl = 90, .hso = 30, .hspw = 30, + .va = 1280, .vbl = 42, .vso = 30, .vspw = 4, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, + }, + .init = { + PANEL_DELAY(24), + PANEL_DCS(0xE0, 0x00), + PANEL_DCS(0xE1, 0x93), + PANEL_DCS(0xE2, 0x65), + PANEL_DCS(0xE3, 0xF8), + PANEL_DCS(0x80, 0x03), + PANEL_DCS(0xE0, 0x01), + PANEL_DCS(0x0C, 0x74), + PANEL_DCS(0x17, 0x00), + PANEL_DCS(0x18, 0xBF), + PANEL_DCS(0x19, 0x00), + PANEL_DCS(0x1A, 0x00), + PANEL_DCS(0x1B, 0xBF), + PANEL_DCS(0x1C, 0x00), + PANEL_DCS(0x1F, 0x70), + PANEL_DCS(0x20, 0x2D), + PANEL_DCS(0x21, 0x2D), + PANEL_DCS(0x22, 0x7E), + PANEL_DCS(0x24, 0xFE), + PANEL_DCS(0x37, 0x19), + PANEL_DCS(0x35, 0x28), + PANEL_DCS(0x38, 0x05), + PANEL_DCS(0x39, 0x08), + PANEL_DCS(0x3A, 0x12), + PANEL_DCS(0x3C, 0x78), + PANEL_DCS(0x3D, 0xFF), + PANEL_DCS(0x3E, 0xFF), + PANEL_DCS(0x3F, 0x7F), + PANEL_DCS(0x40, 0x06), + PANEL_DCS(0x41, 0xA0), + PANEL_DCS(0x43, 0x1E), + PANEL_DCS(0x44, 0x0B), + PANEL_DCS(0x0C, 0x74), + PANEL_DCS(0x55, 0x02), + PANEL_DCS(0x56, 0x01), + PANEL_DCS(0x57, 0x8E), + PANEL_DCS(0x58, 0x09), + PANEL_DCS(0x59, 0x0A), + PANEL_DCS(0x5A, 0x2E), + PANEL_DCS(0x5B, 0x1A), + PANEL_DCS(0x5C, 0x15), + PANEL_DCS(0x5D, 0x7F), + PANEL_DCS(0x5E, 0x69), + PANEL_DCS(0x5F, 0x59), + PANEL_DCS(0x60, 0x4E), + PANEL_DCS(0x61, 0x4C), + PANEL_DCS(0x62, 0x40), + PANEL_DCS(0x63, 0x45), + PANEL_DCS(0x64, 0x30), + PANEL_DCS(0x65, 0x4A), + PANEL_DCS(0x66, 0x49), + PANEL_DCS(0x67, 0x4A), + PANEL_DCS(0x68, 0x68), + PANEL_DCS(0x69, 0x57), + PANEL_DCS(0x6A, 0x5B), + PANEL_DCS(0x6B, 0x4E), + PANEL_DCS(0x6C, 0x49), + PANEL_DCS(0x6D, 0x24), + PANEL_DCS(0x6E, 0x12), + PANEL_DCS(0x6F, 0x02), + PANEL_DCS(0x70, 0x7F), + PANEL_DCS(0x71, 0x69), + PANEL_DCS(0x72, 0x59), + PANEL_DCS(0x73, 0x4E), + PANEL_DCS(0x74, 0x4C), + PANEL_DCS(0x75, 0x40), + PANEL_DCS(0x76, 0x45), + PANEL_DCS(0x77, 0x30), + PANEL_DCS(0x78, 0x4A), + PANEL_DCS(0x79, 0x49), + PANEL_DCS(0x7A, 0x4A), + PANEL_DCS(0x7B, 0x68), + PANEL_DCS(0x7C, 0x57), + PANEL_DCS(0x7D, 0x5B), + PANEL_DCS(0x7E, 0x4E), + PANEL_DCS(0x7F, 0x49), + PANEL_DCS(0x80, 0x24), + PANEL_DCS(0x81, 0x12), + PANEL_DCS(0x82, 0x02), + PANEL_DCS(0xE0, 0x02), + PANEL_DCS(0x00, 0x52), + PANEL_DCS(0x01, 0x55), + PANEL_DCS(0x02, 0x55), + PANEL_DCS(0x03, 0x50), + PANEL_DCS(0x04, 0x77), + PANEL_DCS(0x05, 0x57), + PANEL_DCS(0x06, 0x55), + PANEL_DCS(0x07, 0x4E), + PANEL_DCS(0x08, 0x4C), + PANEL_DCS(0x09, 0x5F), + PANEL_DCS(0x0A, 0x4A), + PANEL_DCS(0x0B, 0x48), + PANEL_DCS(0x0C, 0x55), + PANEL_DCS(0x0D, 0x46), + PANEL_DCS(0x0E, 0x44), + PANEL_DCS(0x0F, 0x40), + PANEL_DCS(0x10, 0x55), + PANEL_DCS(0x11, 0x55), + PANEL_DCS(0x12, 0x55), + PANEL_DCS(0x13, 0x55), + PANEL_DCS(0x14, 0x55), + PANEL_DCS(0x15, 0x55), + PANEL_DCS(0x16, 0x53), + PANEL_DCS(0x17, 0x55), + PANEL_DCS(0x18, 0x55), + PANEL_DCS(0x19, 0x51), + PANEL_DCS(0x1A, 0x77), + PANEL_DCS(0x1B, 0x57), + PANEL_DCS(0x1C, 0x55), + PANEL_DCS(0x1D, 0x4F), + PANEL_DCS(0x1E, 0x4D), + PANEL_DCS(0x1F, 0x5F), + PANEL_DCS(0x20, 0x4B), + PANEL_DCS(0x21, 0x49), + PANEL_DCS(0x22, 0x55), + PANEL_DCS(0x23, 0x47), + PANEL_DCS(0x24, 0x45), + PANEL_DCS(0x25, 0x41), + PANEL_DCS(0x26, 0x55), + PANEL_DCS(0x27, 0x55), + PANEL_DCS(0x28, 0x55), + PANEL_DCS(0x29, 0x55), + PANEL_DCS(0x2A, 0x55), + PANEL_DCS(0x2B, 0x55), + PANEL_DCS(0x2C, 0x13), + PANEL_DCS(0x2D, 0x15), + PANEL_DCS(0x2E, 0x15), + PANEL_DCS(0x2F, 0x01), + PANEL_DCS(0x30, 0x37), + PANEL_DCS(0x31, 0x17), + PANEL_DCS(0x32, 0x15), + PANEL_DCS(0x33, 0x0D), + PANEL_DCS(0x34, 0x0F), + PANEL_DCS(0x35, 0x15), + PANEL_DCS(0x36, 0x05), + PANEL_DCS(0x37, 0x07), + PANEL_DCS(0x38, 0x15), + PANEL_DCS(0x39, 0x09), + PANEL_DCS(0x3A, 0x0B), + PANEL_DCS(0x3B, 0x11), + PANEL_DCS(0x3C, 0x15), + PANEL_DCS(0x3D, 0x15), + PANEL_DCS(0x3E, 0x15), + PANEL_DCS(0x3F, 0x15), + PANEL_DCS(0x40, 0x15), + PANEL_DCS(0x41, 0x15), + PANEL_DCS(0x42, 0x12), + PANEL_DCS(0x43, 0x15), + PANEL_DCS(0x44, 0x15), + PANEL_DCS(0x45, 0x00), + PANEL_DCS(0x46, 0x37), + PANEL_DCS(0x47, 0x17), + PANEL_DCS(0x48, 0x15), + PANEL_DCS(0x49, 0x0C), + PANEL_DCS(0x4A, 0x0E), + PANEL_DCS(0x4B, 0x15), + PANEL_DCS(0x4C, 0x04), + PANEL_DCS(0x4D, 0x06), + PANEL_DCS(0x4E, 0x15), + PANEL_DCS(0x4F, 0x08), + PANEL_DCS(0x50, 0x0A), + PANEL_DCS(0x51, 0x10), + PANEL_DCS(0x52, 0x15), + PANEL_DCS(0x53, 0x15), + PANEL_DCS(0x54, 0x15), + PANEL_DCS(0x55, 0x15), + PANEL_DCS(0x56, 0x15), + PANEL_DCS(0x57, 0x15), + PANEL_DCS(0x58, 0x40), + PANEL_DCS(0x5B, 0x10), + PANEL_DCS(0x5C, 0x06), + PANEL_DCS(0x5D, 0x40), + PANEL_DCS(0x5E, 0x00), + PANEL_DCS(0x5F, 0x00), + PANEL_DCS(0x60, 0x40), + PANEL_DCS(0x61, 0x03), + PANEL_DCS(0x62, 0x04), + PANEL_DCS(0x63, 0x6C), + PANEL_DCS(0x64, 0x6C), + PANEL_DCS(0x65, 0x75), + PANEL_DCS(0x66, 0x08), + PANEL_DCS(0x67, 0xB4), + PANEL_DCS(0x68, 0x08), + PANEL_DCS(0x69, 0x6C), + PANEL_DCS(0x6A, 0x6C), + PANEL_DCS(0x6B, 0x0C), + PANEL_DCS(0x6D, 0x00), + PANEL_DCS(0x6E, 0x00), + PANEL_DCS(0x6F, 0x88), + PANEL_DCS(0x75, 0xBB), + PANEL_DCS(0x76, 0x00), + PANEL_DCS(0x77, 0x05), + PANEL_DCS(0x78, 0x2A), + PANEL_DCS(0xE0, 0x04), + PANEL_DCS(0x02, 0x23), + PANEL_DCS(0x09, 0x11), + PANEL_DCS(0x0E, 0x48), + PANEL_DCS(0x36, 0x49), + PANEL_DCS(0x2B, 0x08), + PANEL_DCS(0x2E, 0x03), + PANEL_DCS(0xE0, 0x00), + PANEL_DCS(0xE6, 0x02), + PANEL_DCS(0xE7, 0x06), + PANEL_DCS(0x11, 0x00), + PANEL_DELAY(120), + PANEL_DCS(0x29, 0x00), + PANEL_DELAY(50), + }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/83220?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60858109e4b07f720461e320212d7b197ec1130c Gerrit-Change-Number: 83220 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/intel: Adapt crashlog IP to also support 64-bit
by Sowmya Aralguppe (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Nick Vaccaro, Paul Menzel, Pratikkumar V Prajapati, Subrata Banik, Tarun. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email ) Change subject: soc/intel: Adapt crashlog IP to also support 64-bit ...................................................................... Patch Set 22: (1 comment) Patchset: PS22: > > The pointer typecast correction is part of 64-bit support […] I wouldnt say that the implementation was wrong but imho it did not have all child records . -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 22 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 14:08:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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