coreboot-gerrit June 2024

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[S] Change in coreboot[main]: include/device_tree.h: Fix function name fdt_node_name
by Maximilian Brune (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Eric Lai, Felix Singer, Julius Werner, Yu-Ping Wu. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83084?usp=email ) Change subject: include/device_tree.h: Fix function name fdt_node_name ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Need to rebase. done -- To view, visit https://review.coreboot.org/c/coreboot/+/83084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I527146df26264a0c3af1ad01c21644d751b80236 Gerrit-Change-Number: 83084 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 10:22:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: include/device_tree.h: Fix function name fdt_node_name
by Maximilian Brune (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Eric Lai, Felix Singer, Julius Werner, Maximilian Brune, Yu-Ping Wu. Hello Eric Lai, Julius Werner, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83084?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Eric Lai, Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: include/device_tree.h: Fix function name fdt_node_name ...................................................................... include/device_tree.h: Fix function name fdt_node_name Rename fdt_node_name to the actual function name and also rename the references. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I527146df26264a0c3af1ad01c21644d751b80236 --- M src/commonlib/include/commonlib/device_tree.h M src/lib/fit.c 2 files changed, 6 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/83084/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I527146df26264a0c3af1ad01c21644d751b80236 Gerrit-Change-Number: 83084 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/intel: Adapt crashlog IP to also support 64-bit
by Angel Pons (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Nick Vaccaro, Paul Menzel, Pratikkumar V Prajapati, Sowmya Aralguppe, Subrata Banik, Tarun. Angel Pons has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email ) Change subject: soc/intel: Adapt crashlog IP to also support 64-bit ...................................................................... Patch Set 22: (2 comments) Patchset: PS22: > There were some discrepancies in the original implementation […] It would be great if you could put fixes in a separate commit. Otherwise it is hard to know what is part of adding 64-bit support, what is a fix and what is a new bug. File src/soc/intel/meteorlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/83106/comment/3d74b4c0_f809fdbe?us… : PS22, Line 355: if (!is_crashlog_data_valid(dw0)) > This is in line 343 . […] `cur_offset` changes inside the loop, so this reads a different register every iteration -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 22 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 10:15:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: commonlib/device_tree: Improve node and property allocation speed
by Maximilian Brune (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Julius Werner, Patrick Rudolph, Raul Rangel, Reka Norman. Maximilian Brune has posted comments on this change by Julius Werner. ( https://review.coreboot.org/c/coreboot/+/83208?usp=email ) Change subject: commonlib/device_tree: Improve node and property allocation speed ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f4d80a8b750febfb069b32ef47304ccecdc35af Gerrit-Change-Number: 83208 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 26 Jun 2024 10:10:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: device/azalia_device.c: Use `azalia_enter_reset()`
by Elyes Haouas (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Angel Pons, Arthur Heymans, Nico Huber. Elyes Haouas has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/83217?usp=email ) Change subject: device/azalia_device.c: Use `azalia_enter_reset()` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83217?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04924e68420a93a1ad46f5a7ab359e38c0f7e210 Gerrit-Change-Number: 83217 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 26 Jun 2024 09:43:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel: Adapt crashlog IP to also support 64-bit
by Sowmya Aralguppe (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Nick Vaccaro, Paul Menzel, Pratikkumar V Prajapati, Subrata Banik, Tarun. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email ) Change subject: soc/intel: Adapt crashlog IP to also support 64-bit ...................................................................... Patch Set 22: (2 comments) Patchset: PS22: > @sowmya.aralguppe@intel.com: can you please check below prints w/ and w/o your CL? […] There were some discrepancies in the original implementation 1) The child record count is 5 but the loop happens for only 2 times. 2) Cpu crash log size is wrong . PMC CrashLog size in discovery mode: 0x2208 [DEBUG] adjusted cpu discovery table offset: 0x1f70 [DEBUG] cpu_crashlog_discovery_table buffer count: 0x5 [DEBUG] cpu_crashlog_discovery_table buffer: 0x0 size: 0x800 offset: 0x0 [DEBUG] cpu_crashlog_discovery_table buffer: 0x1 size: 0x800 offset: 0x4000 With more prints I could see that it is not taking offset properly – address which was supposed to be 0x8d7c1f78 and it was wrongly taken as 0x8d7c1f90 for offset of 8 [DEBUG] bar address value is: 0x8d7c0000 [DEBUG] adjusted cpu discovery table offset: 0x1f70 [DEBUG] disc_tab_addr value is: 0x8d7c1f70 [DEBUG] The derefernced value is: 0x80300513 [DEBUG] Header data is: 0x3b80300513 [DEBUG] cpu_crashlog_discovery_table buffer count: 0x5 [DEBUG] The 64 bit dw1 data is 0x80000000000 [DEBUG] The Address value is: 0x0x8d7c1f90 [DEBUG] The derefernced value is: 0x4000 and the offset is 8 Was able to root cause this issue to pointer typecast and with this there was an increase in the cpu crashlog [DEBUG] cpu_crashlog_discovery_table buffer count: 0x5 [DEBUG] cpu_crashlog_discovery_table buffer: 0x1 size: 0x800 offset: 0x4000 [DEBUG] cpu_crashlog_discovery_table buffer: 0x2 size: 0x800 offset: 0x10000 [DEBUG] cpu_crashlog_discovery_table buffer: 0x3 size: 0x800 offset: 0x14000 [DEBUG] cpu_crashlog_discovery_table buffer: 0x4 size: 0x93 offset: 0x20000 [DEBUG] PMC crashLog size : 0x2208 [DEBUG] Region[0x0].Tag=0x7 offset=0x9b, size=0x400 [DEBUG] Found metadata tag. PMC crashlog size adjusted to: 0x1208 [DEBUG] Region[0x1].Tag=0x0 offset=0xa00, size=0x280 [DEBUG] Region[0x2].Tag=0x0 offset=0x2bb0, size=0xa [DEBUG] Region[0x3].Tag=0x0 offset=0x3a00, size=0x80 [DEBUG] Region[0x4].Tag=0x1 offset=0x500, size=0x100 [DEBUG] Region[0x5].Tag=0x1 offset=0x12d8, size=0xa [DEBUG] Region[0x6].Tag=0x1 offset=0x1600, size=0x6e [DEBUG] Invalid data 0xdeadbeef at offset 0x1600 from addr 0x8d6fc000 [DEBUG] PMC crashlog size adjusted to: 0x1050 [DEBUG] Region[0x7].Tag=0x0 offset=0x0, size=0x0 [DEBUG] m_cpu_crashLog_size : 0x624C bytes There was one more change Here in the below code, we are checking for the offset and not size static bool is_crashlog_data_valid(u32 dw0) { return (dw0 != 0x0 && dw0 != INVALID_CRASHLOG_RECORD); } dw0 = read32((u32 *)(uintptr_t)disc_tab_addr + cur_offset); if (!is_crashlog_data_valid(dw0)) continue we should be checking the upper 32 bytes. [DEBUG] adjusted cpu discovery table offset: 0x1f70 [DEBUG] cpu_crashlog_discovery_table buffer count: 0x5 [DEBUG] cpu_crashlog_discovery_table buffer: 0x0 size: 0x800 offset: 0x0 [DEBUG] cpu_crashlog_discovery_table buffer: 0x1 size: 0x800 offset: 0x4000 [DEBUG] cpu_crashlog_discovery_table buffer: 0x2 size: 0x800 offset: 0x10000 [DEBUG] cpu_crashlog_discovery_table buffer: 0x3 size: 0x800 offset: 0x14000 [DEBUG] cpu_crashlog_discovery_table buffer: 0x4 size: 0x93 offset: 0x20000 [DEBUG] PMC crashLog size : 0x2208 [DEBUG] Region[0x0].Tag=0x7 offset=0x9b, size=0x400 [DEBUG] Found metadata tag. PMC crashlog size adjusted to: 0x1208 [DEBUG] Region[0x1].Tag=0x0 offset=0xa00, size=0x280 [DEBUG] Region[0x2].Tag=0x0 offset=0x2bb0, size=0xa [DEBUG] Region[0x3].Tag=0x0 offset=0x3a00, size=0x80 [DEBUG] Region[0x4].Tag=0x1 offset=0x500, size=0x100 [DEBUG] Region[0x5].Tag=0x1 offset=0x12d8, size=0xa [DEBUG] Region[0x6].Tag=0x1 offset=0x1600, size=0x6e [DEBUG] Invalid data 0xdeadbeef at offset 0x1600 from addr 0x8d6fc000 [DEBUG] PMC crashlog size adjusted to: 0x1050 [DEBUG] Region[0x7].Tag=0x0 offset=0x0, size=0x0 [DEBUG] m_cpu_crashLog_size : 0x824C bytes [DEBUG] CPU crashLog present. File src/soc/intel/meteorlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/83106/comment/b6aaaa9d_67d2430d?us… : PS22, Line 355: if (!is_crashlog_data_valid(dw0)) > This check is gone, is this intentional? This is in line 343 .Inside for loop we need to check for size only -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 22 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 09:41:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: device/azalia_device.c: Always read-write GCAP
by Angel Pons (Code Review) 26 Jun '24

26 Jun '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83218?usp=email ) Change subject: device/azalia_device.c: Always read-write GCAP ...................................................................... device/azalia_device.c: Always read-write GCAP In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP register is RO (Read Only). However, it is known that in some Intel PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some of the bitfields in the GCAP register are R/WO (Read / Write Once). GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock bit for GCAP elsewhere. Lock GCAP by reading GCAP and writing back the same value. This has no effect on platforms that implement GCAP as a RO register or lock GCAP through a different mechanism. Change-Id: Id61e6976a455273e8c681dbeb4bad35d57b1a8a2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/Kconfig M src/device/azalia_device.c M src/soc/intel/common/block/hda/Kconfig 3 files changed, 13 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83218/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index f1343f8..243e23e 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -575,15 +575,6 @@ mainboard directory to the build which contain the board-specific HD audio codec configuration. -config AZALIA_LOCK_DOWN_R_WO_GCAP - def_bool n - depends on AZALIA_HDA_CODEC_SUPPORT - help - The GCAP register is implemented as R/WO (Read / Write Once) on some - HD Audio controllers, such as Intel 6-series PCHs. Select this option - to lock down the GCAP register after deasserting the controller reset - bit. Locking is done by reading GCAP and writing back the read value. - config PCIEXP_PLUGIN_SUPPORT bool default y diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 02bbf89..4eed489 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -56,10 +56,19 @@ if (azalia_exit_reset(base) < 0) goto no_codec; - if (CONFIG(AZALIA_LOCK_DOWN_R_WO_GCAP)) { - /* If GCAP is R/WO, lock it down after deasserting controller reset */ - write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); - } + /* + * In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP + * register is RO (Read Only). However, it is known that in some Intel + * PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some + * of the bitfields in the GCAP register are R/WO (Read / Write Once). + * GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock + * bit for GCAP elsewhere. + * + * Lock GCAP by reading GCAP and writing back the same value. This has + * no effect on platforms that implement GCAP as a RO register or lock + * GCAP through a different mechanism. + */ + write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); /* clear STATESTS bits (BAR + 0x0e)[14:0] */ reg16 = read16(base + HDA_STATESTS_REG); diff --git a/src/soc/intel/common/block/hda/Kconfig b/src/soc/intel/common/block/hda/Kconfig index 64f34ef..a91764a 100644 --- a/src/soc/intel/common/block/hda/Kconfig +++ b/src/soc/intel/common/block/hda/Kconfig @@ -8,6 +8,5 @@ config SOC_INTEL_COMMON_BLOCK_HDA_VERB bool depends on SOC_INTEL_COMMON_BLOCK_HDA - select AZALIA_LOCK_DOWN_R_WO_GCAP help Enable initialization of HDA codecs. -- To view, visit https://review.coreboot.org/c/coreboot/+/83218?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id61e6976a455273e8c681dbeb4bad35d57b1a8a2 Gerrit-Change-Number: 83218 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: device/azalia_device.c: Use `azalia_enter_reset()`
by Angel Pons (Code Review) 26 Jun '24

26 Jun '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83217?usp=email ) Change subject: device/azalia_device.c: Use `azalia_enter_reset()` ...................................................................... device/azalia_device.c: Use `azalia_enter_reset()` Use the existing `azalia_enter_reset()` function instead of explicitly clearing the bit (and having to explain in a comment what this means). Change-Id: I04924e68420a93a1ad46f5a7ab359e38c0f7e210 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/azalia_device.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/83217/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 8051f2e..02bbf89 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -96,8 +96,7 @@ no_codec: /* Codec Not found */ - /* Put HDA back in reset (BAR + 0x8) [0] */ - azalia_set_bits(base + HDA_GCTL_REG, 1, 0); + azalia_enter_reset(base); printk(BIOS_DEBUG, "azalia_audio: no codec!\n"); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/83217?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04924e68420a93a1ad46f5a7ab359e38c0f7e210 Gerrit-Change-Number: 83217 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel: Adapt crashlog IP to also support 64-bit
by Angel Pons (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Nick Vaccaro, Paul Menzel, Pratikkumar V Prajapati, Sowmya Aralguppe, Tarun. Angel Pons has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email ) Change subject: soc/intel: Adapt crashlog IP to also support 64-bit ...................................................................... Patch Set 22: (1 comment) File src/soc/intel/meteorlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/83106/comment/4b21c231_f17b680a?us… : PS22, Line 355: if (!is_crashlog_data_valid(dw0)) This check is gone, is this intentional? -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 22 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 08:53:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: nb/intel/i945/{raminit,rcven}: Remove unnecessary hidden cast to (voi...
by Elyes Haouas (Code Review) 26 Jun '24

26 Jun '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83216?usp=email ) Change subject: nb/intel/i945/{raminit,rcven}: Remove unnecessary hidden cast to (void *) ...................................................................... nb/intel/i945/{raminit,rcven}: Remove unnecessary hidden cast to (void *) Change-Id: Ie3613fb917591f9dc6495a961c6f8c4dc8c7fdcc Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/rcven.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/83216/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a37754b..6894be7 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -76,7 +76,7 @@ { PRINTK_DEBUG(" RAM read: %" PRIxPTR "\n", offset); - read32p(offset); + read32(offset); } void sdram_dump_mchbar_registers(void) diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index 024a263..f263e0e 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -29,8 +29,8 @@ } for (i = 0; i < 28; i++) { - read32p(addr); - read32p(addr + 0x80); + read32(addr); + read32(addr + 0x80); } reg32 = mchbar_read32(RCVENMT); -- To view, visit https://review.coreboot.org/c/coreboot/+/83216?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie3613fb917591f9dc6495a961c6f8c4dc8c7fdcc Gerrit-Change-Number: 83216 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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