coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

1 participants
3527 discussions

[S] Change in coreboot[main]: Makefile: update clean-symlink target
by Eric Lai (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Felix Singer, Martin L Roth, Maximilian Brune. Eric Lai has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/83124?usp=email ) Change subject: Makefile: update clean-symlink target ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife0e7cf1b856b7394cd5e1de9b35856bd984663c Gerrit-Change-Number: 83124 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 08:07:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: drivers/spi/acpi: Add generic property list
by Eric Lai (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Jian Tong, Kun Liu, Paul Menzel, Subrata Banik. Eric Lai has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/83139?usp=email ) Change subject: drivers/spi/acpi: Add generic property list ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83139?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8 Gerrit-Change-Number: 83139 Gerrit-PatchSet: 8 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 08:06:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: arch/x86/mpspec: Use uintptr_t for mpc_apicaddr
by Elyes Haouas (Code Review) 26 Jun '24

26 Jun '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83215?usp=email ) Change subject: arch/x86/mpspec: Use uintptr_t for mpc_apicaddr ...................................................................... arch/x86/mpspec: Use uintptr_t for mpc_apicaddr Change-Id: I6cc2b3947a2c79e8962985e035e7cc74c2deb307 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/smp/mpspec.h M src/arch/x86/mpspec.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/83215/1 diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h index 80ae7e8..ee5e021 100644 --- a/src/arch/x86/include/arch/smp/mpspec.h +++ b/src/arch/x86/include/arch/smp/mpspec.h @@ -102,7 +102,7 @@ u8 mpc_apicver; u8 mpc_flags; #define MPC_APIC_USABLE 0x01 - void *mpc_apicaddr; + uintptr_t mpc_apicaddr; } __packed; struct mpc_config_intsrc { diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index d6f0cd5b..fde2ffa 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -215,7 +215,7 @@ mpc->mpc_apicid = id; mpc->mpc_apicver = ver; mpc->mpc_flags = MPC_APIC_USABLE; - mpc->mpc_apicaddr = (void *)apicaddr; + mpc->mpc_apicaddr = apicaddr; smp_add_mpc_entry(mc, sizeof(*mpc)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/83215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6cc2b3947a2c79e8962985e035e7cc74c2deb307 Gerrit-Change-Number: 83215 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[XS] Change in coreboot[main]: mb/google/lotso: Add hid report address for gt7986u
by Eric Lai (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Kun Liu. Eric Lai has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/83201?usp=email ) Change subject: mb/google/lotso: Add hid report address for gt7986u ...................................................................... Patch Set 2: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83201/comment/86ec1c66_2f3b882c?us… : PS2, Line 9: Add hid report address for gt7986u add . in the end https://review.coreboot.org/c/coreboot/+/83201/comment/10276796_f54b274f?us… : PS2, Line 13: TEST=Verify touchscreen work normal add . in the end -- To view, visit https://review.coreboot.org/c/coreboot/+/83201?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I464c2691505083314528519f608108c8a31e6cc0 Gerrit-Change-Number: 83201 Gerrit-PatchSet: 2 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 08:05:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: treewide/azalia: Make codec_detect() common and use it
by Eric Lai (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Angel Pons, Elyes Haouas. Eric Lai has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/83214?usp=email ) Change subject: treewide/azalia: Make codec_detect() common and use it ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7be3c0b1a90a766c5bb0f950c4dbac31a87c20f Gerrit-Change-Number: 83214 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 26 Jun 2024 08:04:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: treewide/azalia: Make codec_detect() common and use it
by Elyes Haouas (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Angel Pons, Elyes Haouas. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83214?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: treewide/azalia: Make codec_detect() common and use it ...................................................................... treewide/azalia: Make codec_detect() common and use it Change-Id: Ib7be3c0b1a90a766c5bb0f950c4dbac31a87c20f Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/device/azalia_device.c M src/include/device/azalia_device.h M src/northbridge/intel/haswell/minihd.c M src/soc/intel/baytrail/hda.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pch/hda.c M src/soc/intel/common/hda_verb.c M src/soc/intel/common/hda_verb.h M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/lynxpoint/azalia.c D src/southbridge/intel/lynxpoint/hda_verb.c D src/southbridge/intel/lynxpoint/hda_verb.h 12 files changed, 7 insertions(+), 133 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/83214/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7be3c0b1a90a766c5bb0f950c4dbac31a87c20f Gerrit-Change-Number: 83214 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
by Shuo Liu (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82252?usp=email ) Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/xeon_sp/acpi.c: https://review.coreboot.org/c/coreboot/+/82252/comment/19bad06f_a1415ca8?us… : PS4, Line 194: acpigen_write_BBN > missing _SEG Yeah ... there are indeed issues around here. I checked the ACPI spec and _SEG/_BBN should only be used for PCI host bridges, which is aligned to UEFI bootloader's usage as well. Hence I need to remove the _BBN here. 6.5.5 _BBN (Base Bus Number) For multi-root PCI platforms, the _BBN object evaluates to the PCI bus number that the platform boot firmware assigns. This is needed to access a PCI_Config operation region for the specific bus. The _BBN object is located under a PCI host bridge and must be unique for every host bridge within a segment since it is the PCI bus number. -- To view, visit https://review.coreboot.org/c/coreboot/+/82252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I434fea7880a463c2027abfa22ba2b3bb985815c0 Gerrit-Change-Number: 82252 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 07:35:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
by Shuo Liu (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82252?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port ...................................................................... soc/intel/xeon_sp: Add acpigen_write_pci_root_port acpigen_write_pci_root_port writes SSDT device objects for PCIe root port, _ADR and _BBN are provided. SSDT objects for direct subordinate devices will also be created (if detected), _ADR and _SUN are provided. TEST=Build and boot on intel/archercity CRB Change-Id: I434fea7880a463c2027abfa22ba2b3bb985815c0 Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h 2 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/82252/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/82252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I434fea7880a463c2027abfa22ba2b3bb985815c0 Gerrit-Change-Number: 82252 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

1 0

[M] Change in coreboot[main]: treewide/azalia: Make codec_detect() common and use it
by Elyes Haouas (Code Review) 26 Jun '24

26 Jun '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83214?usp=email ) Change subject: treewide/azalia: Make codec_detect() common and use it ...................................................................... treewide/azalia: Make codec_detect() common and use it Change-Id: Ib7be3c0b1a90a766c5bb0f950c4dbac31a87c20f Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/device/azalia_device.c M src/include/device/azalia_device.h M src/northbridge/intel/haswell/minihd.c M src/soc/intel/baytrail/hda.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pch/hda.c M src/soc/intel/common/hda_verb.c M src/soc/intel/common/hda_verb.h M src/southbridge/intel/lynxpoint/azalia.c D src/southbridge/intel/lynxpoint/hda_verb.c D src/southbridge/intel/lynxpoint/hda_verb.h 11 files changed, 7 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/83214/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 8051f2e..3841c58 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -48,7 +48,7 @@ return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST); } -static u16 codec_detect(u8 *base) +u16 codec_detect(u8 *base) { struct stopwatch sw; u16 reg16; diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 59e7ea2..3018df0 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -20,6 +20,7 @@ #define AZALIA_MAX_CODECS 15 +u16 codec_detect(u8 *base); int azalia_set_bits(void *port, u32 mask, u32 val); int azalia_enter_reset(u8 *base); int azalia_exit_reset(u8 *base); diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 6abc6c1..4e6fb6c 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -7,7 +7,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <southbridge/intel/lynxpoint/hda_verb.h> static const u32 minihd_verb_table[] = { /* coreboot specific header */ @@ -74,7 +73,7 @@ write32(base + 0x1010, reg32); /* Init the codec and write the verb table */ - codec_mask = hda_codec_detect(base); + codec_mask = codec_detect(base); if (codec_mask) { for (i = 3; i >= 0; i--) { diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index 46fbce1..d006408 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -68,7 +68,7 @@ return; base = res2mmio(res, 0, 0); - codec_mask = hda_codec_detect(base); + codec_mask = codec_detect(base); printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask); if (!codec_mask) diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index ee63501..ccca636 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -8,7 +8,6 @@ #include <device/pci_ops.h> #include <device/mmio.h> #include <soc/igd.h> -#include <southbridge/intel/lynxpoint/hda_verb.h> static const u32 minihd_verb_table[] = { /* coreboot specific header */ @@ -75,7 +74,7 @@ write32(base + 0x1010, reg32); /* Init the codec and write the verb table */ - codec_mask = hda_codec_detect(base); + codec_mask = codec_detect(base); if (codec_mask) { for (i = 3; i >= 0; i--) { diff --git a/src/soc/intel/broadwell/pch/hda.c b/src/soc/intel/broadwell/pch/hda.c index ad3d8e9..77acc0b 100644 --- a/src/soc/intel/broadwell/pch/hda.c +++ b/src/soc/intel/broadwell/pch/hda.c @@ -9,7 +9,6 @@ #include <device/mmio.h> #include <soc/pch.h> #include <soc/rcba.h> -#include <southbridge/intel/lynxpoint/hda_verb.h> static void hda_pch_init(struct device *dev, u8 *base) { @@ -76,7 +75,7 @@ hda_pch_init(dev, base); - codec_mask = hda_codec_detect(base); + codec_mask = codec_detect(base); if (codec_mask) { printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index dceb031..5a7b582 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -8,46 +8,6 @@ #include "hda_verb.h" -int hda_codec_detect(u8 *base) -{ - u8 reg8; - - /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (azalia_exit_reset(base) < 0) - goto no_codec; - - /* Write back the value once reset bit is set. */ - write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); - - /* - * Clear the "State Change Status Register" STATESTS bits - * for each of the "SDIN Stat Change Status Flag" - */ - write8(base + HDA_STATESTS_REG, 0xf); - - /* Turn off the link and poll RESET# bit until it reads back as 0 */ - if (azalia_enter_reset(base) < 0) - goto no_codec; - - /* Turn on the link and poll RESET# bit until it reads back as 1 */ - if (azalia_exit_reset(base) < 0) - goto no_codec; - - /* Read in Codec location (BAR + 0xe)[2..0] */ - reg8 = read8(base + HDA_STATESTS_REG); - reg8 &= 0x0f; - if (!reg8) - goto no_codec; - - return reg8; - -no_codec: - /* Codec not found, put HDA back in reset */ - azalia_enter_reset(base); - printk(BIOS_DEBUG, "HDA: No codec!\n"); - return 0; -} - /* * Wait 50usec for the codec to indicate it is ready. * No response would imply that the codec is non-operative. diff --git a/src/soc/intel/common/hda_verb.h b/src/soc/intel/common/hda_verb.h index ddd5774..53ca3ff 100644 --- a/src/soc/intel/common/hda_verb.h +++ b/src/soc/intel/common/hda_verb.h @@ -5,7 +5,6 @@ #include <stdint.h> -int hda_codec_detect(u8 *base); int hda_codec_write(u8 *base, u32 size, const u32 *data); int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data); diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 34f0753..0c85ea5 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -9,7 +9,6 @@ #include <device/azalia_device.h> #include "pch.h" -#include "hda_verb.h" static void azalia_pch_init(struct device *dev, u8 *base) { @@ -97,7 +96,7 @@ azalia_pch_init(dev, base); - codec_mask = hda_codec_detect(base); + codec_mask = codec_detect(base); if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c deleted file mode 100644 index 7e9f4d2..0000000 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/azalia_device.h> -#include <device/mmio.h> - -#include "hda_verb.h" - -int hda_codec_detect(u8 *base) -{ - u8 reg8; - - /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (azalia_exit_reset(base) < 0) - goto no_codec; - - /* Write back the value once reset bit is set. */ - write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); - - /* - * Clear the "State Change Status Register" STATESTS bits - * for each of the "SDIN Stat Change Status Flag" - */ - write8(base + HDA_STATESTS_REG, 0xf); - - /* Turn off the link and poll RESET# bit until it reads back as 0 */ - if (azalia_enter_reset(base) < 0) - goto no_codec; - - /* Turn on the link and poll RESET# bit until it reads back as 1 */ - if (azalia_exit_reset(base) < 0) - goto no_codec; - - /* Read in Codec location (BAR + 0xe)[2..0] */ - reg8 = read8(base + HDA_STATESTS_REG); - reg8 &= 0x0f; - if (!reg8) - goto no_codec; - - return reg8; - -no_codec: - /* Codec not found, put HDA back in reset */ - azalia_enter_reset(base); - printk(BIOS_DEBUG, "HDA: No codec!\n"); - return 0; -} diff --git a/src/southbridge/intel/lynxpoint/hda_verb.h b/src/southbridge/intel/lynxpoint/hda_verb.h deleted file mode 100644 index 1d6ef39..0000000 --- a/src/southbridge/intel/lynxpoint/hda_verb.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef LYNXPOINT_HDA_VERB_H -#define LYNXPOINT_HDA_VERB_H - -#include <stdint.h> - -int hda_codec_detect(u8 *base); - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/83214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7be3c0b1a90a766c5bb0f950c4dbac31a87c20f Gerrit-Change-Number: 83214 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[S] Change in coreboot[main]: acpi: Add support for DRHD size reporting
by Shuo Liu (Code Review) 25 Jun '24

25 Jun '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jeff Daly, Jincheng Li, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lance Zhao, Lean Sheng Tan, Nick Vaccaro, Nico Huber, Patrick Rudolph, Paul Menzel, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Werner Zeh. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82429?usp=email ) Change subject: acpi: Add support for DRHD size reporting ...................................................................... Patch Set 17: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82429/comment/3babc5ce_5da3a431?us… : PS10, Line 18: TEST=Build and boot on intel/archercity CRB > SPR has DRHD size as 4KB, the same as the default DRHD setting if size is not specified, and hence n […] Please allow me to close the now and please feel free to raise new opens if any? File src/acpi/acpi_dmar.c: https://review.coreboot.org/c/coreboot/+/82429/comment/39f7cfcd_cc58b892?us… : PS16, Line 42: u16 segment, u64 bar) > nit: […] Done https://review.coreboot.org/c/coreboot/+/82429/comment/a3628836_abd884ed?us… : PS16, Line 44: 1 > Since you kept the `size` parameter in bytes: […] Sorry, good catch. https://review.coreboot.org/c/coreboot/+/82429/comment/48eab6c5_ab079e6b?us… : PS16, Line 48: u16 segment, u64 bar, u32 size) > nit: […] Done https://review.coreboot.org/c/coreboot/+/82429/comment/4de73f14_2f924773?us… : PS16, Line 60: * Refer to chapter 8.3 of https://cdrdv2.intel.com/v1/dl/getContent/671081 > This is true for the the whole _drhd functions, maybe place above? […] Done https://review.coreboot.org/c/coreboot/+/82429/comment/fe5d6634_ff7f59d7?us… : PS16, Line 68: (1 << (drhd->size + 12) > If `size` is less than 4 KiB and `drhd->size` ends up being 0, it is treated as if it were 1 (4 KiB) […] Done File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/82429/comment/50b818c6_9a7ccb20?us… : PS16, Line 1855: u32 > (`size` can't be greater than 128 MiB anyway, but yes. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82429?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I49dd5de2eca257a5f6240e36d05755cabca96d1c Gerrit-Change-Number: 82429 Gerrit-PatchSet: 17 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 06:58:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2024