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Change subject: drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC
......................................................................
Patch Set 3:
(1 comment)
File src/include/sar.h:
https://review.coreboot.org/c/coreboot/+/81790/comment/ab955cee_56e440c4?us… :
PS2, Line 65: __packed
> any reason for using `packed`?
I think this maps to the SAR file format therefore packed is needed.
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Change subject: drivers/wifi: Support Bluetooth Regulator Domain Settings
......................................................................
Patch Set 4:
This change is ready for review.
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Change subject: lib/malloc.c: Move heap as part of BSS
......................................................................
Patch Set 4:
(1 comment)
File tests/lib/malloc-test.c:
https://review.coreboot.org/c/coreboot/+/82421/comment/f20553f1_50a10b24?us… :
PS4, Line 34: TEST_SYMBOL(heap, _test_heap);
I'm not really sure there's a point for any of these four lines in this test. TEST_SYMBOL() and TEST_REGION() are only necessary when you need to mock a particular linker script symbol name because the coreboot code under test directly accesses that symbol. In this test I think all they needed was a local byte array.
And now, that you have the byte array in malloc.c already, I think the test can just use it? I think all you need to do here is have `setup_test()` reinitialize the three globals to point to the full array again.
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Change subject: lib/*stage_cache: Don't save BSS in stage cache
......................................................................
Patch Set 12:
(3 comments)
File src/include/program_loading.h:
https://review.coreboot.org/c/coreboot/+/82419/comment/363587ce_1713f56c?us… :
PS12, Line 106: flen
prog_set_fsize?
File src/lib/cbfs.c:
https://review.coreboot.org/c/coreboot/+/82419/comment/76a0991d_e6f3d0f7?us… :
PS12, Line 576: prog_set_area(pstage, (void *)(uintptr_t)be64toh(sattr->loadaddr), be32toh(sattr->memlen));
Unclear why you remove the line break here? It looks like it doesn't fit 96 chars... (or are we doing 100 chars now? I might have missed that memo).
File src/lib/rmodule.c:
https://review.coreboot.org/c/coreboot/+/82419/comment/048791a6_b54a49c3?us… :
PS12, Line 71: return module->header->bss_begin;
I think(?) this should technically be `module->header->bss_begin - module->header->module_link_start_address`, even though the latter may always be 0 in practice (cf. `rmodule_entry_offset()`).
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The following approvals got outdated and were removed:
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Change subject: drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC
......................................................................
drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC
Add support for the configuration of 320MHz Bandwidth per MCC based on
countries. The implementation follows document #559910 Intel
Connectivity Platforms BIOS Guidelines revision 8.3.
BUG=b:333804562
BRANCH=firmware-rex-15709.B
TEST=WBEM method is added to the CNVW device and return the data
supplied by the SAR binary blob
Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17
Signed-off-by: Poornima Tom <poornima.tom(a)intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/wifi/generic/acpi.c
M src/include/sar.h
M src/vendorcode/google/chromeos/sar.c
3 files changed, 49 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81790/3
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Change subject: commonlib/device_tree: Improve node and property allocation speed
......................................................................
Patch Set 2:
(1 comment)
File src/commonlib/device_tree.c:
https://review.coreboot.org/c/coreboot/+/83208/comment/93a726c1_cf76889b?us… :
PS2, Line 37: 2000
> nit: `#define` the constants
Done
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Hello Maximilian Brune, Patrick Rudolph, Raul Rangel, Reka Norman, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83208?usp=email
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Change subject: commonlib/device_tree: Improve node and property allocation speed
......................................................................
commonlib/device_tree: Improve node and property allocation speed
Now that the device tree code has been made available in libpayload, we
should reintroduce the node and property allocation optimization for
libpayload's memory allocator that was originally dropped when porting
this code from depthcharge to coreboot.
On a Qualcomm SC7180 unflattening a normal ChromeOS kernel device tree,
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Change-Id: I0f4d80a8b750febfb069b32ef47304ccecdc35af
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M src/commonlib/device_tree.c
1 file changed, 41 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/83208/3
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Change subject: mb/google/lotso: Add hid report address for gt7986u
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83201/comment/e75ea59b_5fc4dbbc?us… :
PS1, Line 7: lotso
> "mb/google/lotso"
Done
https://review.coreboot.org/c/coreboot/+/83201/comment/b246232c_2f53eef1?us… :
PS1, Line 10:
> It would be good to mention the datasheet name and version which was used or any place from where th […]
This information is provided by the manufacturer,please refer to the following comments for details
https://partnerissuetracker.corp.google.com/issues/342932183#comment4
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