coreboot-gerrit June 2024

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[S] Change in coreboot[main]: include/device_tree.h: Fix function name fdt_node_name
by Yu-Ping Wu (Code Review) 25 Jun '24

25 Jun '24

Attention is currently required from: Felix Singer, Julius Werner, Maximilian Brune. Yu-Ping Wu has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83084?usp=email ) Change subject: include/device_tree.h: Fix function name fdt_node_name ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I527146df26264a0c3af1ad01c21644d751b80236 Gerrit-Change-Number: 83084 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 26 Jun 2024 05:09:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: lib/fit: Fix non-existent function fdt_node_name()
by Yu-Ping Wu (Code Review) 25 Jun '24

25 Jun '24

Yu-Ping Wu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/83213?usp=email ) Change subject: lib/fit: Fix non-existent function fdt_node_name() ...................................................................... Abandoned Duplicate of CB:83084 -- To view, visit https://review.coreboot.org/c/coreboot/+/83213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I417f0cc9dbe4d04644597d59ec98e9e8d2e951fc Gerrit-Change-Number: 83213 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: mb/google/brask/var/bujia: Configure Serial IO UARTs Mode
by Subrata Banik (Code Review) 25 Jun '24

25 Jun '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Shon Wang. Subrata Banik has posted comments on this change by Shon Wang. ( https://review.coreboot.org/c/coreboot/+/83205?usp=email ) Change subject: mb/google/brask/var/bujia: Configure Serial IO UARTs Mode ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38 Gerrit-Change-Number: 83205 Gerrit-PatchSet: 5 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 05:05:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: lib/fit: Fix non-existent function fdt_node_name()
by Yu-Ping Wu (Code Review) 25 Jun '24

25 Jun '24

Yu-Ping Wu has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83213?usp=email ) Change subject: lib/fit: Fix non-existent function fdt_node_name() ...................................................................... lib/fit: Fix non-existent function fdt_node_name() fdt_node_name() was renamed to fdt_next_node_name() in CB:81081. Fix the caller in fit.c. Change-Id: I417f0cc9dbe4d04644597d59ec98e9e8d2e951fc Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/lib/fit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/83213/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I417f0cc9dbe4d04644597d59ec98e9e8d2e951fc Gerrit-Change-Number: 83213 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: lib/fit: Fix non-existing function fdt_node_name()
by Yu-Ping Wu (Code Review) 25 Jun '24

25 Jun '24

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83213?usp=email ) Change subject: lib/fit: Fix non-existing function fdt_node_name() ...................................................................... lib/fit: Fix non-existing function fdt_node_name() fdt_node_name() was renamed to fdt_next_node_name() in CB:81081. Fix the caller in fit.c. Change-Id: I417f0cc9dbe4d04644597d59ec98e9e8d2e951fc Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/lib/fit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/83213/1 diff --git a/src/lib/fit.c b/src/lib/fit.c index 7f0fe67..3bfca57 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -178,7 +178,7 @@ int offset = start_offset; int size; - size = fdt_node_name(blob, offset, NULL); + size = fdt_next_node_name(blob, offset, NULL); if (!size) return -1; offset += size; -- To view, visit https://review.coreboot.org/c/coreboot/+/83213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I417f0cc9dbe4d04644597d59ec98e9e8d2e951fc Gerrit-Change-Number: 83213 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: mb/google/brox: Create jubilant variant
by Ren Kuo (Code Review) 25 Jun '24

25 Jun '24

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83212?usp=email ) Change subject: mb/google/brox: Create jubilant variant ...................................................................... mb/google/brox: Create jubilant variant Create the jubilant variant of the brox reference board by copying the template files to a new directory named for the variant. BUG=b:348543712 BRANCH=None TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_JUBILANT. Change-Id: Ic54437697058f8bce2167093bd88c0880d1b7cac --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brox/Kconfig.name A src/mainboard/google/brox/variants/jubilant/Makefile.mk A src/mainboard/google/brox/variants/jubilant/data.vbt A src/mainboard/google/brox/variants/jubilant/fw_config.c A src/mainboard/google/brox/variants/jubilant/gpio.c A src/mainboard/google/brox/variants/jubilant/include/variant/ec.h A src/mainboard/google/brox/variants/jubilant/include/variant/gpio.h A src/mainboard/google/brox/variants/jubilant/include/variant/hda_verb.h A src/mainboard/google/brox/variants/jubilant/memory/Makefile.mk A src/mainboard/google/brox/variants/jubilant/memory/dram_id.generated.txt A src/mainboard/google/brox/variants/jubilant/memory/mem_parts_used.txt A src/mainboard/google/brox/variants/jubilant/overridetree.cb A src/mainboard/google/brox/variants/jubilant/ramstage.c A src/mainboard/google/brox/variants/jubilant/variant.c 15 files changed, 665 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/83212/1 diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 2637e89..47a9e79 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -74,6 +74,11 @@ select CHROMEOS_WIFI_SAR if CHROMEOS select MEMORY_SODIMM +config BOARD_GOOGLE_JUBILANT + select BOARD_GOOGLE_BASEBOARD_BROX + select CHROMEOS_WIFI_SAR if CHROMEOS + select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS + if BOARD_GOOGLE_BROX_COMMON config BASEBOARD_DIR @@ -126,11 +131,13 @@ default "Brox" if BOARD_GOOGLE_BROX default "Lotso" if BOARD_GOOGLE_LOTSO default "Greenbayupoc" if BOARD_GOOGLE_GREENBAYUPOC + default "Jubilant" if BOARD_GOOGLE_JUBILANT config VARIANT_DIR default "brox" if BOARD_GOOGLE_BROX || BOARD_GOOGLE_BROX_EC_ISH default "lotso" if BOARD_GOOGLE_LOTSO default "greenbayupoc" if BOARD_GOOGLE_GREENBAYUPOC + default "jubilant" if BOARD_GOOGLE_JUBILANT config VBOOT select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/brox/Kconfig.name b/src/mainboard/google/brox/Kconfig.name index ae8f5ea..88302ff 100644 --- a/src/mainboard/google/brox/Kconfig.name +++ b/src/mainboard/google/brox/Kconfig.name @@ -13,3 +13,6 @@ config BOARD_GOOGLE_GREENBAYUPOC bool "-> Greenbayupoc" + +config BOARD_GOOGLE_JUBILANT + bool "-> Jubilant" diff --git a/src/mainboard/google/brox/variants/jubilant/Makefile.mk b/src/mainboard/google/brox/variants/jubilant/Makefile.mk new file mode 100644 index 0000000..4a7ff71 --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brox/variants/jubilant/data.vbt b/src/mainboard/google/brox/variants/jubilant/data.vbt new file mode 100644 index 0000000..716d09f --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/data.vbt Binary files differ diff --git a/src/mainboard/google/brox/variants/jubilant/fw_config.c b/src/mainboard/google/brox/variants/jubilant/fw_config.c new file mode 100644 index 0000000..3962991 --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/fw_config.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <drivers/intel/ish/chip.h> +#include <fw_config.h> +#include <gpio.h> + +#define GPIO_PADBASED_OVERRIDE(b, a) gpio_padbased_override(b, a, ARRAY_SIZE(a)) +#define ISH_FIRMWARE_NAME "brox_ish.bin" + +static const struct pad_config ish_enable_pads[] = { + /* GPP_A16 : ISH_GP5, TABLET_MODE_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF4), + /* GPP_B5 : ISH I2C0_SDA */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1), + /* GPP_B6 : ISH_I2C0_SCL */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1), + /* GPP_B15 : ISH_GP7, LID_OPEN_1V8 */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF5), + /* GPP_D2 : ISH_GP2, SOC_ISH_ACCEL_INT_L */ + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + /* GPP_D3 : ISH_GP3, SOC_ISH_IMU_INT_L */ + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + /* GPP_D13 : [NF1: ISH_UART0_RXD ==> UART0_ISH_RX_DBG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* GPP_D14 : [NF1: ISH_UART0_TXD ==> UART0_ISH_TX_DBG_RX */ + PAD_CFG_NF(GPP_D14, DN_20K, DEEP, NF1), + /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */ + PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF2), +}; + +static void fw_config_handle(void *unused) +{ + struct device *ish_config_device = DEV_PTR(ish_conf); + struct drivers_intel_ish_config *config = config_of(ish_config_device); + + if (fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) { + printk(BIOS_INFO, "Configure GPIOs, device config for ISH.\n"); + gpio_configure_pads(ish_enable_pads, ARRAY_SIZE(ish_enable_pads)); + + config->firmware_name = ISH_FIRMWARE_NAME; + } + + if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { + printk(BIOS_INFO, "Configure GPIOs, device config for UFS.\n"); + config->add_acpi_dma_property = true; + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brox/variants/jubilant/gpio.c b/src/mainboard/google/brox/variants/jubilant/gpio.c new file mode 100644 index 0000000..5af3552 --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/gpio.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <boardid.h> +#include <soc/gpio.h> + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/brox/variants/jubilant/include/variant/ec.h b/src/mainboard/google/brox/variants/jubilant/include/variant/ec.h new file mode 100644 index 0000000..4fc0622 --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/brox/variants/jubilant/include/variant/gpio.h b/src/mainboard/google/brox/variants/jubilant/include/variant/gpio.h new file mode 100644 index 0000000..3179c6f --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#define T1_OFF_MS 16 +#define T2_OFF_MS 2 +#define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_E16 +#define WWAN_PERST GPP_E0 + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/brox/variants/jubilant/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/jubilant/include/variant/hda_verb.h new file mode 100644 index 0000000..c0b0eb0 --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/include/variant/hda_verb.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_HDA_VERB_H +#define MAINBOARD_HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 + 0x10ec12ac, // Subsystem ID + 0x00000013, // Number of jacks (NID entries) + + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb table */ + AZALIA_SUBVENDOR(0, 0x10ec12ac), + + /* Pin Widget Verb Table */ + + /* + * DMIC + * Requirement is to use PCH DMIC. Hence, + * commented out codec's Internal DMIC. + * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + */ + + /* Pin widget 0x14 - Front (Port-D) */ + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + /* Pin widget 0x18 - NPC */ + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + /* Pin widget 0x19 - MIC2 (Port-F) */ + AZALIA_PIN_CFG(0, 0x19, 0x04A11040), + /* Pin widget 0x1A - LINE1 (Port-C) */ + AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), + /* Pin widget 0x1B - NPC */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), + /* Pin widget 0x1D - BEEP-IN */ + AZALIA_PIN_CFG(0, 0x1d, 0x40610041), + /* Pin widget 0x1E - NPC */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), + /* Pin widget 0x21 - HP1-OUT (Port-I) */ + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + /* + * Widget node 0x20 - 1 + * Codec hidden reset and speaker power 2W/4ohm + */ + 0x0205001A, + 0x0204C003, + 0x02050038, + 0x02047901, + /* + * Widget node 0x20 - 2 + * Class D power on Reset + */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* + * Widget node 0x20 - 3 + * Disable AGC and set AGC limit to -1.5dB + */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC1, + /* + * Widget node 0x20 - 4 + * Set AGC Post gain +1.5dB then Enable AGC + */ + 0x02050013, + 0x02044023, + 0x02050016, + 0x02040E50, + /* + * Widget node 0x20 - 5 + * Silence detector enabling + Set EAPD to verb control + */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* + * Widget node 0x20 - 6 + * Silence data mode Threshold (-90dB) + */ + 0x02050030, + 0x0204A000, + 0x0205001B, + 0x02040A4B, + /* + * Widget node 0x20 - 7 + * Default setting - 1 + */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* + * Widget node 0x20 - 8 + * support 1 pin detect two port + */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* + * Widget node 0x20 - 9 + * To set LDO1/LDO2 as default (used for headset) + */ + 0x02050008, + 0x02046A0C, + 0x02050008, + 0x02046A0C, +}; + +const u32 pc_beep_verbs[] = { + /* Dos beep path - 1 */ + 0x01470C00, + 0x02050036, + 0x02047151, + 0x01470740, + /* Dos beep path - 2 */ + 0x0143b000, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/google/brox/variants/jubilant/memory/Makefile.mk b/src/mainboard/google/brox/variants/jubilant/memory/Makefile.mk new file mode 100644 index 0000000..380edbf --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/memory/Makefile.mk @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = MT62F1G32D2DS-023 WT:B diff --git a/src/mainboard/google/brox/variants/jubilant/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/jubilant/memory/dram_id.generated.txt new file mode 100644 index 0000000..d6224cc --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/memory/dram_id.generated.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) +H9JCNNNBK3MLYR-N6E 0 (0000) +MT62F1G32D4DR-031 WT:B 1 (0001) +MT62F1G32D2DS-023 WT:B 2 (0010) diff --git a/src/mainboard/google/brox/variants/jubilant/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/jubilant/memory/mem_parts_used.txt new file mode 100644 index 0000000..f5c81a3 --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/memory/mem_parts_used.txt @@ -0,0 +1,4 @@ +MT62F512M32D2DR-031 WT:B +H9JCNNNBK3MLYR-N6E +MT62F1G32D4DR-031 WT:B +MT62F1G32D2DS-023 WT:B diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb new file mode 100644 index 0000000..21774f8 --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -0,0 +1,335 @@ +fw_config + field RETIMER 0 1 + option RETIMER_UNKNOWN 0 + option RETIMER_BYPASS 1 + option RETIMER_JHL8040 2 + end + field STORAGE 2 3 + option STORAGE_UNKNOWN 0 + option STORAGE_UFS 1 + option STORAGE_NVME 2 + end + field WIFI_BT 4 4 + option WIFI_BT_CNVI 0 + option WIFI_BT_PCIE 1 + end + field AUDIO 5 7 + option AUDIO_UNKNOWN 0 + option AUDIO_REALTEK_ALC256 1 + end + field UFC 8 9 + option UFC_NONE 0 + option UFC_OV2740 1 + end + field ISH 21 + option ISH_DISABLE 0 + option ISH_ENABLE 1 + end +end + +chip soc/intel/alderlake + register "platform_pmax" = "208" + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Fan-Inlet"" + + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(95, 90), + TEMP_PCT(92, 80), + TEMP_PCT(89, 60), + TEMP_PCT(85, 40), + TEMP_PCT(80, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(54, 95), + TEMP_PCT(52, 90), + TEMP_PCT(50, 80), + TEMP_PCT(48, 50), + TEMP_PCT(46, 30), + TEMP_PCT(44, 25), + TEMP_PCT(42, 20), + TEMP_PCT(40, 15), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(54, 95), + TEMP_PCT(52, 90), + TEMP_PCT(50, 80), + TEMP_PCT(48, 50), + TEMP_PCT(46, 30), + TEMP_PCT(44, 25), + TEMP_PCT(42, 20), + TEMP_PCT(40, 15), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 97, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end # DTT + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 + register "device[3].name" = ""DD03"" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 SD Bridge"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DCI)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DCI)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port3 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 3 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 3, + .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe STORAGE STORAGE_NVME + end + device ref pcie_rp5 on + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on + probe WIFI_BT WIFI_BT_PCIE + end + end + chip soc/intel/common/block/pcie/rtd3 + # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "1" + device generic 0 on end + end + probe WIFI_BT WIFI_BT_PCIE + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + probe WIFI_BT WIFI_BT_CNVI + end + device ref ish on + chip drivers/intel/ish + device generic 0 alias ish_conf on end + end + probe ISH ISH_ENABLE + probe STORAGE STORAGE_UFS + end + device ref ufs on + probe STORAGE STORAGE_UFS + end + end +end diff --git a/src/mainboard/google/brox/variants/jubilant/ramstage.c b/src/mainboard/google/brox/variants/jubilant/ramstage.c new file mode 100644 index 0000000..86418da --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/ramstage.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/power_limit.h> + +/* + * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), + * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) + * Following values are for performance config as per document #640982 + */ + +const struct cpu_power_limits performance_efficient_limits[] = { + { + .mchid = PCI_DID_INTEL_RPL_P_ID_3, + .cpu_tdp = 15, + .pl1_min_power = 6000, + .pl1_max_power = 15000, + .pl2_min_power = 55000, + .pl2_max_power = 55000, + .pl4_power = 114000 + }, + { + .mchid = PCI_DID_INTEL_RPL_P_ID_4, + .cpu_tdp = 15, + .pl1_min_power = 6000, + .pl1_max_power = 15000, + .pl2_min_power = 55000, + .pl2_max_power = 55000, + .pl4_power = 114000 + }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DID_INTEL_RPL_P_ID_3, 15, 60 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 60 }, +}; + +const struct psys_config psys_config = { + .efficiency = 86, +}; + +void __weak variant_devtree_update(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + + const struct cpu_power_limits *limits = performance_efficient_limits; + size_t limits_size = ARRAY_SIZE(performance_efficient_limits); + + variant_update_power_limits(limits, limits_size); + variant_update_psys_power_limits(limits, sys_limits, limits_size, &psys_config); +} diff --git a/src/mainboard/google/brox/variants/jubilant/variant.c b/src/mainboard/google/brox/variants/jubilant/variant.c new file mode 100644 index 0000000..e085a86 --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/variant.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <baseboard/variants.h> +#include <chip.h> +#include <fw_config.h> +#include <sar.h> + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (fw_config_probe(FW_CONFIG(WIFI_BT, WIFI_BT_CNVI))) { + printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); + config->cnvi_bt_core = true; + } +} + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_BT)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/83212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic54437697058f8bce2167093bd88c0880d1b7cac Gerrit-Change-Number: 83212 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/intel: Adapt crashlog IP to also support 64-bit
by Subrata Banik (Code Review) 25 Jun '24

25 Jun '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Paul Menzel, Pratikkumar V Prajapati, Sowmya Aralguppe, Tarun. Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email ) Change subject: soc/intel: Adapt crashlog IP to also support 64-bit ...................................................................... Patch Set 22: Code-Review+1 (1 comment) Patchset: PS22: @th3fanbus@gmail.com, wondering if this is okay to approve this CL ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 22 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 03:29:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC
by Shuo Liu (Code Review) 25 Jun '24

25 Jun '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83136?usp=email ) Change subject: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/xeon_sp/spr/ioat.c: https://review.coreboot.org/c/coreboot/+/83136/comment/2d5e7f11_5114fae3?us… : PS8, Line 141: pcidev_on_root(0, 0) > Is this always true? e.g. […] Each socket will have IOAT, and all VTd bar in the SoC has the same size. Here we just use 00:0.0 to probe the bar size since this is the only known device that could be used to probe the size at this call site (where domain are created but device are not probed, and still quite early). -- To view, visit https://review.coreboot.org/c/coreboot/+/83136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8 Gerrit-Change-Number: 83136 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 02:28:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[M] Change in coreboot[main]: drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC
by Jérémy Compostella (Code Review) 25 Jun '24

25 Jun '24

Attention is currently required from: Bob Moragues, Bora Guvendik, Cliff Huang, Hannah Williams, Jérémy Compostella, Poornima Tom, Ravishankar Sarawadi, Subrata Banik, dinesh.sharma(a)intel.com. Jérémy Compostella has uploaded a new patch set (#5) to the change originally created by Poornima Tom. ( https://review.coreboot.org/c/coreboot/+/81790?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC ...................................................................... drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC Add support for the configuration of 320MHz Bandwidth per MCC based on countries. The implementation follows document #559910 Intel Connectivity Platforms BIOS Guidelines revision 8.3. BUG=b:333804562 BRANCH=firmware-rex-15709.B TEST=WBEM method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Signed-off-by: Poornima Tom <poornima.tom(a)intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/wifi/generic/acpi.c M src/include/sar.h M src/vendorcode/google/chromeos/sar.c 3 files changed, 49 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81790/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Gerrit-Change-Number: 81790 Gerrit-PatchSet: 5 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dinesh.sharma(a)intel.com Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Dinesh Sharma <dinesh.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-CC: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: dinesh.sharma(a)intel.com Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com>

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[M] Change in coreboot[main]: drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC
by Jérémy Compostella (Code Review) 25 Jun '24

25 Jun '24

Attention is currently required from: Bob Moragues, Bora Guvendik, Cliff Huang, Hannah Williams, Jérémy Compostella, Poornima Tom, Ravishankar Sarawadi, Subrata Banik, dinesh.sharma(a)intel.com. Jérémy Compostella has uploaded a new patch set (#4) to the change originally created by Poornima Tom. ( https://review.coreboot.org/c/coreboot/+/81790?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC ...................................................................... drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC Add support for the configuration of 320MHz Bandwidth per MCC based on countries. The implementation follows document #559910 Intel Connectivity Platforms BIOS Guidelines revision 8.3. BUG=b:333804562 BRANCH=firmware-rex-15709.B TEST=WBEM method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Signed-off-by: Poornima Tom <poornima.tom(a)intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/wifi/generic/acpi.c M src/include/sar.h M src/vendorcode/google/chromeos/sar.c 3 files changed, 49 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81790/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Gerrit-Change-Number: 81790 Gerrit-PatchSet: 4 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dinesh.sharma(a)intel.com Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Dinesh Sharma <dinesh.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-CC: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: dinesh.sharma(a)intel.com Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com>

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