coreboot-gerrit June 2024

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[L] Change in coreboot[main]: include/commonlib/sot.h: Add SOT structs
by Lean Sheng Tan (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Elyes Haouas, Martin L Roth, Maximilian Brune, Patrick Rudolph, Sean Rhodes. Lean Sheng Tan has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/77882?usp=email ) Change subject: include/commonlib/sot.h: Add SOT structs ...................................................................... Patch Set 14: Code-Review+1 (3 comments) File Documentation/drivers/cfr.md: https://review.coreboot.org/c/coreboot/+/77882/comment/0c6825bb_b17554fb?us… : PS9, Line 21: The coreboot table is generated from coreboot ramstage : code. : > Any thoughts @gaumless@gmail. […] Acknowledged https://review.coreboot.org/c/coreboot/+/77882/comment/51f6ff8c_2cbd6bd0?us… : PS9, Line 25: tatus flags. > Any thoughts @gaumless@gmail. […] Acknowledged File src/commonlib/include/commonlib/cfr.h: https://review.coreboot.org/c/coreboot/+/77882/comment/073d204b_f7a81ba8?us… : PS9, Line 102: > Any thoughts @gaumless@gmail. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/77882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f006318a15556f97da286dc032c58ccb7993e4 Gerrit-Change-Number: 77882 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 26 Jun 2024 13:48:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com>

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[M] Change in coreboot[main]: soc/intel: Adapt crashlog IP to also support 64-bit
by Subrata Banik (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Nick Vaccaro, Paul Menzel, Pratikkumar V Prajapati, Sowmya Aralguppe, Tarun. Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email ) Change subject: soc/intel: Adapt crashlog IP to also support 64-bit ...................................................................... Patch Set 22: (1 comment) Patchset: PS22: > The pointer typecast correction is part of 64-bit support unable to follow, are you saying the CPU crashlog size was incorrect in the original implementation ? if so, then while using crashlog tool, i should have received an error while parsing the crashlog. But that was never been the case previously. -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 22 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 13:44:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: device/azalia_device.c: Use `azalia_enter_reset()`
by Felix Singer (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Angel Pons, Arthur Heymans, Nico Huber. Felix Singer has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/83217?usp=email ) Change subject: device/azalia_device.c: Use `azalia_enter_reset()` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83217?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04924e68420a93a1ad46f5a7ab359e38c0f7e210 Gerrit-Change-Number: 83217 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 26 Jun 2024 11:45:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: skl mainboards/dt: Move SsicPortEnable setting into XHCI device scope
by Felix Singer (Code Review) 26 Jun '24

26 Jun '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83189?usp=email ) Change subject: skl mainboards/dt: Move SsicPortEnable setting into XHCI device scope ...................................................................... skl mainboards/dt: Move SsicPortEnable setting into XHCI device scope Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83189 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Marvin Evers <marvin.n.evers(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb 4 files changed, 8 insertions(+), 14 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Marvin Evers: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 8a3161a..9d4c0d9 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -41,10 +41,6 @@ # RP17, uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7" - # USB related - register "SsicPortEnable" = "1" - - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -66,6 +62,8 @@ device domain 0 on device ref south_xhci on + register "SsicPortEnable" = "1" + register "usb2_ports" = "{ [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ [1] = USB2_PORT_MID(OC3), /* Touch Pad */ diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 0af8282..7de1454 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -71,9 +71,6 @@ # RP10, uses CLK SRC 4 register "PcieRpClkSrcNumber[9]" = "4" - - register "SsicPortEnable" = "1" # Enable SSIC for WWAN - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -91,6 +88,8 @@ device domain 0 on device ref south_xhci on + register "SsicPortEnable" = "1" # Enable SSIC for WWAN + register "usb2_ports" = "{ [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 010312c..eb13212 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -93,9 +93,6 @@ register "PcieRpClkReqNumber[8]" = "6" register "PcieRpClkReqNumber[16]" = "7" - - register "SsicPortEnable" = "1" # Enable SSIC for WWAN - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -118,6 +115,8 @@ device domain 0 on device ref south_xhci on + register "SsicPortEnable" = "1" # Enable SSIC for WWAN + register "usb2_ports" = "{ [0] = USB2_PORT_MAX(OC2), /* Type-C Port */ [1] = USB2_PORT_MAX(OC5), /* Front panel */ diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 2f5058d..c92377a 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -120,10 +120,6 @@ register "PcieRpClkReqNumber[5]" = "0" register "PcieRpClkReqNumber[12]" = "1" - # USB related - register "SsicPortEnable" = "1" - - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V # Must leave UART0 enabled or SD/eMMC will not work as PCI @@ -156,6 +152,8 @@ device domain 0 on device ref igpu on end device ref south_xhci on + register "SsicPortEnable" = "1" + register "usb2_ports" = "{ [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ [1] = USB2_PORT_MID(OC3), /* Touch Pad */ -- To view, visit https://review.coreboot.org/c/coreboot/+/83189?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3 Gerrit-Change-Number: 83189 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: skl mainboards/dt: Move serirq setting into LPC device scope
by Felix Singer (Code Review) 26 Jun '24

26 Jun '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83188?usp=email ) Change subject: skl mainboards/dt: Move serirq setting into LPC device scope ...................................................................... skl mainboards/dt: Move serirq setting into LPC device scope Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83188 Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm> Reviewed-by: Marvin Evers <marvin.n.evers(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb 11 files changed, 25 insertions(+), 27 deletions(-) Approvals: Marvin Evers: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, but someone else must approve build bot (Jenkins): Verified Jonathon Hall: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved Erik van den Bogaert: Looks good to me, but someone else must approve diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 1f2fa40..3ffc00f 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -39,8 +39,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enable Root Ports 3, 4 and 9 register "PcieRpEnable[2]" = "1" # Ethernet controller register "PcieRpClkReqSupport[2]" = "1" @@ -116,6 +114,8 @@ device ref pcie_rp4 on end device ref pcie_rp9 on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index c41a26f..763a380 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -18,9 +18,6 @@ register "lpc_iod" = "0x0070" register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66" - # LPC serial IRQ - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # "Intel SpeedStep Technology" register "eist_enable" = "1" @@ -214,6 +211,8 @@ device ref uart0 on end device ref emmc on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + # CPLD host command ranges are in 0x280-0x2BF # EC PNP registers are at 0x6e and 0x6f register "gen1_dec" = "0x003c0281" diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 49edccb..8a3161a 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -4,8 +4,6 @@ register "DspEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enable PCIE slot register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" @@ -119,5 +117,8 @@ device ref sdxc off end device ref hda on end device ref gbe on end + device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + end end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 5516fee..010312c 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -7,8 +7,6 @@ # FSP Configuration register "ScsEmmcHs400Enabled" = "0" - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | @@ -173,6 +171,8 @@ device ref emmc off end device ref sdxc off end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + #chip drivers/pc80/tpm # device pnp 0c31.0 on end #end diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 73df651..2f5058d 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -32,8 +32,6 @@ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03" - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | @@ -217,6 +215,9 @@ device ref gspi1 on end device ref hda on end device ref smbus on end + device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + end device ref fast_spi on end device ref gbe on end end diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 02c3538..2ebc6702 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -9,8 +9,6 @@ register "eist_enable" = "1" - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Set the Thermal Control Circuit (TCC) activation value to 95C # even though FSP integration guide says to set it to 100C for SKL-U # (offset at 0), because when the TCC activates at 100C, the CPU @@ -170,6 +168,8 @@ device ref pcie_rp11 on end device ref pcie_rp12 on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 5565064..228676b 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -17,9 +17,6 @@ # Disable DPTF register "dptf_enable" = "0" - # Enable SERIRQ continuous - register "serirq_mode" = "SERIRQ_CONTINUOUS" - register "tcc_offset" = "5" # TCC of 95C # FSP Configuration @@ -198,6 +195,8 @@ "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x00fc0201" register "gen2_dec" = "0x007c0a01" register "gen3_dec" = "0x000c03e1" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 7892c7e..ca18f7a 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -47,9 +47,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - # EC/KBC requires continuous mode - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | @@ -153,6 +150,9 @@ device ref pcie_rp5 on end device ref pcie_rp9 on end device ref lpc_espi on + # EC/KBC requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f register "gen1_dec" = "0x00000381" chip drivers/pc80/tpm diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 438d323..b8ebb1b 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -28,8 +28,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | @@ -172,6 +170,8 @@ device ref pcie_rp5 on end device ref pcie_rp9 on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 29759fd..fbf896c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -4,9 +4,6 @@ register "SkipExtGfxScan" = "1" - # LPC - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch register "s0ix_enable" = true register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" @@ -33,6 +30,8 @@ }" end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + chip superio/common device pnp 2e.0 on end end diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 38578e0..e4658a7 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -18,9 +18,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART }" - # Serial IRQ - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Power register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s @@ -172,6 +169,8 @@ register "PcieRpLtrEnable[8]" = "1" end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" register "gen3_dec" = "0x00040069" -- To view, visit https://review.coreboot.org/c/coreboot/+/83188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144 Gerrit-Change-Number: 83188 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: skl mainboards/dt: Move SATA related settings into SATA device scope
by Felix Singer (Code Review) 26 Jun '24

26 Jun '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83179?usp=email ) Change subject: skl mainboards/dt: Move SATA related settings into SATA device scope ...................................................................... skl mainboards/dt: Move SATA related settings into SATA device scope Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> Reviewed-by: Marvin Evers <marvin.n.evers(a)gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 12 files changed, 108 insertions(+), 94 deletions(-) Approvals: Eric Lai: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve Jonathon Hall: Looks good to me, but someone else must approve build bot (Jenkins): Verified Marvin Evers: Looks good to me, but someone else must approve Erik van den Bogaert: Looks good to me, but someone else must approve diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 7a77e64..1f2fa40 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -30,15 +30,6 @@ register "dptf_enable" = "0" # FSP Configuration - register "SataSalpSupport" = "1" - - # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsDevSlp[2]" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" @@ -106,7 +97,21 @@ end device ref thermal on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + + # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + end device ref pcie_rp3 on end device ref pcie_rp4 on end device ref pcie_rp9 on end diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 854b887..c41a26f 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -32,11 +32,6 @@ register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - }" - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s register "PmConfigSlpS3MinAssert" = "2" @@ -209,7 +204,10 @@ device ref south_xdci on end device ref thermal on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + end device ref pcie_rp3 on end # x1 baseboard WWAN device ref pcie_rp6 on end # x1 baseboard i210 device ref pcie_rp9 on end # x4 FPGA diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 7d11653..9458c81 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -59,9 +59,6 @@ register "s0ix_enable" = true # FSP Configuration - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[1]" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SkipExtGfxScan" = "1" @@ -359,7 +356,13 @@ device ref i2c0 on end device ref i2c2 on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + }" + register "SataPortsDevSlp[1]" = "1" + end device ref uart2 on end device ref i2c5 on end device ref pcie_rp1 on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index f2e569d..49edccb 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -47,17 +47,6 @@ register "SsicPortEnable" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -112,7 +101,19 @@ device ref sa_thermal off end device ref i2c2 off end device ref i2c3 off end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref i2c4 off end device ref emmc off end device ref sdxc off end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 87bf0d8..99963bf 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -1,11 +1,5 @@ chip soc/intel/skylake - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - }" - # Enable deep Sx states register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" @@ -155,7 +149,13 @@ end device ref i2c2 off end device ref i2c3 off end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + end device ref pcie_rp3 on end device ref pcie_rp4 on end device ref pcie_rp5 on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 8e70c1e..5516fee 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -98,18 +98,6 @@ register "SsicPortEnable" = "1" # Enable SSIC for WWAN - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }" - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -164,7 +152,19 @@ end device ref i2c2 off end device ref i2c3 off end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref i2c4 off end device ref pcie_rp1 off end device ref pcie_rp3 on end diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 067cb59..73df651 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -130,17 +130,6 @@ # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -205,7 +194,19 @@ device ref i2c2 on end device ref i2c3 on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref uart2 on end device ref i2c5 on end device ref i2c4 on end diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb index 6657fa9..b6b3574 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -8,8 +8,6 @@ register "PcieRpEnable[ 3]" = "1" register "PcieRpEnable[11]" = "1" - register "SataPortsEnable[3]" = "1" - device domain 0 on device ref south_xhci on register "usb2_ports" = "{ @@ -26,6 +24,9 @@ [3] = USB3_PORT_DEFAULT(OC1), }" end + device ref sata on + register "SataPortsEnable[3]" = "1" + end device ref pcie_rp1 on end device ref pcie_rp2 on end device ref pcie_rp3 on end diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index f173e1e..02c3538 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -29,12 +29,6 @@ register "dptf_enable" = "0" # FSP Configuration - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - }" - register "SataSpeedLimit" = "2" register "DspEnable" = "1" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" @@ -154,7 +148,14 @@ device ref south_xdci on end device ref thermal on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + register "SataSpeedLimit" = "2" + end device ref pcie_rp3 on end device ref pcie_rp5 on smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 0b5d0cd..5565064 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -101,10 +101,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - # Enable SATA ports 1,2 - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - # Enable Root ports. 1-6 for LAN and Root Port 9 register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" @@ -183,7 +179,12 @@ }" end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + }" + end device ref pcie_rp1 on end device ref pcie_rp2 on end device ref pcie_rp3 on end diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 5b222fc..7892c7e 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -38,8 +38,6 @@ register "dptf_enable" = "0" # FSP Configuration - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[2]" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" @@ -146,7 +144,12 @@ device ref south_xhci on end device ref south_xdci on end device ref thermal on end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [2] = 1, + }" + end device ref pcie_rp5 on end device ref pcie_rp9 on end device ref lpc_espi on diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 1a8be1d..29759fd 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -3,18 +3,6 @@ # FSP Configuration register "SkipExtGfxScan" = "1" - # SATA configuration - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }" # LPC register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -31,7 +19,19 @@ device ref south_xhci on end device ref thermal on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref lpc_espi on chip superio/common device pnp 2e.0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/83179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Gerrit-Change-Number: 83179 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: skl mainboards/dt: Move genx_dec settings into LPC device scope
by Felix Singer (Code Review) 26 Jun '24

26 Jun '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83172?usp=email ) Change subject: skl mainboards/dt: Move genx_dec settings into LPC device scope ...................................................................... skl mainboards/dt: Move genx_dec settings into LPC device scope Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm> Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Marvin Evers <marvin.n.evers(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb 24 files changed, 104 insertions(+), 106 deletions(-) Approvals: Jonathon Hall: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, but someone else must approve Erik van den Bogaert: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved Marvin Evers: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 51cb89a..7a77e64 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -26,9 +26,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x000c0681" - register "gen2_dec" = "0x000c1641" - # Disable DPTF register "dptf_enable" = "0" @@ -114,6 +111,9 @@ device ref pcie_rp4 on end device ref pcie_rp9 on end device ref lpc_espi on + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + chip ec/51nb/npce985la0dx device pnp 0c09.0 on end device pnp 4e.5 on end diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 609e181..854b887 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -18,11 +18,6 @@ register "lpc_iod" = "0x0070" register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66" - # CPLD host command ranges are in 0x280-0x2BF - # EC PNP registers are at 0x6e and 0x6f - register "gen1_dec" = "0x003c0281" - register "gen3_dec" = "0x0004006d" - # LPC serial IRQ register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -221,6 +216,11 @@ device ref uart0 on end device ref emmc on end device ref lpc_espi on + # CPLD host command ranges are in 0x280-0x2BF + # EC PNP registers are at 0x6e and 0x6f + register "gen1_dec" = "0x003c0281" + register "gen3_dec" = "0x0004006d" + chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index e6a4178..38d0742 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -29,12 +29,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # FSP Configuration register "DspEnable" = "1" register "IoBufferOwnership" = "3" @@ -379,6 +373,12 @@ end device ref emmc on end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index a6ec6b6..7d11653 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -52,12 +52,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # Enable DPTF register "dptf_enable" = "1" @@ -407,6 +401,12 @@ end device ref sdxc on end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 864d73e5..88b7fbc 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -27,10 +27,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # Enable DPTF register "dptf_enable" = "1" @@ -97,6 +93,10 @@ device ref uart0 on end device ref emmc on end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 8b821f6..85a1e23a 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -27,12 +27,6 @@ register "gpe0_dw1" = "GPP_B" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # Enable DPTF register "dptf_enable" = "1" @@ -363,6 +357,12 @@ device ref sdio off end device ref sdxc off end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 8fbed5a..c44b380 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -18,12 +18,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # Enable DPTF register "dptf_enable" = "1" @@ -372,6 +366,12 @@ device ref sdio off end device ref sdxc on end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index c851c37..43c1b4b 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -27,12 +27,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # Enable DPTF register "dptf_enable" = "1" @@ -463,6 +457,12 @@ device ref sdio off end device ref sdxc off end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 122fb15..5d31208 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -27,12 +27,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # Enable DPTF register "dptf_enable" = "1" @@ -410,6 +404,12 @@ device ref sdio off end device ref sdxc on end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 140f5f8..9853f49 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -20,12 +20,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # Enable DPTF register "dptf_enable" = "1" @@ -401,6 +395,12 @@ device ref sdio off end device ref sdxc off end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 823df7c..fa57537 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -27,12 +27,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # Enable DPTF register "dptf_enable" = "1" @@ -376,6 +370,12 @@ device ref sdio off end device ref sdxc on end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index e877260..d7dea15 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -27,12 +27,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # Enable DPTF register "dptf_enable" = "1" @@ -355,6 +349,12 @@ device ref sdio off end device ref sdxc on end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index b57deff..be5ba44 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -13,9 +13,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - # Enable DPTF register "dptf_enable" = "1" @@ -127,6 +124,10 @@ device ref emmc on end device ref sdxc on end device ref smbus on end + device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + end device ref fast_spi on end end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 81557eb..0af8282 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -3,9 +3,6 @@ # GPE configuration register "gpe0_dw0" = "GPP_C" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen2_dec" = "0x000c0201" - # FSP Configuration register "DspEnable" = "1" @@ -123,6 +120,9 @@ device ref pcie_rp9 on end # x1 WLAN device ref pcie_rp10 on end # x1 WIGIG device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen2_dec" = "0x000c0201" + chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 9e8c814..87bf0d8 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -10,9 +10,6 @@ register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen2_dec" = "0x000c0201" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -164,6 +161,9 @@ device ref pcie_rp5 on end device ref pcie_rp6 on end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen2_dec" = "0x000c0201" + chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 45f7103..6e08059 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -13,10 +13,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # Enable DPTF register "dptf_enable" = "1" @@ -235,6 +231,10 @@ device ref emmc on end device ref sdxc on end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index d6bc990..f173e1e 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -25,10 +25,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f - register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef - register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff - # Disable DPTF register "dptf_enable" = "0" @@ -173,6 +169,9 @@ device ref pcie_rp11 on end device ref pcie_rp12 on end device ref lpc_espi on + register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f + register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef + register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 6148196..0b5d0cd 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -12,11 +12,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x00fc0201" - register "gen2_dec" = "0x007c0a01" - register "gen3_dec" = "0x000c03e1" - register "gen4_dec" = "0x001c02e1" - register "eist_enable" = "1" # Disable DPTF @@ -202,6 +197,10 @@ "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" end device ref lpc_espi on + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" chip superio/ite/it8772f register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_RESISTOR" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 03d48fa..5b222fc 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -34,9 +34,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" - # Disable DPTF register "dptf_enable" = "0" @@ -153,6 +150,8 @@ device ref pcie_rp5 on end device ref pcie_rp9 on end device ref lpc_espi on + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index da44d22..438d323 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -15,9 +15,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x000c0681" - register "gen2_dec" = "0x000c1641" - # Disable DPTF register "dptf_enable" = "0" @@ -175,6 +172,9 @@ device ref pcie_rp5 on end device ref pcie_rp9 on end device ref lpc_espi on + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + chip superio/ite/it8528e device pnp 6e.1 off end device pnp 6e.2 off end diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb index 4063bed..8a28ca1 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -8,9 +8,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x007c0a01" # Super IO SWC - register "gen2_dec" = "0x000c0ca1" # IPMI KCS - # Additional FSP Configuration # This board has an IGD with no output. register "PrimaryDisplay" = "Display_Auto" @@ -83,6 +80,9 @@ smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref lpc_espi on + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + chip drivers/ipmi # On cold boot it takes a while for the BMC to start the IPMI service register "wait_for_bmc" = "1" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 035811f..97f995d 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -8,9 +8,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x007c0a01" # Super IO SWC - register "gen2_dec" = "0x000c0ca1" # IPMI KCS - # FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1" @@ -67,6 +64,9 @@ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end device ref lpc_espi on + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + chip drivers/ipmi use pch_gpio as gpio_dev register "post_complete_gpio" = "GPP_B20" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 1b553d1..7993383 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -8,9 +8,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x007c0a01" # Super IO SWC - register "gen2_dec" = "0x000c0ca1" # IPMI KCS - device domain 0 on subsystemid 0x15d9 0x0896 inherit device ref south_xhci on @@ -84,6 +81,9 @@ end end device ref lpc_espi on + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + chip drivers/ipmi use pch_gpio as gpio_dev register "bmc_jumper_gpio" = "GPP_D22" # JPB1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb index 17ba31b..1d0dc7f 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb @@ -8,9 +8,6 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x007c0a01" # Super IO SWC - register "gen2_dec" = "0x000c0ca1" # IPMI KCS - # Additional FSP Configuration # This board has an IGD with no output. register "PrimaryDisplay" = "Display_Auto" @@ -71,6 +68,9 @@ end end device ref lpc_espi on + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + chip drivers/ipmi # On cold boot it takes a while for the BMC to start the IPMI service register "wait_for_bmc" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/83172?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832 Gerrit-Change-Number: 83172 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XL] Change in coreboot[main]: skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
by Felix Singer (Code Review) 26 Jun '24

26 Jun '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83171?usp=email ) Change subject: skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope ...................................................................... skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Marvin Evers <marvin.n.evers(a)gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/fizz/variants/karma/overridetree.cb M src/mainboard/google/glados/variants/asuka/overridetree.cb M src/mainboard/google/glados/variants/caroline/overridetree.cb M src/mainboard/google/glados/variants/cave/overridetree.cb M src/mainboard/google/glados/variants/chell/overridetree.cb M src/mainboard/google/glados/variants/glados/overridetree.cb M src/mainboard/google/glados/variants/lars/overridetree.cb M src/mainboard/google/glados/variants/sentry/overridetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb M src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb 35 files changed, 672 insertions(+), 564 deletions(-) Approvals: Jonathon Hall: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved Erik van den Bogaert: Looks good to me, but someone else must approve Marvin Evers: Looks good to me, but someone else must approve build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, but someone else must approve diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 17a5f75..51cb89a 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -75,18 +75,6 @@ register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" - register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) - register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) - register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # FPR - register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # SD - register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # INT - register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Webcam - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # mPCIe / WiFi Port - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # mSATA / WWAN Port - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) # PL1 override 25W # PL2 override 44W @@ -101,7 +89,24 @@ device domain 0 on device ref igpu on end device ref sa_thermal on end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC1), // Type-A Port (left) + [1] = USB2_PORT_MID(OC1), // Type-A Port (left) + [2] = USB2_PORT_FLEX(OC_SKIP), // FPR + [3] = USB2_PORT_FLEX(OC_SKIP), // SD + [4] = USB2_PORT_FLEX(OC_SKIP), // INT + [5] = USB2_PORT_MID(OC1), // Type-A Port (right) + [6] = USB2_PORT_FLEX(OC_SKIP), // Webcam + [7] = USB2_PORT_MID(OC_SKIP), // mPCIe / WiFi Port + [8] = USB2_PORT_MID(OC_SKIP), // mSATA / WWAN Port + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC1), // Type-A Port (left) + [1] = USB3_PORT_DEFAULT(OC1), // Type-A Port (left) + }" + end device ref thermal on end device ref heci1 on end device ref sata on end diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 4bc61dd..609e181 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -174,21 +174,6 @@ # Disable Aspm register "pcie_rp_aspm[8]" = "AspmDisabled" - register "usb2_ports" = "{ - [0] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 2 */ - [1] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 1 */ - [2] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 2 */ - [3] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 1 */ - [4] = USB2_PORT_SHORT(OC_SKIP), /* M2 Port */ - [6] = USB2_PORT_SHORT(OC_SKIP), /* Audio board */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 2 */ - [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 1 */ - [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 2 */ - [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 1 */ - }" # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ @@ -209,7 +194,23 @@ device ref igpu on end device ref sa_thermal on end device ref gmm on end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 2 */ + [1] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 1 */ + [2] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 2 */ + [3] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 1 */ + [4] = USB2_PORT_SHORT(OC_SKIP), /* M2 Port */ + [6] = USB2_PORT_SHORT(OC_SKIP), /* Audio board */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 2 */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 1 */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 2 */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 1 */ + }" + end device ref south_xdci on end device ref thermal on end device ref heci1 on end diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index a2b4311..e6a4178 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -141,15 +141,6 @@ #RP 5 uses CLK SRC 4 register "PcieRpClkSrcNumber[4]" = "4" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # H1 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -229,6 +220,18 @@ device ref igpu on end device ref sa_thermal on end device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC0), // Type-C Port 1 + [1] = USB2_PORT_FLEX(OC_SKIP), // Camera + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [4] = USB2_PORT_LONG(OC1), // Type-C Port 2 + [6] = USB2_PORT_MID(OC_SKIP), // H1 + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2 + }" chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index d64a9f9..a6ec6b6 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -233,22 +233,6 @@ # RP 12 uses CLK SRC 2 register "PcieRpClkSrcNumber[11]" = "2" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C - register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front - register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front - register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear - register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug @@ -306,6 +290,25 @@ device ref igpu on end device ref sa_thermal on end device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC0), // Type-C + [1] = USB2_PORT_MID(OC3), // Type-A Rear + [2] = USB2_PORT_MID(OC2), // Type-A Front + [3] = USB2_PORT_MID(OC2), // Type-A Front + [4] = USB2_PORT_MID(OC1), // Type-A Rear + [5] = USB2_PORT_MID(OC1), // Type-A Rear + [6] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [7] = USB2_PORT_MID(OC_SKIP), // Type-A 2.0 / Debug + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C + [1] = USB3_PORT_DEFAULT(OC3), // Type-A Rear + [2] = USB3_PORT_DEFAULT(OC2), // Type-A Front + [3] = USB3_PORT_DEFAULT(OC2), // Type-A Front + [4] = USB3_PORT_DEFAULT(OC1), // Type-A Rear + [5] = USB3_PORT_DEFAULT(OC1), // Type-A Rear + }" chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 989b2406..3da4f0e 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -42,20 +42,6 @@ register "PcieRpEnable[10]" = "0" register "PcieRpEnable[11]" = "0" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # HDMI - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Rear - register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Rear - register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-A Rear - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # HDMI Audio - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # TPU register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # None @@ -78,6 +64,23 @@ device domain 0 on device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC_SKIP), // Type-C + [1] = USB2_PORT_MID(OC_SKIP), // HDMI + [2] = USB2_PORT_MID(OC2), // Type-A Rear + [3] = USB2_PORT_MID(OC2), // Type-A Rear + [4] = USB2_PORT_MID(OC3), // Type-A Rear + [5] = USB2_PORT_MID(OC_SKIP), // HDMI Audio + [6] = USB2_PORT_MID(OC_SKIP), // Bluetooth + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C + [1] = USB3_PORT_DEFAULT(OC_SKIP), // HDMI + [2] = USB3_PORT_DEFAULT(OC2), // Type-A Rear + [3] = USB3_PORT_DEFAULT(OC2), // Type-A Rear + [4] = USB3_PORT_DEFAULT(OC3), // Type-A Rear + }" chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb index d1dc46f..25b39f4 100644 --- a/src/mainboard/google/fizz/variants/karma/overridetree.cb +++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb @@ -1,28 +1,32 @@ chip soc/intel/skylake - # Mapping of USB port # to device - #+----------------+-------+-----------------------------------+ - #| Device | Port# | Rev | - #+----------------+-------+-----------------------------------+ - #| USB A Side | 3 | 2/3 | - #| SD Card | 4 | | - #| Camera | 8 | | - #| Touchsreen | 10 | | - #+----------------+-------+-----------------------------------+ - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Side - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Touchscreen - - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Side - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader - register "power_limits_config" = "{ .psys_pmax = 151, }" device domain 0 on device ref south_xhci on + # Mapping of USB port # to device + #+----------------+-------+-----------------------------------+ + #| Device | Port# | Rev | + #+----------------+-------+-----------------------------------+ + #| USB A Side | 3 | 2/3 | + #| SD Card | 4 | | + #| Camera | 8 | | + #| Touchsreen | 10 | | + #+----------------+-------+-----------------------------------+ + register "usb2_ports" = "{ + [2] = USB2_PORT_MID(OC2), // Type-A Side + [3] = USB2_PORT_MID(OC_SKIP), // Card reader + [7] = USB2_PORT_MID(OC_SKIP), // Camera + [9] = USB2_PORT_MID(OC_SKIP), // Touchscreen + }" + + register "usb3_ports" = "{ + [2] = USB3_PORT_DEFAULT(OC2), // Type-A Side + [3] = USB3_PORT_DEFAULT(OC_SKIP), // Card reader + }" + chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi diff --git a/src/mainboard/google/glados/variants/asuka/overridetree.cb b/src/mainboard/google/glados/variants/asuka/overridetree.cb index 61220ee..85b0155 100644 --- a/src/mainboard/google/glados/variants/asuka/overridetree.cb +++ b/src/mainboard/google/glados/variants/asuka/overridetree.cb @@ -1,19 +1,24 @@ chip soc/intel/skylake - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # Card Reader - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (board) - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # PIC MCU - register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (board) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) - device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC0), // Type-C Port 1 + [1] = USB2_PORT_MID(OC2), // Card Reader + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [4] = USB2_PORT_MID(OC2), // Type-A Port (board) + [6] = USB2_PORT_FLEX(OC_SKIP), // Camera + [7] = USB2_PORT_MID(OC_SKIP), // PIC MCU + [8] = USB2_PORT_LONG(OC3), // Type-A Port (board) + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC_SKIP), // Card Reader + [2] = USB3_PORT_DEFAULT(OC2), // Type-A Port (board) + [3] = USB3_PORT_DEFAULT(OC3), // Type-A Port (board) + }" + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" diff --git a/src/mainboard/google/glados/variants/caroline/overridetree.cb b/src/mainboard/google/glados/variants/caroline/overridetree.cb index 6ea4845..fd6ded4 100644 --- a/src/mainboard/google/glados/variants/caroline/overridetree.cb +++ b/src/mainboard/google/glados/variants/caroline/overridetree.cb @@ -9,14 +9,6 @@ register "SlowSlewRateForGt" = "3" # Fast/16 register "SlowSlewRateForSa" = "0" # Fast/2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port (main) - register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (sub) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (main) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (sub) - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, // touchpad [PchSerialIoIndexI2C1] = PchSerialIoPci, // touchscreen @@ -38,6 +30,19 @@ register "tcc_offset" = "10" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), // Type-C Port (main) + [1] = USB2_PORT_MAX(OC_SKIP), // Type-C Port (sub) + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [6] = USB2_PORT_FLEX(OC_SKIP), // Camera + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port (main) + [1] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port (sub) + }" + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""ATML0001"" diff --git a/src/mainboard/google/glados/variants/cave/overridetree.cb b/src/mainboard/google/glados/variants/cave/overridetree.cb index 7d78d6b..0aeb317 100644 --- a/src/mainboard/google/glados/variants/cave/overridetree.cb +++ b/src/mainboard/google/glados/variants/cave/overridetree.cb @@ -3,14 +3,6 @@ register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port (board) - register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (flex) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (board) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (flex) - # PL2 override 15W register "power_limits_config" = "{ .tdp_pl2_override = 15, @@ -26,6 +18,19 @@ register "sdcard_cd_gpio" = "GPP_A7" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC_SKIP), // Type-C Port (board) + [1] = USB2_PORT_MAX(OC_SKIP), // Type-C Port (flex) + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [6] = USB2_PORT_FLEX(OC_SKIP), // Camera + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port (board) + [1] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port (flex) + }" + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" diff --git a/src/mainboard/google/glados/variants/chell/overridetree.cb b/src/mainboard/google/glados/variants/chell/overridetree.cb index 9e4b7f0..8ab7c35 100644 --- a/src/mainboard/google/glados/variants/chell/overridetree.cb +++ b/src/mainboard/google/glados/variants/chell/overridetree.cb @@ -3,18 +3,6 @@ register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms - register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-C Port 2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # SD - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD - # PL2 override 15W register "power_limits_config" = "{ .tdp_pl2_override = 15, @@ -27,6 +15,23 @@ register "tcc_offset" = "10" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC2), // Type-C Port 1 + [1] = USB2_PORT_LONG(OC3), // Type-C Port 2 + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [4] = USB2_PORT_MID(OC0), // Type-A Port + [6] = USB2_PORT_FLEX(OC_SKIP), // Camera + [8] = USB2_PORT_MID(OC_SKIP), // SD + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC2), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC3), // Type-C Port 2 + [2] = USB3_PORT_DEFAULT(OC0), // Type-A Port + [3] = USB3_PORT_DEFAULT(OC_SKIP), // SD + }" + end device ref i2c1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/glados/variants/glados/overridetree.cb b/src/mainboard/google/glados/variants/glados/overridetree.cb index 3bd4e3a..b2d8fc0 100644 --- a/src/mainboard/google/glados/variants/glados/overridetree.cb +++ b/src/mainboard/google/glados/variants/glados/overridetree.cb @@ -3,18 +3,6 @@ register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port (board) - register "usb2_ports[1]" = "USB2_PORT_MAX(OC3)" # Type-C Port (flex) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port 1 - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC1)" # Type-A Port 2 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port (board) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port (flex) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 2 - # PL2 override 15W register "power_limits_config" = "{ .tdp_pl2_override = 15, @@ -27,6 +15,23 @@ register "tcc_offset" = "10" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC2), // Type-C Port (board) + [1] = USB2_PORT_MAX(OC3), // Type-C Port (flex) + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [4] = USB2_PORT_MID(OC0), // Type-A Port 1 + [6] = USB2_PORT_FLEX(OC_SKIP), // Camera + [8] = USB2_PORT_MID(OC1), // Type-A Port 2 + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC2), // Type-C Port (board) + [1] = USB3_PORT_DEFAULT(OC3), // Type-C Port (flex) + [2] = USB3_PORT_DEFAULT(OC0), // Type-A Port 1 + [3] = USB3_PORT_DEFAULT(OC1), // Type-A Port 2 + }" + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" diff --git a/src/mainboard/google/glados/variants/lars/overridetree.cb b/src/mainboard/google/glados/variants/lars/overridetree.cb index 2616044..1165520 100644 --- a/src/mainboard/google/glados/variants/lars/overridetree.cb +++ b/src/mainboard/google/glados/variants/lars/overridetree.cb @@ -1,18 +1,23 @@ chip soc/intel/skylake - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card) - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # SD - register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) - device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC0), // Type-C Port 1 + [1] = USB2_PORT_FLEX(OC_SKIP), // Camera + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [4] = USB2_PORT_MID(OC2), // Type-A Port (card) + [5] = USB2_PORT_MID(OC_SKIP), // SD + [8] = USB2_PORT_LONG(OC3), // Type-A Port (board) + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC_SKIP), // SD + [2] = USB3_PORT_DEFAULT(OC2), // Type-A Port (card) + [3] = USB3_PORT_DEFAULT(OC3), // Type-A Port (board) + }" + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" diff --git a/src/mainboard/google/glados/variants/sentry/overridetree.cb b/src/mainboard/google/glados/variants/sentry/overridetree.cb index e052502..f59108c 100644 --- a/src/mainboard/google/glados/variants/sentry/overridetree.cb +++ b/src/mainboard/google/glados/variants/sentry/overridetree.cb @@ -1,17 +1,5 @@ chip soc/intel/skylake - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card) - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) - # I2C0 is 3.3V register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" @@ -19,6 +7,23 @@ register "sdcard_cd_gpio" = "GPP_A7" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC0), // Type-C Port 1 + [1] = USB2_PORT_TYPE_C(OC1), // Type-C Port 2 + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [4] = USB2_PORT_MID(OC2), // Type-A Port (card) + [6] = USB2_PORT_FLEX(OC_SKIP), // Camera + [8] = USB2_PORT_LONG(OC3), // Type-A Port (board) + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2 + [2] = USB3_PORT_DEFAULT(OC2), // Type-A Port (card) + [3] = USB3_PORT_DEFAULT(OC3), // Type-A Port (board) + }" + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""RAYD0001"" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 181c77b..8b821f6 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -140,15 +140,6 @@ register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" - # USB 2.0 - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 - - # USB 3.0 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -231,6 +222,17 @@ device ref imgu on end device ref ish off end device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC0), // Type-C Port 1 + [2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth + [4] = USB2_PORT_LONG(OC1), // Type-C Port 2 + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2 + }" + chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 0317139..8fbed5a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -130,17 +130,6 @@ # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -251,7 +240,22 @@ device ref igpu on end device ref sa_thermal on end device ref imgu on end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC0), // Type-C Port 1 + [1] = USB2_PORT_MID(OC_SKIP), // Type-A Port + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [4] = USB2_PORT_LONG(OC1), // Type-C Port 2 + [6] = USB2_PORT_MID(OC_SKIP), // Type-A Port + [8] = USB2_PORT_MID(OC_SKIP), // Type-A Port + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2 + [2] = USB3_PORT_DEFAULT(OC_SKIP), // Type-A Port + }" + end device ref south_xdci on end device ref thermal on end device ref cio on end diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 2bb5e11..c851c37 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -167,19 +167,6 @@ register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 0 - register "usb2_ports[1]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WiFi - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Rear camera - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Front camera - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader - # Touchscreen register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" @@ -276,7 +263,24 @@ device ref igpu on end device ref sa_thermal on end device ref imgu off end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC0), // Type-C Port 0 + [1] = USB2_PORT_LONG(OC1), // Type-C Port 1 + [2] = USB2_PORT_MID(OC2), // Type-A Port + [3] = USB2_PORT_MID(OC_SKIP), // Card reader + [4] = USB2_PORT_MID(OC_SKIP), // WiFi + [5] = USB2_PORT_MID(OC_SKIP), // Rear camera + [6] = USB2_PORT_MID(OC_SKIP), // Front camera + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 0 + [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 1 + [2] = USB3_PORT_DEFAULT(OC2), // Type-A Port + [3] = USB3_PORT_DEFAULT(OC_SKIP), // Card reader + }" + end device ref south_xdci on end device ref thermal on end device ref cio off end diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 29233c9..122fb15 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -148,18 +148,6 @@ # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_SHORT(OC2)" # Type-A Port - register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_LONG(OC0)" # Type-C Port 2 - register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1 - register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # LTE module - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -282,7 +270,23 @@ device ref igpu on end device ref sa_thermal on end device ref imgu on end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC1), // Type-C Port 1 + [1] = USB2_PORT_SHORT(OC2), // Type-A Port + [2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth + [4] = USB2_PORT_LONG(OC0), // Type-C Port 2 + [6] = USB2_PORT_SHORT(OC_SKIP), // H1 + [8] = USB2_PORT_SHORT(OC_SKIP), // Camera + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC1), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC0), // Type-C Port 2 + [2] = USB3_PORT_DEFAULT(OC2), // Type-A Port + [3] = USB3_PORT_DEFAULT(OC_SKIP), // LTE module + }" + end device ref south_xdci on end device ref thermal on end device ref cio on end diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 1ef0b45..140f5f8 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -147,16 +147,6 @@ register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" - # USB 2.0 - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 - register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # pogo port - - # USB 3.0 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -247,6 +237,18 @@ device ref sa_thermal on end device ref imgu on end device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC0), // Type-C Port 1 + [2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth + [4] = USB2_PORT_LONG(OC1), // Type-C Port 2 + [6] = USB2_PORT_LONG(OC_SKIP), // pogo port + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2 + }" + chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 42528cf..823df7c 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -137,17 +137,6 @@ # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" - register "usb2_ports[0]" = "USB2_PORT_SHORT(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-A Port - register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 - register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1 - register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -233,6 +222,20 @@ device ref sa_thermal on end device ref imgu off end device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_SHORT(OC0), // Type-C Port 1 + [1] = USB2_PORT_LONG(OC3), // Type-A Port + [2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth + [4] = USB2_PORT_LONG(OC1), // Type-C Port 2 + [6] = USB2_PORT_SHORT(OC_SKIP), // H1 + [8] = USB2_PORT_SHORT(OC_SKIP), // Camera + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2 + [2] = USB3_PORT_DEFAULT(OC3), // Type-A Port + }" chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index fb8aad2..e877260 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -139,17 +139,6 @@ # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-C Port 2 - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -261,7 +250,22 @@ device ref igpu on end device ref sa_thermal on end device ref imgu on end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC0), // Type-C Port 1 + [1] = USB2_PORT_MID(OC_SKIP), // Type-A Port + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [4] = USB2_PORT_MAX(OC1), // Type-C Port 2 + [6] = USB2_PORT_MID(OC_SKIP), // Type-A Port + [8] = USB2_PORT_MID(OC_SKIP), // Type-A Port + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2 + [2] = USB3_PORT_DEFAULT(OC_SKIP), // Type-A Port + }" + end device ref south_xdci on end device ref thermal on end device ref cio on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index b580e76..f2e569d 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -46,35 +46,6 @@ # USB related register "SsicPortEnable" = "1" - register "usb2_ports" = "{ - [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ - [1] = USB2_PORT_MID(OC3), /* Touch Pad */ - [2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */ - [3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */ - [4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */ - [5] = USB2_PORT_MID(OC0), /* Front Panel */ - [6] = USB2_PORT_MID(OC0), /* Front Panel */ - [7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ - [8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ - [9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ - [10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ - [11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */ - [12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ - [13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC5), /* OTG */ - [1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */ - [2] = USB3_PORT_DEFAULT(OC3), /* Flex */ - [3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */ - [4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ - [5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ - [6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ - [7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ - [8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ - [9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ - }" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ @@ -107,6 +78,37 @@ }" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ + [1] = USB2_PORT_MID(OC3), /* Touch Pad */ + [2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */ + [3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */ + [4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */ + [5] = USB2_PORT_MID(OC0), /* Front Panel */ + [6] = USB2_PORT_MID(OC0), /* Front Panel */ + [7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ + [8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ + [9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ + [10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ + [11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */ + [12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ + [13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC5), /* OTG */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */ + [2] = USB3_PORT_DEFAULT(OC3), /* Flex */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */ + [4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ + [5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ + [6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ + [7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ + [8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ + [9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ + }" + end device ref sa_thermal off end device ref i2c2 off end device ref i2c3 off end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index b7c4395..81557eb 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -74,26 +74,6 @@ # RP10, uses CLK SRC 4 register "PcieRpClkSrcNumber[9]" = "4" - register "usb2_ports" = "{ - [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ - [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ - [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */ - [4] = USB2_PORT_MAX(OC_SKIP), /* Type-A Port */ - [5] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ - [6] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [7] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [9] = USB2_PORT_MAX(OC1), /* TYPE-A Port */ - [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */ - [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ - [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ - [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */ - }" register "SsicPortEnable" = "1" # Enable SSIC for WWAN @@ -113,6 +93,28 @@ }" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ + [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */ + [4] = USB2_PORT_MAX(OC_SKIP), /* Type-A Port */ + [5] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [6] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [7] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [9] = USB2_PORT_MAX(OC1), /* TYPE-A Port */ + [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */ + }" + end device ref imgu on end device ref cio on end device ref pcie_rp1 on end # x4 SLOT1 diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index ce4bf4b..9e8c814 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -113,28 +113,6 @@ # RP 9 uses CLK SRC 1# register "PcieRpClkSrcNumber[8]" = "1" - register "usb2_ports" = "{ - [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ - [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ - [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */ - [4] = USB2_PORT_MAX(OC1), /* Type-A Port */ - [5] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [6] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ - [7] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ - [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [9] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */ - [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ - [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ - [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */ - [4] = USB3_PORT_DEFAULT(OC2), /* TYPE-A Port */ - [5] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ - }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -154,6 +132,30 @@ register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ + [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */ + [4] = USB2_PORT_MAX(OC1), /* Type-A Port */ + [5] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [6] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [7] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [9] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */ + [4] = USB3_PORT_DEFAULT(OC2), /* TYPE-A Port */ + [5] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + }" + end device ref i2c2 off end device ref i2c3 off end device ref sata on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 2291c63..8e70c1e 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -95,35 +95,6 @@ register "PcieRpClkReqNumber[8]" = "6" register "PcieRpClkReqNumber[16]" = "7" - register "usb2_ports" = "{ - [0] = USB2_PORT_MAX(OC2), /* Type-C Port */ - [1] = USB2_PORT_MAX(OC5), /* Front panel */ - [2] = USB2_PORT_MAX(OC4), /* Back panel */ - [3] = USB2_PORT_MAX(OC4), /* Back panel */ - [4] = USB2_PORT_MAX(OC1), /* Back panel-1 */ - [5] = USB2_PORT_MAX(OC1), /* Back panel */ - [6] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ - [7] = USB2_PORT_MAX(OC_SKIP), /* Front panel */ - [8] = USB2_PORT_MAX(OC_SKIP), /* M.2 BT */ - [9] = USB2_PORT_MAX(OC2), /* Front panel */ - [10] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ - [11] = USB2_PORT_MAX(OC_SKIP), /* Back panel-1 */ - [12] = USB2_PORT_MAX(OC3), /* Back panel */ - [13] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C Port */ - [1] = USB3_PORT_DEFAULT(OC1), /* Back panel */ - [2] = USB3_PORT_DEFAULT(OC1), /* Back panel */ - [3] = USB3_PORT_DEFAULT(OC0), /* Back panel-2 */ - [4] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ - [5] = USB3_PORT_DEFAULT(OC_SKIP), /* Front Panel */ - [6] = USB3_PORT_DEFAULT(OC2), /* Front Panel */ - [7] = USB3_PORT_DEFAULT(OC2), /* Front Panel */ - [8] = USB3_PORT_DEFAULT(OC3), /* Back panel */ - [9] = USB3_PORT_DEFAULT(OC_SKIP), /* LAN */ - }" register "SsicPortEnable" = "1" # Enable SSIC for WWAN @@ -160,6 +131,37 @@ }" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MAX(OC2), /* Type-C Port */ + [1] = USB2_PORT_MAX(OC5), /* Front panel */ + [2] = USB2_PORT_MAX(OC4), /* Back panel */ + [3] = USB2_PORT_MAX(OC4), /* Back panel */ + [4] = USB2_PORT_MAX(OC1), /* Back panel-1 */ + [5] = USB2_PORT_MAX(OC1), /* Back panel */ + [6] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ + [7] = USB2_PORT_MAX(OC_SKIP), /* Front panel */ + [8] = USB2_PORT_MAX(OC_SKIP), /* M.2 BT */ + [9] = USB2_PORT_MAX(OC2), /* Front panel */ + [10] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ + [11] = USB2_PORT_MAX(OC_SKIP), /* Back panel-1 */ + [12] = USB2_PORT_MAX(OC3), /* Back panel */ + [13] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C Port */ + [1] = USB3_PORT_DEFAULT(OC1), /* Back panel */ + [2] = USB3_PORT_DEFAULT(OC1), /* Back panel */ + [3] = USB3_PORT_DEFAULT(OC0), /* Back panel-2 */ + [4] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ + [5] = USB3_PORT_DEFAULT(OC_SKIP), /* Front Panel */ + [6] = USB3_PORT_DEFAULT(OC2), /* Front Panel */ + [7] = USB3_PORT_DEFAULT(OC2), /* Front Panel */ + [8] = USB3_PORT_DEFAULT(OC3), /* Back panel */ + [9] = USB3_PORT_DEFAULT(OC_SKIP), /* LAN */ + }" + end device ref i2c2 off end device ref i2c3 off end device ref sata on end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index d09a4d1..45f7103 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -117,21 +117,6 @@ register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkReqNumber[4]" = "2" - register "usb2_ports" = "{ - [0] = USB2_PORT_TYPE_C(OC0), /* Type-C Port 1 */ - [1] = USB2_PORT_TYPE_C(OC1), /* Type-C Port 2 */ - [2] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ - [4] = USB2_PORT_MID(OC2), /* Type-A Port (card) */ - [6] = USB2_PORT_FLEX(OC_SKIP), /* Camera */ - [8] = USB2_PORT_LONG(OC3), /* Type-A Port (board) */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC0), /* Type-C Port 1 */ - [1] = USB3_PORT_DEFAULT(OC1), /* Type-C Port 2 */ - [2] = USB3_PORT_DEFAULT(OC2), /* Type-A Port (card) */ - [3] = USB3_PORT_DEFAULT(OC3), /* Type-A Port (board) */ - }" register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V @@ -164,7 +149,23 @@ device domain 0 on device ref igpu on end device ref sa_thermal on end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC0), /* Type-C Port 1 */ + [1] = USB2_PORT_TYPE_C(OC1), /* Type-C Port 2 */ + [2] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ + [4] = USB2_PORT_MID(OC2), /* Type-A Port (card) */ + [6] = USB2_PORT_FLEX(OC_SKIP), /* Camera */ + [8] = USB2_PORT_LONG(OC3), /* Type-A Port (board) */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), /* Type-C Port 1 */ + [1] = USB3_PORT_DEFAULT(OC1), /* Type-C Port 2 */ + [2] = USB3_PORT_DEFAULT(OC2), /* Type-A Port (card) */ + [3] = USB3_PORT_DEFAULT(OC3), /* Type-A Port (board) */ + }" + end device ref thermal on end device ref i2c0 on chip drivers/i2c/generic diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index d888de4..067cb59 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -125,35 +125,6 @@ # USB related register "SsicPortEnable" = "1" - register "usb2_ports" = "{ - [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ - [1] = USB2_PORT_MID(OC3), /* Touch Pad */ - [2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */ - [3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */ - [4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */ - [5] = USB2_PORT_MID(OC0), /* Front Panel */ - [6] = USB2_PORT_MID(OC0), /* Front Panel */ - [7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ - [8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ - [9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ - [10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ - [11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */ - [12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ - [13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC5), /* OTG */ - [1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */ - [2] = USB3_PORT_DEFAULT(OC3), /* Flex */ - [3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */ - [4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ - [5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ - [6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ - [7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ - [8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ - [9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ - }" register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V @@ -197,7 +168,37 @@ device domain 0 on device ref igpu on end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ + [1] = USB2_PORT_MID(OC3), /* Touch Pad */ + [2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */ + [3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */ + [4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */ + [5] = USB2_PORT_MID(OC0), /* Front Panel */ + [6] = USB2_PORT_MID(OC0), /* Front Panel */ + [7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ + [8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ + [9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ + [10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ + [11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */ + [12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ + [13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC5), /* OTG */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */ + [2] = USB3_PORT_DEFAULT(OC3), /* Flex */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */ + [4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ + [5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ + [6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ + [7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ + [8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ + [9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ + }" + end device ref thermal on end device ref i2c0 on end device ref i2c1 on end diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb index ecfcd6f..6657fa9 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -8,19 +8,24 @@ register "PcieRpEnable[ 3]" = "1" register "PcieRpEnable[11]" = "1" - register "usb2_ports[5]" = "USB2_PORT_LONG(OC2)" - register "usb2_ports[6]" = "USB2_PORT_LONG(OC3)" - register "usb2_ports[7]" = "USB2_PORT_LONG(OC3)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" - register "SataPortsEnable[3]" = "1" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [5] = USB2_PORT_LONG(OC2), + [6] = USB2_PORT_LONG(OC3), + [7] = USB2_PORT_LONG(OC3), + [8] = USB2_PORT_MID(OC4), + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), + [1] = USB3_PORT_DEFAULT(OC0), + [2] = USB3_PORT_DEFAULT(OC1), + [3] = USB3_PORT_DEFAULT(OC1), + }" + end device ref pcie_rp1 on end device ref pcie_rp2 on end device ref pcie_rp3 on end diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index dd2fc60..d6bc990 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -125,24 +125,6 @@ register "PcieRpClkSrcNumber[10]" = "3" register "PcieRpClkSrcNumber[11]" = "3" - register "usb2_ports" = "{ - [0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ - [1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ - [2] = USB2_PORT_MID(OC_SKIP), /* WiFi */ - [3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ - [4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ - [5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ - [6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ - [7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ - [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ - [2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ - [3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ - }" - # PL2 override 25W register "power_limits_config" = "{ .tdp_pl2_override = 25, @@ -154,7 +136,25 @@ device domain 0 on device ref igpu on end device ref sa_thermal on end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ + [1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ + [2] = USB2_PORT_MID(OC_SKIP), /* WiFi */ + [3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ + [4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ + [5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ + [6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ + [7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ + }" + end device ref south_xdci on end device ref thermal on end device ref heci1 on end diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index f57f978..6148196 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -152,23 +152,6 @@ # RP 9 shares CLKSRC5# with RP 6 register "PcieRpClkSrcNumber[8]" = "5" - - # USB 2.0 enable ports 1-8, disable ports 9-12 - register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port - register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot - - # USB 3.0 enable ports 1-4, disable ports 5-6 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, @@ -185,7 +168,25 @@ device domain 0 on device ref igpu on end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port + [1] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port + [2] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port + [3] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port + [4] = USB2_PORT_SHORT(OC_SKIP), // Type-A Port + [5] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port + [6] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port + [7] = USB2_PORT_SHORT(OC_SKIP), // mPCIe slot + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port + [1] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port + [2] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port + [3] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port + }" + end device ref heci1 on end device ref sata on end device ref pcie_rp1 on end diff --git a/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb index 18ce220..08cf745 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb @@ -1,17 +1,23 @@ chip soc/intel/skylake - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD + device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC_SKIP), // Type-C Port + [1] = USB2_PORT_MID(OC0), // Type-A Port (right) + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [3] = USB2_PORT_FLEX(OC_SKIP), // Camera + [5] = USB2_PORT_FLEX(OC2), // Type-A Port (left) + [6] = USB2_PORT_MID(OC_SKIP), // SD + }" - # OC1 should be for Type-C but it seems to not have been wired, according to - # the available schematics, even though it is labeled as USB_OC_TYPEC. - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - - device domain 0 on end + # OC1 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port + [1] = USB3_PORT_DEFAULT(OC0), // Type-A Port (right) + [2] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port + }" + end + end end diff --git a/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb index 343944e..fa76a78 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb @@ -5,23 +5,28 @@ # SRCCLKREQ2# for NVMe per schematic register "PcieRpClkReqNumber[8]" = "2" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) - register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) - register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) - register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD - - # OC0 should be for Type-C but it seems to not have been wired, according to - # the available schematics, even though it is labeled as USB_OC_TYPEC. - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC_SKIP), // Type-C Port + [1] = USB2_PORT_MID(OC1), // Type-A Port (right) + [2] = USB2_PORT_MID(OC1), // Type-A Port (right) + [3] = USB2_PORT_FLEX(OC2), // Type-A Port (left) + [4] = USB2_PORT_FLEX(OC2), // Type-A Port (left) + [5] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [6] = USB2_PORT_FLEX(OC_SKIP), // Camera + [7] = USB2_PORT_FLEX(OC_SKIP), // SD + }" + + # OC0 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port + [1] = USB3_PORT_DEFAULT(OC1), // Type-A Port (right) + [2] = USB3_PORT_DEFAULT(OC1), // Type-A Port (right) + [3] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port + }" + end device ref pcie_rp5 on end end end diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb index 98bfb04..4063bed 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -15,32 +15,33 @@ # This board has an IGD with no output. register "PrimaryDisplay" = "Display_Auto" - register "usb2_ports" = "{ - [0] = USB2_PORT_MID(OC0), /* USB 2 */ - [1] = USB2_PORT_MID(OC0), /* USB 3 */ - [2] = USB2_PORT_MID(OC1), /* USB 4 */ - [3] = USB2_PORT_MID(OC1), /* USB 5 */ - [4] = USB2_PORT_MID(OC2), /* USB 0 */ - [5] = USB2_PORT_MID(OC2), /* USB 1 */ - [8] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */ - [9] = USB2_PORT_MID(OC5), /* USB 8 (3.0) */ - [10] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */ - [11] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */ - [12] = USB2_PORT_MID(OC3), /* USB 10 (3.0) */ - [13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */ - [14] = USB2_PORT_MID(OC0), /* Unknown */ - [15] = USB2_PORT_MID(OC0), /* Unknown */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC5), /* USB 8 */ - [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */ - [2] = USB3_PORT_DEFAULT(OC4), /* USB 7 */ - [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */ - [4] = USB3_PORT_DEFAULT(OC3), /* USB 10 */ - }" - device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), /* USB 2 */ + [1] = USB2_PORT_MID(OC0), /* USB 3 */ + [2] = USB2_PORT_MID(OC1), /* USB 4 */ + [3] = USB2_PORT_MID(OC1), /* USB 5 */ + [4] = USB2_PORT_MID(OC2), /* USB 0 */ + [5] = USB2_PORT_MID(OC2), /* USB 1 */ + [8] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */ + [9] = USB2_PORT_MID(OC5), /* USB 8 (3.0) */ + [10] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */ + [11] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */ + [12] = USB2_PORT_MID(OC3), /* USB 10 (3.0) */ + [13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */ + [14] = USB2_PORT_MID(OC0), /* Unknown */ + [15] = USB2_PORT_MID(OC0), /* Unknown */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC5), /* USB 8 */ + [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */ + [2] = USB3_PORT_DEFAULT(OC4), /* USB 7 */ + [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */ + [4] = USB3_PORT_DEFAULT(OC3), /* USB 10 */ + }" + end device ref peg0 on # Slot JPCIE3 smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index b46b220..035811f 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -14,32 +14,33 @@ # FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1" - register "usb2_ports" = "{ - [0] = USB2_PORT_MID(OC0), /* USB 2 */ - [1] = USB2_PORT_MID(OC0), /* USB 3 */ - [2] = USB2_PORT_MID(OC1), /* USB 4 */ - [3] = USB2_PORT_MID(OC1), /* USB 5 */ - [4] = USB2_PORT_MID(OC2), /* USB 0 */ - [5] = USB2_PORT_MID(OC2), /* USB 1 */ - [8] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */ - [9] = USB2_PORT_MID(OC5), /* USB 8 (3.0) */ - [10] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */ - [11] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */ - [12] = USB2_PORT_MID(OC3), /* USB 10 (3.0) */ - [13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */ - [14] = USB2_PORT_MID(OC0), /* Unknown */ - [15] = USB2_PORT_MID(OC0), /* Unknown */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC5), /* USB 8 */ - [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */ - [2] = USB3_PORT_DEFAULT(OC4), /* USB 7 */ - [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */ - [4] = USB3_PORT_DEFAULT(OC3), /* USB 10 */ - }" - device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), /* USB 2 */ + [1] = USB2_PORT_MID(OC0), /* USB 3 */ + [2] = USB2_PORT_MID(OC1), /* USB 4 */ + [3] = USB2_PORT_MID(OC1), /* USB 5 */ + [4] = USB2_PORT_MID(OC2), /* USB 0 */ + [5] = USB2_PORT_MID(OC2), /* USB 1 */ + [8] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */ + [9] = USB2_PORT_MID(OC5), /* USB 8 (3.0) */ + [10] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */ + [11] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */ + [12] = USB2_PORT_MID(OC3), /* USB 10 (3.0) */ + [13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */ + [14] = USB2_PORT_MID(OC0), /* Unknown */ + [15] = USB2_PORT_MID(OC0), /* Unknown */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC5), /* USB 8 */ + [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */ + [2] = USB3_PORT_DEFAULT(OC4), /* USB 7 */ + [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */ + [4] = USB3_PORT_DEFAULT(OC3), /* USB 10 */ + }" + end device ref peg0 on end # unused device ref peg1 on # Slot JPCIE1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 29252fe..1b553d1 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -11,31 +11,32 @@ register "gen1_dec" = "0x007c0a01" # Super IO SWC register "gen2_dec" = "0x000c0ca1" # IPMI KCS - register "usb2_ports" = "{ - [0] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */ - [1] = USB2_PORT_MID(OC3), /* USB 8 (3.0) */ - [2] = USB2_PORT_MID(OC1), /* USB 3 */ - [3] = USB2_PORT_MID(OC1), /* USB 2 */ - [4] = USB2_PORT_MID(OC2), /* USB 1 */ - [5] = USB2_PORT_MID(OC2), /* USB 0 */ - [6] = USB2_PORT_MID(OC0), /* USB 5 */ - [7] = USB2_PORT_MID(OC0), /* USB 4 */ - [8] = USB2_PORT_MID(OC_SKIP), /* IPMI USB HUB */ - [9] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */ - [10] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */ - [11] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC4), /* USB 7 */ - [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */ - [2] = USB3_PORT_DEFAULT(OC5), /* USB 10 */ - [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */ - [4] = USB3_PORT_DEFAULT(OC3), /* USB 8 */ - }" - device domain 0 on subsystemid 0x15d9 0x0896 inherit + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */ + [1] = USB2_PORT_MID(OC3), /* USB 8 (3.0) */ + [2] = USB2_PORT_MID(OC1), /* USB 3 */ + [3] = USB2_PORT_MID(OC1), /* USB 2 */ + [4] = USB2_PORT_MID(OC2), /* USB 1 */ + [5] = USB2_PORT_MID(OC2), /* USB 0 */ + [6] = USB2_PORT_MID(OC0), /* USB 5 */ + [7] = USB2_PORT_MID(OC0), /* USB 4 */ + [8] = USB2_PORT_MID(OC_SKIP), /* IPMI USB HUB */ + [9] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */ + [10] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */ + [11] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC4), /* USB 7 */ + [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */ + [2] = USB3_PORT_DEFAULT(OC5), /* USB 10 */ + [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */ + [4] = USB3_PORT_DEFAULT(OC3), /* USB 8 */ + }" + end device ref peg0 on # Slot JPCIE6 smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb index 29babda..17ba31b 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb @@ -15,33 +15,34 @@ # This board has an IGD with no output. register "PrimaryDisplay" = "Display_Auto" - # NB: Overcurrent OCx values untested - register "usb2_ports" = "{ - [0] = USB2_PORT_MID(OC3), /* USB 6 (3.0) */ - [1] = USB2_PORT_MID(OC3), /* USB 7 (3.0) */ - [2] = USB2_PORT_MID(OC2), /* USB 0 */ - [3] = USB2_PORT_MID(OC2), /* USB 1 */ - [4] = USB2_PORT_MID(OC1), /* USB 4 */ - [5] = USB2_PORT_MID(OC1), /* USB 5 */ - [8] = USB2_PORT_MID(OC0), /* USB 2 */ - [9] = USB2_PORT_MID(OC0), /* USB 3 */ - [10] = USB2_PORT_MID(OC5), /* USB 9 (3.0) */ - [11] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */ - [12] = USB2_PORT_MID(OC4), /* USB 8 (3.0) */ - [13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */ - [14] = USB2_PORT_MID(OC0), /* Unknown */ - [15] = USB2_PORT_MID(OC0), /* Unknown */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC3), /* USB 6 */ - [1] = USB3_PORT_DEFAULT(OC3), /* USB 7 */ - [2] = USB3_PORT_DEFAULT(OC4), /* USB 8 */ - [3] = USB3_PORT_DEFAULT(OC5), /* USB 9 */ - [4] = USB3_PORT_DEFAULT(OC5), /* USB 10 */ - }" - device domain 0 on + device ref south_xhci on + # NB: Overcurrent OCx values untested + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC3), /* USB 6 (3.0) */ + [1] = USB2_PORT_MID(OC3), /* USB 7 (3.0) */ + [2] = USB2_PORT_MID(OC2), /* USB 0 */ + [3] = USB2_PORT_MID(OC2), /* USB 1 */ + [4] = USB2_PORT_MID(OC1), /* USB 4 */ + [5] = USB2_PORT_MID(OC1), /* USB 5 */ + [8] = USB2_PORT_MID(OC0), /* USB 2 */ + [9] = USB2_PORT_MID(OC0), /* USB 3 */ + [10] = USB2_PORT_MID(OC5), /* USB 9 (3.0) */ + [11] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */ + [12] = USB2_PORT_MID(OC4), /* USB 8 (3.0) */ + [13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */ + [14] = USB2_PORT_MID(OC0), /* Unknown */ + [15] = USB2_PORT_MID(OC0), /* Unknown */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC3), /* USB 6 */ + [1] = USB3_PORT_DEFAULT(OC3), /* USB 7 */ + [2] = USB3_PORT_DEFAULT(OC4), /* USB 8 */ + [3] = USB3_PORT_DEFAULT(OC5), /* USB 9 */ + [4] = USB3_PORT_DEFAULT(OC5), /* USB 10 */ + }" + end device ref peg0 on # Slot JSXB1B smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT1 PCI-E 3.0 X16" "SlotDataBusWidth16X" -- To view, visit https://review.coreboot.org/c/coreboot/+/83171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Gerrit-Change-Number: 83171 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt
by Shuo Liu (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/81374?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt ...................................................................... Patch Set 22: (1 comment) Patchset: PS22: May we move ahead on this one? -- To view, visit https://review.coreboot.org/c/coreboot/+/81374?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c Gerrit-Change-Number: 81374 Gerrit-PatchSet: 22 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 10:58:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel: Adapt crashlog IP to also support 64-bit
by Sowmya Aralguppe (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Nick Vaccaro, Paul Menzel, Pratikkumar V Prajapati, Subrata Banik, Tarun. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email ) Change subject: soc/intel: Adapt crashlog IP to also support 64-bit ...................................................................... Patch Set 22: (2 comments) Patchset: PS22: > It would be great if you could put fixes in a separate commit. […] The pointer typecast correction is part of 64-bit support File src/soc/intel/meteorlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/83106/comment/893614ea_650aaee1?us… : PS22, Line 355: if (!is_crashlog_data_valid(dw0)) > `cur_offset` changes inside the loop, so this reads a different register every iteration right where it checks for buffer size for non zero value . The crashlog record (header) is initialized to either 0 or 0xdeadbeef which is checked in the beginning Crashlog record initialization: Write 0x0 to crashlog record header - first 28 bytes of the crashlog record () Write 0xDEADBEEF to the rest of the crashlog header record region Same thing will hold good when crashlog is disabled/rearmed -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 22 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 10:38:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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