coreboot-gerrit June 2024

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[S] Change in coreboot[main]: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space
by Nico Huber (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Nico Huber has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82264?usp=email ) Change subject: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space ...................................................................... Patch Set 8: (4 comments) Patchset: PS8: Not sure if we have to put much effort into this? Is there actually a requirement for MTRR-based caching above for 4G? In any case, I wouldn't want FSP hooks here. File src/cpu/x86/mtrr/mtrr.c: https://review.coreboot.org/c/coreboot/+/82264/comment/c0b97b96_9b7c1f84?us… : PS3, Line 203: soc_update_physical_address_space > There seem to be no specification when it comes to MTRRs. […] Looks like ASSIGNED is actually set? There are two more pitfalls: size = 0 is ignored and SUBTRACTIVE resources as well. Two signs that the code isn't meant to consider windows. Subtractive windows shouldn't be. But we don't have those on Xeon-SP. I guess setting the size could work (something we wouldn't have to worry about if coreboot would handle the resources). File src/cpu/x86/mtrr/mtrr.c: https://review.coreboot.org/c/coreboot/+/82264/comment/2639a8dc_e6b32e7b?us… : PS8, Line 203: soc_fill_uc_holes_in_physical_address_space(addr_space); Putting MMIO high above the DRAM seems common. And I assume we'll see more of it. A general solution could look as follows: ``` max_dram = find_highest_dram_above_4g(); min_mmio = find_lowest_mmio_above_4g(); if (max_dram > min_mmio) that's odd, bail out; mmio_base = 1 << log2_64(min_mmio); /* align to best power of 2 */ while (mmio_base <= max_dram) mmio_base |= mmio_base >> 1; fill holes from mmio_base; ``` Well, that still assumes that there is a reasonably aligned barrier between DRAM and MMIO. But I hope the idea comes through. *OTOH* unless somebody knows a good reason for MTRR caching above 4G, we could do a much simpler best effort: ``` min_mmio = find_lowest_mmio_above_4g(); mmio_base = 1 << log2_64(min_mmio); ``` This would kill some of the caching for DRAM if MMIO isn't well enough above it. But do we care? Not sure if we optimize the upper end yet, do we? For the very end, it's just a matter of aligning up to a power of 2. File src/include/cpu/x86/mtrr.h: https://review.coreboot.org/c/coreboot/+/82264/comment/68799775_311bf54a?us… : PS8, Line 64: include < > alphabetical order. why? it wasn't before and one could as well argue that it looks better with the standard C headers above. but let's not argue, we probably won't need it. -- To view, visit https://review.coreboot.org/c/coreboot/+/82264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b4be85e79007fd1ccf5882de4dfeaeacd98a4db Gerrit-Change-Number: 82264 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 27 Jun 2024 21:12:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[XS] Change in coreboot[main]: mb/intel/tglrvp/dt: Remove superfluous USB2_PORT_EMPTY settings
by Felix Singer (Code Review) 27 Jun '24

27 Jun '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83246?usp=email ) Change subject: mb/intel/tglrvp/dt: Remove superfluous USB2_PORT_EMPTY settings ...................................................................... mb/intel/tglrvp/dt: Remove superfluous USB2_PORT_EMPTY settings Configuring USB2_PORT_EMPTY is equal to just not setting it. So remove it to clean up a bit. Change-Id: I6854f4a0d3e7b51b242549556a5838d4183d3473 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83246/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index ca2e08b..10dcd6c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -201,7 +201,6 @@ device ref south_xhci on register "usb2_ports" = "{ [0] = USB2_PORT_MID(OC0), // Type-C Port1 - [1] = USB2_PORT_EMPTY, // M.2 WWAN [2] = USB2_PORT_MID(OC3), // M.2 Bluetooth [3] = USB2_PORT_MID(OC0), // USB3/2 Type A port1 [4] = USB2_PORT_MID(OC0), // Type-C Port2 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index cfa8874..fafdbf9 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -205,14 +205,10 @@ device ref south_xhci on register "usb2_ports" = "{ [0] = USB2_PORT_MID(OC3), // Type-C Port1 - [1] = USB2_PORT_EMPTY, // M.2 WWAN [2] = USB2_PORT_MID(OC0), // M.2 Bluetooth, USB3/2 Type A Port1 [3] = USB2_PORT_MID(OC3), // USB3/2 Type A Port 1 [4] = USB2_PORT_MID(OC3), // Type-C Port2 [5] = USB2_PORT_MID(OC3), // Type-C Port3 / MECC - [6] = USB2_PORT_EMPTY, // Not used - [7] = USB2_PORT_EMPTY, // Not used - [8] = USB2_PORT_EMPTY, // Not used [9] = USB2_PORT_MID(OC3), // CNVi/BT }" -- To view, visit https://review.coreboot.org/c/coreboot/+/83246?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6854f4a0d3e7b51b242549556a5838d4183d3473 Gerrit-Change-Number: 83246 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[L] Change in coreboot[main]: tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope
by Felix Singer (Code Review) 27 Jun '24

27 Jun '24

Felix Singer has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83245?usp=email ) Change subject: tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/83245?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a Gerrit-Change-Number: 83245 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Thu, 27 Jun 2024 21:05:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space
by Jérémy Compostella (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Shuo Liu, Tim Chu. Jérémy Compostella has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82264?usp=email ) Change subject: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82264/comment/2a2bc3c8_8201d524?us… : PS8, Line 14: windows window File src/include/cpu/x86/mtrr.h: https://review.coreboot.org/c/coreboot/+/82264/comment/7135d064_1ab80d30?us… : PS8, Line 64: include < alphabetical order. -- To view, visit https://review.coreboot.org/c/coreboot/+/82264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b4be85e79007fd1ccf5882de4dfeaeacd98a4db Gerrit-Change-Number: 82264 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 27 Jun 2024 19:40:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/intel/tglrvp/dt: Make use of device alias names
by Felix Singer (Code Review) 27 Jun '24

27 Jun '24

Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83244?usp=email ) Change subject: mb/intel/tglrvp/dt: Make use of device alias names ...................................................................... mb/intel/tglrvp/dt: Make use of device alias names Also, remove superfluous comments from devices which repeat their name. Change-Id: I009330042b59c9e6e78aa6f3819546b771b26ff0 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 142 insertions(+), 145 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/83244/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009330042b59c9e6e78aa6f3819546b771b26ff0 Gerrit-Change-Number: 83244 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[L] Change in coreboot[main]: mb/intel/tglrvp/dt: Make use of device alias names
by Felix Singer (Code Review) 27 Jun '24

27 Jun '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83244?usp=email ) Change subject: mb/intel/tglrvp/dt: Make use of device alias names ...................................................................... mb/intel/tglrvp/dt: Make use of device alias names Change-Id: I009330042b59c9e6e78aa6f3819546b771b26ff0 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 142 insertions(+), 145 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/83244/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 6a7db5f..f03f677 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -162,10 +162,9 @@ }" device domain 0 on - #From EDS(575683) - device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y - device pci 02.0 on end # Graphics - device pci 04.0 on + device ref system_agent on end + device ref igpu on end + device ref dptf on # Default DPTF Policy for all tglrvp_up3 boards if not overridden chip drivers/intel/dptf register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" @@ -186,45 +185,44 @@ .granularity = 1000,}" device generic 0 on end end - end # DPTF 0x9A04:U22/0x9A14:U42 + end - device pci 05.0 on end # IPU 0x9A19 - device pci 06.0 on end # PEG60 0x9A09 - device pci 07.0 on end # TBT_PCIe0 0x9A23 - device pci 07.1 on end # TBT_PCIe1 0x9A25 - device pci 07.2 on end # TBT_PCIe2 0x9A27 - device pci 07.3 on end # TBT_PCIe3 0x9A29 - device pci 08.0 off end # GNA 0x9A11 - device pci 09.0 off end # NPK 0x9A33 - device pci 0a.0 off end # Crash-log SRAM 0x9A0D - device pci 0d.0 on end # USB xHCI 0x9A13 - device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 on end # TBT DMA1 0x9A1D - device pci 0e.0 off end # VMD 0x9A0B + device ref ipu on end + device ref peg on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref gna off end + device ref npk off end + device ref crashlog off end + device ref north_xhci on end + device ref north_xdci on end + device ref tbt_dma0 on end + device ref tbt_dma1 on end + device ref vmd off end - # From PCH EDS(576591) - device pci 10.6 off end # THC0 0xA0D0 - device pci 10.7 off end # THC1 0xA0D1 - device pci 12.0 on # SensorHUB 0xA0FC + device ref thc0 off end + device ref thc1 off end + device ref ish on chip drivers/intel/ish register "firmware_name" = ""tglrvp_ish.bin"" device generic 0 on end end end - device pci 12.6 off end # GSPI2 0x34FB - device pci 13.0 off end # GSPI3 0xA0FD - device pci 14.0 on end # USB3.1 xHCI 0xA0ED - device pci 14.1 on end # USB3.1 xDCI 0xA0EE - device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 on + device ref gspi2 off end + device ref gspi3 off end + device ref south_xhci on end + device ref south_xdci on end + device ref shared_ram on end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device generic 0 on end end - end # CNVi: WiFi 0xA0F0 - A0F3 + end - device pci 15.0 on # I2C0 0xA0E8 + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC1308"" register "name" = ""RTAM"" @@ -259,58 +257,58 @@ register "property_list[0].integer" = "1" device i2c 1a on end end - end # I2C0 - device pci 15.1 on end # I2C1 0xA0E9 - device pci 15.2 on end # I2C2 0xA0EA - device pci 15.3 on end # I2C3 0xA0EB - device pci 16.0 on end # HECI1 0xA0E0 - device pci 16.1 off end # HECI2 0xA0E1 - device pci 16.2 off end # CSME 0xA0E2 - device pci 16.3 off end # CSME 0xA0E3 - device pci 16.4 off end # HECI3 0xA0E4 - device pci 16.5 off end # HECI4 0xA0E5 - device pci 17.0 on end # SATA 0xA0D3 - device pci 19.0 off end # I2C4 0xA0C5 - device pci 19.1 on end # I2C5 0xA0C6 - device pci 19.2 on end # UART2 0xA0C7 - device pci 1c.0 off end # RP1 0xA0B8 - device pci 1c.1 off end # RP2 0xA0B9 - device pci 1c.2 on end # RP3 0xA0BA - device pci 1c.3 on + end + device ref i2c1 on end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref heci2 off end + device ref csme1 off end + device ref csme2 off end + device ref heci3 off end + device ref heci4 off end + device ref sata on end + device ref i2c4 off end + device ref i2c5 on end + device ref uart2 on end + device ref pcie_rp1 off end + device ref pcie_rp2 off end + device ref pcie_rp3 on end + device ref pcie_rp4 on chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" register "srcclk_pin" = "2" device generic 0 on end end - end # RP4 0xA0BB - device pci 1c.4 off end # RP5 0xA0BC - device pci 1c.5 off end # RP6 0xA0BD - device pci 1c.6 off end # RP7 0xA0BE - device pci 1c.7 off end # RP8 0xA0BF - device pci 1d.0 on end # RP9 0xA0B0 - device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 on end # RP11 0xA0B2 - device pci 1d.3 off end # RP12 0xA0B3 - device pci 1e.0 off end # UART0 0xA0A8 - device pci 1e.1 off end # UART1 0xA0A9 - device pci 1e.2 on end # GSPI0 0xA0AA - device pci 1e.3 on + end + device ref pcie_rp5 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 off end + device ref pcie_rp9 on end + device ref pcie_rp10 off end + device ref pcie_rp11 on end + device ref pcie_rp12 off end + device ref uart0 off end + device ref uart1 off end + device ref gspi0 on end + device ref gspi1 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)" device spi 0 on end end - end # GSPI1 0xA0AB - device pci 1f.0 on + end + device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] device pnp 0c09.0 on end end - end # eSPI 0xA080 - A09F - device pci 1f.1 on end # P2SB 0xA0A0 - device pci 1f.2 hidden # PMC 0xA0A1 + end + device ref p2sb on end + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -331,11 +329,11 @@ end end end - end # PMC - device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF - device pci 1f.4 on end # SMBus 0xA0A3 - device pci 1f.5 on end # SPI 0xA0A4 - device pci 1f.6 off end # GbE 0x15E1/0x15E2 - device pci 1f.7 off end # TH 0xA0A6 + end + device ref hda on end + device ref smbus on end + device ref fast_spi on end + device ref gbe off end + device ref tracehub off end end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 5960a3c..03e9c2d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -167,9 +167,9 @@ device domain 0 on #From EDS(575683) - device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y - device pci 02.0 on end # Graphics - device pci 04.0 on + device ref system_agent on end + device ref igpu on end + device ref dptf on # Default DPTF Policy for all tglrvp_up4 boards if not overridden chip drivers/intel/dptf register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" @@ -190,45 +190,44 @@ .granularity = 1000,}" device generic 0 on end end - end # DPTF 0x9A02:Y22/0x9A12:Y42 + end - device pci 05.0 on end # IPU 0x9A19 - device pci 06.0 on end # PEG60 0x9A09 - device pci 07.0 on end # TBT_PCIe0 0x9A23 - device pci 07.1 on end # TBT_PCIe1 0x9A25 - device pci 07.2 on end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 - device pci 08.0 off end # GNA 0x9A11 - device pci 09.0 off end # NPK 0x9A33 - device pci 0a.0 off end # Crash-log SRAM 0x9A0D - device pci 0d.0 on end # USB xHCI 0x9A13 - device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 on end # TBT DMA1 0x9A1D - device pci 0e.0 off end # VMD 0x9A0B + device ref ipu on end + device ref peg on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 off end + device ref gna off end + device ref npk off end + device ref crashlog off end + device ref north_xhci on end + device ref north_xdci on end + device ref tbt_dma0 on end + device ref tbt_dma1 on end + device ref vmd off end - # From PCH EDS(576591) - device pci 10.6 off end # THC0 0xA0D0 - device pci 10.7 off end # THC1 0xA0D1 - device pci 12.0 on # SensorHUB 0xA0FC + device ref thc0 off end + device ref thc1 off end + device ref ish on chip drivers/intel/ish register "firmware_name" = ""tglrvp_ish.bin"" device generic 0 on end end end - device pci 12.6 off end # GSPI2 0x34FB - device pci 13.0 off end # GSPI3 0xA0FD - device pci 14.0 on end # USB3.1 xHCI 0xA0ED - device pci 14.1 on end # USB3.1 xDCI 0xA0EE - device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 on + device ref gspi2 off end + device ref gspi3 off end + device ref south_xhci on end + device ref south_xdci on end + device ref shared_ram on end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device generic 0 on end end - end # CNVi: WiFi 0xA0F0 - A0F3 + end - device pci 15.0 on # I2C0 0xA0E8 + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC1308"" register "name" = ""RTAM"" @@ -263,58 +262,58 @@ register "property_list[0].integer" = "1" device i2c 1a on end end - end # I2C0 - device pci 15.1 on end # I2C1 0xA0E9 - device pci 15.2 on end # I2C2 0xA0EA - device pci 15.3 on end # I2C3 0xA0EB - device pci 16.0 on end # HECI1 0xA0E0 - device pci 16.1 off end # HECI2 0xA0E1 - device pci 16.2 off end # CSME 0xA0E2 - device pci 16.3 off end # CSME 0xA0E3 - device pci 16.4 off end # HECI3 0xA0E4 - device pci 16.5 off end # HECI4 0xA0E5 - device pci 17.0 on end # SATA 0xA0D3 - device pci 19.0 off end # I2C4 0xA0C5 - device pci 19.1 on end # I2C5 0xA0C6 - device pci 19.2 on end # UART2 0xA0C7 - device pci 1c.0 off end # RP1 0xA0B8 - device pci 1c.1 off end # RP2 0xA0B9 - device pci 1c.2 on end # RP3 0xA0BA - device pci 1c.3 on + end + device ref i2c1 on end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref heci2 off end + device ref csme1 off end + device ref csme2 off end + device ref heci3 off end + device ref heci4 off end + device ref sata on end + device ref i2c4 off end + device ref i2c5 on end + device ref uart2 on end + device ref pcie_rp1 off end + device ref pcie_rp2 off end + device ref pcie_rp3 on end + device ref pcie_rp4 on chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" register "srcclk_pin" = "2" device generic 0 on end end - end # RP4 0xA0BB - device pci 1c.4 off end # RP5 0xA0BC - device pci 1c.5 off end # RP6 0xA0BD - device pci 1c.6 off end # RP7 0xA0BE - device pci 1c.7 off end # RP8 0xA0BF - device pci 1d.0 on end # RP9 0xA0B0 - device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 on end # RP11 0xA0B2 - device pci 1d.3 off end # RP12 0xA0B3 - device pci 1e.0 off end # UART0 0xA0A8 - device pci 1e.1 off end # UART1 0xA0A9 - device pci 1e.2 on end # GSPI0 0xA0AA - device pci 1e.3 on + end + device ref pcie_rp5 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 off end + device ref pcie_rp9 on end + device ref pcie_rp10 off end + device ref pcie_rp11 on end + device ref pcie_rp12 off end + device ref uart0 off end + device ref uart1 off end + device ref gspi0 on end + device ref gspi1 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)" device spi 0 on end end - end # GSPI1 0xA0AB - device pci 1f.0 on + end + device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] device pnp 0c09.0 on end end - end # eSPI 0xA080 - A09F - device pci 1f.1 on end # P2SB 0xA0A0 - device pci 1f.2 hidden # PMC 0xA0A1 + end + device ref p2sb on end + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -335,11 +334,11 @@ end end end - end # PMC - device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF - device pci 1f.4 on end # SMBus 0xA0A3 - device pci 1f.5 on end # SPI 0xA0A4 - device pci 1f.6 off end # GbE 0x15E1/0x15E2 - device pci 1f.7 off end # TH 0xA0A6 + end + device ref hda on end + device ref smbus on end + device ref fast_spi on end + device ref gbe off end + device ref tracehub off end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/83244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009330042b59c9e6e78aa6f3819546b771b26ff0 Gerrit-Change-Number: 83244 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[M] Change in coreboot[main]: soc/intel: Adapt crashlog IP to also support 64-bit
by Pratikkumar V Prajapati (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Nick Vaccaro, Paul Menzel, Sowmya Aralguppe, Subrata Banik, Tarun. Pratikkumar V Prajapati has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email ) Change subject: soc/intel: Adapt crashlog IP to also support 64-bit ...................................................................... Patch Set 22: (1 comment) File src/soc/intel/meteorlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/83106/comment/81bc13ec_e5111dac?us… : PS22, Line 352: + 4 Why do we need to add 4 here? Dont we need to check for 0xdeadbeef also for the first record? in previous code we are checking data at disc_tab_addr + cur_offset to make sure its not 0 and not 0xdeadbeef. -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 22 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 27 Jun 2024 18:59:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/wifi: Support Bluetooth Regulator Domain Settings
by Jérémy Compostella (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Eric Lai, Subrata Banik, YH Lin, dinesh.sharma(a)intel.com. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83200?usp=email ) Change subject: drivers/wifi: Support Bluetooth Regulator Domain Settings ...................................................................... Patch Set 6: (2 comments) File src/drivers/wifi/generic/acpi.c: https://review.coreboot.org/c/coreboot/+/83200/comment/32c90009_112e9f15?us… : PS4, Line 528: package_size = 1 + 1 + 1 + table_size; > nit: a comment here to explain why `1+1+1+table_size` Done https://review.coreboot.org/c/coreboot/+/83200/comment/022c8845_c04885e3?us… : PS4, Line 535: i > nit: int i Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e209 Gerrit-Change-Number: 83200 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dinesh.sharma(a)intel.com Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: dinesh.sharma(a)intel.com Gerrit-Comment-Date: Thu, 27 Jun 2024 18:11:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC
by Jérémy Compostella (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Bob Moragues, Bora Guvendik, Cliff Huang, Eric Lai, Hannah Williams, Poornima Tom, Ravishankar Sarawadi, Subrata Banik, YH Lin, dinesh.sharma(a)intel.com. Jérémy Compostella has posted comments on this change by Poornima Tom. ( https://review.coreboot.org/c/coreboot/+/81790?usp=email ) Change subject: drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC ...................................................................... Patch Set 7: (1 comment) File src/drivers/wifi/generic/acpi.c: https://review.coreboot.org/c/coreboot/+/81790/comment/c4777e3f_146fa3a5?us… : PS5, Line 561: wbem->revision > do we need similar revision check implemented for BT in previous CL ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Gerrit-Change-Number: 81790 Gerrit-PatchSet: 7 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dinesh.sharma(a)intel.com Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Dinesh Sharma <dinesh.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: dinesh.sharma(a)intel.com Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Comment-Date: Thu, 27 Jun 2024 18:10:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: drivers/wifi: Support Bluetooth Regulator Domain Settings
by Jérémy Compostella (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Eric Lai, Jérémy Compostella, YH Lin, dinesh.sharma(a)intel.com. Hello Eric Lai, Subrata Banik, YH Lin, build bot (Jenkins), dinesh.sharma(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83200?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+1 by YH Lin, Verified+1 by build bot (Jenkins) Change subject: drivers/wifi: Support Bluetooth Regulator Domain Settings ...................................................................... drivers/wifi: Support Bluetooth Regulator Domain Settings The 'Bluetooth Increased Power Mode - SAR Limitation' feature provides ability to utilize increased device Transmit power capability for Bluetooth applications in coordination with Wi-Fi adhering to product SAR limit when Bluetooth and Wi-Fi run together. This feature is required for Meteor Lake rex karis variant. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.3 specification. BUG=b:348345301 BRANCH=firmware-rex-15709.B TEST=BRDS method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e209 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/wifi/generic/acpi.c M src/include/sar.h M src/vendorcode/google/chromeos/sar.c 3 files changed, 80 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/83200/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/83200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e209 Gerrit-Change-Number: 83200 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dinesh.sharma(a)intel.com Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: dinesh.sharma(a)intel.com

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