coreboot-gerrit June 2024

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[S] Change in coreboot[main]: drivers/spi/acpi: Add generic property list
by Kun Liu (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Eric Lai, Felix Held, Jian Tong, Karthik Ramasubramanian, Paul Menzel, Shelley Chen, Subrata Banik. Kun Liu has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/83139?usp=email ) Change subject: drivers/spi/acpi: Add generic property list ...................................................................... Patch Set 9: (1 comment) File src/drivers/spi/acpi/chip.h: https://review.coreboot.org/c/coreboot/+/83139/comment/33aeb42f_7537f172?us… : PS8, Line 49: int > unsigned int Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83139?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8 Gerrit-Change-Number: 83139 Gerrit-PatchSet: 9 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Jun 2024 01:12:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: ec/google/chromeec: Stop checking CBI for UCSI
by Daisuke Nojiri (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Abhishek Pandit-Subedi, Caveh Jalali, Forest Mittelberg. Daisuke Nojiri has posted comments on this change by Abhishek Pandit-Subedi. ( https://review.coreboot.org/c/coreboot/+/83252?usp=email ) Change subject: ec/google/chromeec: Stop checking CBI for UCSI ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9d820c637e56a527fd90f45b1848158a960dee7 Gerrit-Change-Number: 83252 Gerrit-PatchSet: 1 Gerrit-Owner: Abhishek Pandit-Subedi <abhishekpandit(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Abhishek Pandit-Subedi <abhishekpandit(a)chromium.org> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Fri, 28 Jun 2024 00:01:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/google/chromeec: Stop checking CBI for UCSI
by Abhishek Pandit-Subedi (Code Review) 27 Jun '24

27 Jun '24

Abhishek Pandit-Subedi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83252?usp=email ) Change subject: ec/google/chromeec: Stop checking CBI for UCSI ...................................................................... ec/google/chromeec: Stop checking CBI for UCSI Use only EC_FEATURE_UCSI_PPM to determine whether UCSI is enabled. BUG=b:319124515 TEST=emerge-brox coreboot chromeos-bootimage Cq-Depend: chromium:5664227 Change-Id: Ia9d820c637e56a527fd90f45b1848158a960dee7 Signed-off-by: Abhishek Pandit-Subedi <abhishekpandit(a)chromium.org> --- M src/ec/google/chromeec/ec.c 1 file changed, 1 insertion(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83252/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index a32b2a5..088f2fe 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -726,7 +726,6 @@ bool google_chromeec_get_ucsi_enabled(void) { int rv; - union ec_common_control cc; rv = google_chromeec_check_feature(EC_FEATURE_UCSI_PPM); if (rv < 0) { @@ -734,18 +733,7 @@ return false; } - if (rv == 0) - return false; - - /* Check if PPM is enabled at runtime. */ - cc.ucsi_enabled = 0; - rv = cbi_get_uint32(&cc.raw_value, CBI_TAG_COMMON_CONTROL); - if (rv < 0) { - printk(BIOS_DEBUG, "Cannot get tag CBI_TAG_COMMON_CONTROL from CBI: status = %d\n", rv); - return false; - } - - return (cc.ucsi_enabled != 0); + return rv != 0; } static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag) -- To view, visit https://review.coreboot.org/c/coreboot/+/83252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9d820c637e56a527fd90f45b1848158a960dee7 Gerrit-Change-Number: 83252 Gerrit-PatchSet: 1 Gerrit-Owner: Abhishek Pandit-Subedi <abhishekpandit(a)chromium.org>

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[S] Change in coreboot[main]: tgl mainboards: Move audio related settings into hda device scope
by Felix Singer (Code Review) 27 Jun '24

27 Jun '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83251?usp=email ) Change subject: tgl mainboards: Move audio related settings into hda device scope ...................................................................... tgl mainboards: Move audio related settings into hda device scope Change-Id: I1992c20dcdc5e974143690d44ee199d7c3394cfd Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 3 files changed, 26 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/83251/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index df13fef..4775b0f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -192,9 +192,6 @@ # - PM_CFG.SLP_LAN_MIN_ASST_WDTH register "PchPmPwrCycDur" = "1" # 1s - # HD Audio - register "PchHdaDspEnable" = "1" - # TCSS USB3 register "UsbTcPortEn" = "0x3" register "TcssXhciEn" = "1" @@ -513,6 +510,8 @@ end end device ref hda on + register "PchHdaDspEnable" = "1" + chip drivers/sof register "spkr_tplg" = "max98373" register "jack_tplg" = "rt5682" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 1434bcd..9c5fa6d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -104,14 +104,6 @@ .tdp_pl4 = 105, }" - #HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkDmicEnable[0]" = "1" - register "PchHdaAudioLinkDmicEnable[1]" = "1" - register "PchHdaAudioLinkSspEnable[0]" = "1" - register "PchHdaAudioLinkSspEnable[2]" = "1" - register "PchHdaAudioLinkSndwEnable[0]" = "1" - # Intel Common SoC Config register "common_soc_config" = "{ .gspi[1] = { @@ -331,7 +323,18 @@ end end end - device ref hda on end + device ref hda on + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkDmicEnable" = "{ + [0] = 1, + [1] = 1, + }" + register "PchHdaAudioLinkSspEnable" = "{ + [0] = 1, + [2] = 1, + }" + register "PchHdaAudioLinkSndwEnable[0]" = "1" + end device ref smbus on end device ref fast_spi on end device ref gbe off end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 83451ec..578eb98 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -111,14 +111,6 @@ .tdp_pl4 = 83, }" - #HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkDmicEnable[0]" = "1" - register "PchHdaAudioLinkDmicEnable[1]" = "1" - register "PchHdaAudioLinkSspEnable[0]" = "1" - register "PchHdaAudioLinkSspEnable[2]" = "1" - register "PchHdaAudioLinkSndwEnable[0]" = "1" - # Intel Common SoC Config register "common_soc_config" = "{ .gspi[1] = { @@ -333,7 +325,18 @@ end end end - device ref hda on end + device ref hda on + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkDmicEnable" = "{ + [0] = 1, + [1] = 1, + }" + register "PchHdaAudioLinkSspEnable" = "{ + [0] = 1, + [2] = 1, + }" + register "PchHdaAudioLinkSndwEnable[0]" = "1" + end device ref smbus on end device ref fast_spi on end device ref gbe off end -- To view, visit https://review.coreboot.org/c/coreboot/+/83251?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1992c20dcdc5e974143690d44ee199d7c3394cfd Gerrit-Change-Number: 83251 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[S] Change in coreboot[main]: tgl mainboards: Drop disabled audio settings from dt
by Felix Singer (Code Review) 27 Jun '24

27 Jun '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83250?usp=email ) Change subject: tgl mainboards: Drop disabled audio settings from dt ...................................................................... tgl mainboards: Drop disabled audio settings from dt Configuring them to 0 is equal to not configuring them at all. So remove them to clean up a bit. Change-Id: I9a9eb370e8e9e8874ad8b4b8ac0f43d61c1a4b9b Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 3 files changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/83250/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index fd51840..df13fef 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -194,13 +194,6 @@ # HD Audio register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHdaEnable" = "0" - register "PchHdaAudioLinkDmicEnable[0]" = "0" - register "PchHdaAudioLinkDmicEnable[1]" = "0" - register "PchHdaAudioLinkSspEnable[0]" = "0" - register "PchHdaAudioLinkSspEnable[1]" = "0" - register "PchHdaAudioLinkSndwEnable[0]" = "0" - register "PchHdaAudioLinkSndwEnable[1]" = "0" # TCSS USB3 register "UsbTcPortEn" = "0x3" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index a42d16f..1434bcd 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -106,11 +106,9 @@ #HD Audio register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHdaEnable" = "0" register "PchHdaAudioLinkDmicEnable[0]" = "1" register "PchHdaAudioLinkDmicEnable[1]" = "1" register "PchHdaAudioLinkSspEnable[0]" = "1" - register "PchHdaAudioLinkSspEnable[1]" = "0" register "PchHdaAudioLinkSspEnable[2]" = "1" register "PchHdaAudioLinkSndwEnable[0]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index e0fb3fd..83451ec 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -113,11 +113,9 @@ #HD Audio register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHdaEnable" = "0" register "PchHdaAudioLinkDmicEnable[0]" = "1" register "PchHdaAudioLinkDmicEnable[1]" = "1" register "PchHdaAudioLinkSspEnable[0]" = "1" - register "PchHdaAudioLinkSspEnable[1]" = "0" register "PchHdaAudioLinkSspEnable[2]" = "1" register "PchHdaAudioLinkSndwEnable[0]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/83250?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a9eb370e8e9e8874ad8b4b8ac0f43d61c1a4b9b Gerrit-Change-Number: 83250 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[S] Change in coreboot[main]: tgl mainboards: Move SATA related settings into SATA device scope
by Felix Singer (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Nick Vaccaro. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83249?usp=email ) Change subject: tgl mainboards: Move SATA related settings into SATA device scope ...................................................................... tgl mainboards: Move SATA related settings into SATA device scope Change-Id: I03508c50fe56fd85f8bf89f724863e546d4140e9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 2 files changed, 11 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/83249/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 61d84cc..fd51840 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -122,12 +122,6 @@ register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" - # Enable SATA - register "SataSalpSupport" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsEnableDitoConfig[1]" = "1" - register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -460,7 +454,12 @@ device ref i2c2 on end device ref i2c3 on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsEnableDitoConfig[1]" = "1" + end device ref pcie_rp7 on end device ref pcie_rp8 on probe DB_SD SD_GL9755S diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index d820c7b..a42d16f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -39,10 +39,6 @@ register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcUsage[3]" = "0x8" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - # enabling EDP in PortA register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" @@ -264,7 +260,11 @@ device ref csme2 off end device ref heci3 off end device ref heci4 off end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + end device ref i2c4 off end device ref i2c5 on end device ref uart2 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/83249?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03508c50fe56fd85f8bf89f724863e546d4140e9 Gerrit-Change-Number: 83249 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/volteer/baseboard: Drop disabled SATA settings from dt
by Felix Singer (Code Review) 27 Jun '24

27 Jun '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83248?usp=email ) Change subject: mb/google/volteer/baseboard: Drop disabled SATA settings from dt ...................................................................... mb/google/volteer/baseboard: Drop disabled SATA settings from dt Configuring them to 0 is equal to not configuring them at all. So remove them to clean up a bit. Change-Id: I18134ac784fffb703e1fe513e5914f05faa749c9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/83248/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index c2815c5..61d84cc 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -124,9 +124,7 @@ # Enable SATA register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "1" register "SataPortsEnableDitoConfig[1]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/83248?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18134ac784fffb703e1fe513e5914f05faa749c9 Gerrit-Change-Number: 83248 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[S] Change in coreboot[main]: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space
by Jérémy Compostella (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu. Jérémy Compostella has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82264?usp=email ) Change subject: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space ...................................................................... Patch Set 8: (1 comment) File src/include/cpu/x86/mtrr.h: https://review.coreboot.org/c/coreboot/+/82264/comment/9de2d3bc_c5a0b4e4?us… : PS8, Line 64: include < > why? it wasn't before and one could as well argue that it looks better […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/82264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b4be85e79007fd1ccf5882de4dfeaeacd98a4db Gerrit-Change-Number: 82264 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 27 Jun 2024 21:20:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: tgl mainboards: Move genx_dec settings into eSPI device scope
by Felix Singer (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Nick Vaccaro. Hello Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83247?usp=email to look at the new patch set (#2). Change subject: tgl mainboards: Move genx_dec settings into eSPI device scope ...................................................................... tgl mainboards: Move genx_dec settings into eSPI device scope Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 3 files changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/83247/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9 Gerrit-Change-Number: 83247 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: tgl mainboards: Move genx_dec settings into LPC device scope
by Felix Singer (Code Review) 27 Jun '24

27 Jun '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83247?usp=email ) Change subject: tgl mainboards: Move genx_dec settings into LPC device scope ...................................................................... tgl mainboards: Move genx_dec settings into LPC device scope Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 3 files changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/83247/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ab088e9..c2815c5 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -93,12 +93,6 @@ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)" register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # NVMe PCIE 9 using clk 0 register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" @@ -518,6 +512,12 @@ end # FPMCU end device ref pch_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 10dcd6c..d820c7b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -17,12 +17,6 @@ # CPU replacement check register "CpuReplacementCheck" = "1" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[8]" = "1" @@ -304,6 +298,12 @@ end end device ref pch_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index fafdbf9..e0fb3fd 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -17,12 +17,6 @@ # CPU replacement check register "CpuReplacementCheck" = "1" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[8]" = "1" @@ -306,6 +300,12 @@ end end device ref pch_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] -- To view, visit https://review.coreboot.org/c/coreboot/+/83247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9 Gerrit-Change-Number: 83247 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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