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Change subject: mb/razer/blade_stealth_kbl: add panel_cfg
......................................................................
Patch Set 13:
(1 comment)
File src/mainboard/razer/blade_stealth_kbl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/82458/comment/1c4fe137_3cb190f6?us… :
PS13, Line 163: .…
[View More]backlight_off_delay_ms = 5000, /* T12 */
Alas, the VBT values are not in *ms*. I think it's 1/10th of a ms (most
hardware registers use multiples of 100us). And the mapping is wrong.
The actual sequence is:
1. power up the panel
2. after T3, configure the panel
3. start video output
4. after T7, enable the backlight (so nobody sees things glitch)
...
5. eventually power down the backlight, wait for T9
6. stop video output
7. after T10, power down the panel
...
8. before powering up again, make sure T12 passed
You can also confirm the used values, comparing the register values read
with `intel_reg`. To make sure you have the devicetree values in Linux,
boot *without* a VBT. cf. https://doc.coreboot.org/gfx/display-panel.html
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Change subject: mb/razer/blade_stealth_kbl: Add H3Q variant
......................................................................
Patch Set 6:
(3 comments)
Patchset:
PS6:
Just one Kconfig nit and OC questions... looks quite good otherwise :)
File src/mainboard/razer/blade_stealth_kbl/Kconfig:
https://review.…
[View More]coreboot.org/c/coreboot/+/82506/comment/66f49e8c_f3f3ac80?us… :
PS6, Line 4: def_bool n
Technically, a `def_bool n` isn't necessary. Only difference are
not being able to override the default later and .config cosmetics:
without a default it won't show up as not enabled. For a mainboard
option, I'd prefer to remove it, i.e. just have `bool` here (other-
wise it would be mentioned in every coreboot .config, no matter
what board is selected).
File src/mainboard/razer/blade_stealth_kbl/variants/h3q/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/82506/comment/12d4efb0_6761bd74?us… :
PS6, Line 7: OC_SKIP
No OC pin seems unlikely for a laptop's external ports. Was this confirmed? or is it simply unknown?
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Change subject: mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM
......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/asrock/spc741d8/ramstage.c:
https://review.coreboot.org/c/coreboot/+/82203/comment/…
[View More]51d39674_6fcc0896?us… :
PS3, Line 15: // stub for EDK2
> SOFTWARE_I2C, however, seems to be designed as a developer option, nothing that
> should be selected by a driver (expect bus number conflicts if some other driver
> tries to use a SoC's I2C bus 0).
lol, I just realized that's what the driver already does... so forget what I
said about selecting it in the board Kconfig.
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Change subject: mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM
......................................................................
Patch Set 9: Code-Review+1
(2 comments)
Patchset:
PS9:
I guess we can just merge this without the FSP-header update. One would
only have …
[View More]to update the include path in menuconfig to build, right? WDYT?
File src/mainboard/asrock/spc741d8/ramstage.c:
https://review.coreboot.org/c/coreboot/+/82203/comment/87e19851_5d494707?us… :
PS3, Line 15: // stub for EDK2
> I2C is used to retrieve the EDID of connected displays. […]
The AST code actually expects CONFIG_SOFTWARE_I2C (i2c bitbanging, I suppose) to
be selected. There's a ast_dp501_read_edid() on the primary path that probably
gets a pre-read EDID from the AST. Only if that fails, I2C is tried. Which path
is taken probably depends on the AST firmware.
SOFTWARE_I2C, however, seems to be designed as a developer option, nothing that
should be selected by a driver (expect bus number conflicts if some other driver
tries to use a SoC's I2C bus 0).
For this board, as we know there is no SoC I2C (i.e. no platform_i2c_transfer()
implemented), the best solution might be to simply select SOFTWARE_I2C from the
board Kconfig. The stub, however, will be needed anyway.
Porting SOFTWARE_I2C to our devicetree infrastructure could solve the bigger
puzzle. Doesn't seem necessary for the Aspeed-using boards so far, though.
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Change subject: arch/arm64: Implement initial set of SMBIOS tables
......................................................................
Patch Set 18:
(1 comment)
File src/arch/arm64/smbios.c:
https://review.coreboot.org/c/coreboot/+/78285/comment/08697a9a_c81524ac?us… :
PS18, Line 6: <console/console.h&…
[View More]gt;
not sure if this is used
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Change subject: src/acpi: Increase ACPI revision from 6.0 to 6.4
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80781/comment/10266da1_ac619b81?us……
[View More]:
PS1, Line 9: Modify ACPI revision from 6.0 to 6.4
> Not sure if other platforms will use 6.0, it is recommended to keep it.
see https://review.coreboot.org/c/coreboot/+/72757
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Change subject: tree: Add smbios_processor_type
......................................................................
Patch Set 2:
(1 comment)
File src/include/smbios.h:
https://review.coreboot.org/c/coreboot/+/82645/comment/d0144b2d_2031a4a8?us… :
PS1, Line 504: …
[View More]SMBIOS_PROCESSOR_TYPE_DSP = 0x05
> Missing comma
Thx
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