coreboot-gerrit May 2024

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[S] Change in coreboot[main]: tree: Add smbios_processor_type
by Elyes Haouas (Code Review) 25 May '24

25 May '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82645?usp=email ) Change subject: tree: Add smbios_processor_type ...................................................................... tree: Add smbios_processor_type Change-Id: I46f799ad255993ac42dab11b5c1d2608daa52b42 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/arm64/smbios.c M src/arch/x86/smbios.c M src/include/smbios.h 3 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/82645/1 diff --git a/src/arch/arm64/smbios.c b/src/arch/arm64/smbios.c index ede48e6..291659a 100644 --- a/src/arch/arm64/smbios.c +++ b/src/arch/arm64/smbios.c @@ -68,7 +68,7 @@ t->processor_version = smbios_processor_name(t->eos); t->processor_family = 0xfe; /* Use processor_family2 field */ t->processor_family2 = 0x101; /* ARMv8 */ - t->processor_type = 3; /* System Processor */ + t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL; smbios_cpu_get_core_counts(&t->core_count2, &t->thread_count2); t->core_count = MAX_CPUS_ENABLED(t->core_count2); diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index a2038b6..0338b60 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -126,7 +126,7 @@ t->processor_manufacturer = smbios_cpu_vendor(t->eos); t->processor_version = smbios_processor_name(t->eos); t->processor_family = smbios_processor_family(res); - t->processor_type = 3; /* System Processor */ + t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL; /* * If CPUID leaf 11 is available, calculate "core count" by dividing * SMT_ID (logical processors in a core) by Core_ID (number of cores). diff --git a/src/include/smbios.h b/src/include/smbios.h index 63e80d9..6eeaaa4 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -496,6 +496,15 @@ #define SMBIOS_PROCESSOR_STATUS_POPULATED (1 << 6) #define SMBIOS_PROCESSOR_STATUS_CPU_ENABLED (1 << 0) +enum smbios_processor_type { + SMBIOS_PROCESSOR_TYPE_OTHER = 0x01, + SMBIOS_PROCESSOR_TYPE_UNKNOWN = 0x02, + SMBIOS_PROCESSOR_TYPE_CENTRAL = 0x03, + SMBIOS_PROCESSOR_TYPE_MATH = 0x04, + SMBIOS_PROCESSOR_TYPE_DSP = 0x05 + SMBIOS_PROCESSOR_TYPE_VIDEO = 0x06, +}; + /* enum for socket type */ enum smbios_processor_upgrade_field { PROCESSOR_UPGRADE_OTHER = 0x01, -- To view, visit https://review.coreboot.org/c/coreboot/+/82645?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46f799ad255993ac42dab11b5c1d2608daa52b42 Gerrit-Change-Number: 82645 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: arch/arm64: Implement initial set of SMBIOS tables
by Lean Sheng Tan (Code Review) 25 May '24

25 May '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78285?usp=email ) ( 16 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch/arm64: Implement initial set of SMBIOS tables ...................................................................... arch/arm64: Implement initial set of SMBIOS tables Implement the two architectural tables: processor and cache. Note that SoC/board code should override core-thread count and, for spec-compliance, create CBMEM_ID_MEMINFO. Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78285 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/Kconfig A src/arch/arm64/smbios.c M src/arch/arm64/tables.c M src/include/smbios.h 4 files changed, 226 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index 645d16c..1ec7552 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -918,8 +918,9 @@ If unsure, say Y. config GENERATE_SMBIOS_TABLES - depends on ARCH_X86 + depends on ARCH_X86 || ARCH_ARM64 bool "Generate SMBIOS tables" + default n if ARCH_ARM64 default y help Generate SMBIOS tables for this board. diff --git a/src/arch/arm64/smbios.c b/src/arch/arm64/smbios.c new file mode 100644 index 0000000..ede48e6 --- /dev/null +++ b/src/arch/arm64/smbios.c @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cache.h> +#include <arch/lib_helpers.h> +#include <arch/smc.h> +#include <console/console.h> +#include <smbios.h> +#include <string.h> + +static void smbios_processor_id(u32 *processor_id) +{ + uint32_t jep106code, soc_revision; + uint64_t midr_el1; + + if (smccc_supports_arch_soc_id()) { + smccc_arch_soc_id(&jep106code, &soc_revision); + processor_id[0] = jep106code; + processor_id[1] = soc_revision; + } else { + midr_el1 = raw_read_midr_el1(); + processor_id[0] = midr_el1; + processor_id[1] = 0; + } +} + +static int smbios_processor_manufacturer(u8 *start) +{ + char midr_el1_implementer; + char buf[32]; + + // [31:24] - Implementer code + midr_el1_implementer = (raw_read_midr_el1() & 0xff000000) >> 24; + + snprintf(buf, sizeof(buf), "CPU implementer %x", midr_el1_implementer); + return smbios_add_string(start, buf); +} + +static int smbios_processor_name(u8 *start) +{ + uint16_t midr_el1_partnumber; + char buf[32]; + + // [15:4] - PartNum + midr_el1_partnumber = (raw_read_midr_el1() & 0xfff0) >> 4; + + snprintf(buf, sizeof(buf), "ARMv8 Processor rev %d", midr_el1_partnumber); + return smbios_add_string(start, buf); +} + +#define MAX_CPUS_ENABLED(cpus) (cpus > 0xff ? 0xff : cpus) + +/* NOTE: Not handling big.LITTLE clusters. Consider using MP services (not yet) or the DSU. */ +int smbios_write_type4(unsigned long *current, int handle) +{ + static unsigned int cnt = 0; + char buf[8]; + uint16_t characteristics = 0; + unsigned int cpu_voltage; + + struct smbios_type4 *t = smbios_carve_table(*current, SMBIOS_PROCESSOR_INFORMATION, + sizeof(*t), handle); + + snprintf(buf, sizeof(buf), "CPU%d", cnt++); + t->socket_designation = smbios_add_string(t->eos, buf); + + smbios_processor_id(t->processor_id); + t->processor_manufacturer = smbios_processor_manufacturer(t->eos); + t->processor_version = smbios_processor_name(t->eos); + t->processor_family = 0xfe; /* Use processor_family2 field */ + t->processor_family2 = 0x101; /* ARMv8 */ + t->processor_type = 3; /* System Processor */ + + smbios_cpu_get_core_counts(&t->core_count2, &t->thread_count2); + t->core_count = MAX_CPUS_ENABLED(t->core_count2); + t->thread_count = MAX_CPUS_ENABLED(t->thread_count2); + /* Assume we always enable all cores */ + t->core_enabled = t->core_count; + t->core_enabled2 = t->core_count2; + t->l1_cache_handle = 0xffff; + t->l2_cache_handle = 0xffff; + t->l3_cache_handle = 0xffff; + t->serial_number = smbios_add_string(t->eos, smbios_processor_serial_number()); + t->status = SMBIOS_PROCESSOR_STATUS_CPU_ENABLED | SMBIOS_PROCESSOR_STATUS_POPULATED; + t->processor_upgrade = PROCESSOR_UPGRADE_UNKNOWN; + + t->external_clock = smbios_processor_external_clock(); + if (t->external_clock == 0) + t->external_clock = (raw_read_cntfrq_el0() / 1000 / 1000); + + t->current_speed = smbios_cpu_get_current_speed_mhz(); + + /* This field identifies a capability for the system, not the processor itself. */ + t->max_speed = smbios_cpu_get_max_speed_mhz(); + + /* TODO: Are "Enhanced Virtualization" (by EL2) and "Power/Performance Control" supported? */ + characteristics |= PROCESSOR_64BIT_CAPABLE; + characteristics |= BIT(5); /* Execute Protection */ + + if (t->core_count > 1) + characteristics |= PROCESSOR_MULTI_CORE; + if (t->thread_count > 1) + characteristics |= BIT(4); /* BIT4: Hardware Thread */ + if (smccc_supports_arch_soc_id()) + characteristics |= BIT(9); /* Arm64 SoC ID */ + + t->processor_characteristics = characteristics | smbios_processor_characteristics(); + + cpu_voltage = smbios_cpu_get_voltage(); + if (cpu_voltage > 0) + t->voltage = 0x80 | cpu_voltage; + + const int len = smbios_full_table_len(&t->header, t->eos); + *current += len; + return len; +} + +int smbios_write_type7_cache_parameters(unsigned long *current, + int *handle, + int *max_struct_size, + struct smbios_type4 *type4) +{ + enum cache_level level = CACHE_L1; + int h; + int len = 0; + + while (1) { + enum smbios_cache_type type; + struct cache_info info; + + const u8 cache_type = cpu_get_cache_type(level); + /* No more caches in the system */ + if (!cache_type) + break; + + switch (cache_type) { + case CACHE_INSTRUCTION: + type = SMBIOS_CACHE_TYPE_INSTRUCTION; + cpu_get_cache_info(level, cache_type, &info); + break; + case CACHE_DATA: + type = SMBIOS_CACHE_TYPE_DATA; + cpu_get_cache_info(level, cache_type, &info); + break; + case CACHE_SEPARATE: + type = SMBIOS_CACHE_TYPE_DATA; + cpu_get_cache_info(level, CACHE_DATA, &info); + h = (*handle)++; + update_max(len, *max_struct_size, smbios_write_type7(current, h, + level, smbios_cache_sram_type(), smbios_cache_associativity(info.associativity), + type, info.size, info.size)); + + type = SMBIOS_CACHE_TYPE_INSTRUCTION; + cpu_get_cache_info(level, CACHE_INSTRUCTION, &info); + break; + case CACHE_UNIFIED: + type = SMBIOS_CACHE_TYPE_UNIFIED; + cpu_get_cache_info(level, cache_type, &info); + break; + default: + type = SMBIOS_CACHE_TYPE_UNKNOWN; + info.size = info.associativity = 0; + break; + } + + h = (*handle)++; + update_max(len, *max_struct_size, smbios_write_type7(current, h, + level, smbios_cache_sram_type(), smbios_cache_associativity(info.associativity), + type, info.size, info.size)); + + if (type4) { + switch (level) { + case 1: + type4->l1_cache_handle = h; + break; + case 2: + type4->l2_cache_handle = h; + break; + case 3: + type4->l3_cache_handle = h; + break; + default: + break; + } + } + + level++; + } + + return len; +} diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index c66612b..059d695 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -6,6 +6,9 @@ #include <boot/tables.h> #include <bootmem.h> #include <cbmem.h> +#include <console/console.h> +#include <smbios.h> +#include <string.h> #include <symbols.h> static void write_acpi_table(void) @@ -18,10 +21,40 @@ printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n", acpi_end - acpi_start); } +static void write_smbios_table(void) +{ + unsigned long smbios_begin, smbios_end; + +#define MAX_SMBIOS_SIZE (32 * KiB) + + smbios_begin = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE); + if (!smbios_begin) { + printk(BIOS_ERR, "Out of memory for SMBIOS tables\n"); + return; + } + + /* + * Clear the entire region to ensure the unused space doesn't + * contain garbage from a previous boot, like stale table + * signatures that could be found by the OS. + */ + memset((void *)smbios_begin, 0, MAX_SMBIOS_SIZE); + + smbios_end = smbios_write_tables(smbios_begin); + + if (smbios_end > (smbios_begin + MAX_SMBIOS_SIZE)) + printk(BIOS_ERR, "Increase SMBIOS size\n"); + + printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n", smbios_end - smbios_begin); +} + void arch_write_tables(uintptr_t coreboot_table) { if (CONFIG(HAVE_ACPI_TABLES)) write_acpi_table(); + + if (CONFIG(GENERATE_SMBIOS_TABLES)) + write_smbios_table(); } void bootmem_arch_add_ranges(void) diff --git a/src/include/smbios.h b/src/include/smbios.h index d4ae662..63e80d9 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -70,6 +70,7 @@ void smbios_system_set_uuid(u8 *uuid); const char *smbios_system_sku(void); +void smbios_cpu_get_core_counts(u16 *core_count, u16 *thread_count); unsigned int smbios_cpu_get_max_speed_mhz(void); unsigned int smbios_cpu_get_current_speed_mhz(void); unsigned int smbios_cpu_get_voltage(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/78285?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15 Gerrit-Change-Number: 78285 Gerrit-PatchSet: 18 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com>

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[M] Change in coreboot[main]: arch/arm64: Support calling a trusted monitor
by Lean Sheng Tan (Code Review) 25 May '24

25 May '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78284?usp=email ) Change subject: arch/arm64: Support calling a trusted monitor ...................................................................... arch/arm64: Support calling a trusted monitor Implement support for generating an SMC to call a trusted monitor. Some functions are provided to read the SoC ID from the monitor, if supported. Change-Id: I158db0b971aba722b3995d52162146aa406d1644 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78284 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/arm64/Makefile.mk A src/arch/arm64/include/armv8/arch/smc.h A src/arch/arm64/smc.c A src/arch/arm64/smc_asm.S 4 files changed, 140 insertions(+), 0 deletions(-) Approvals: Julius Werner: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk index 897dae5..6499283 100644 --- a/src/arch/arm64/Makefile.mk +++ b/src/arch/arm64/Makefile.mk @@ -30,6 +30,9 @@ decompressor-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-y += transition.c transition_asm.S +ifneq ($(CONFIG_ARM64_CURRENT_EL),3) +bootblock-y += smc.c smc_asm.S +endif decompressor-y += memset.S bootblock-y += memset.S @@ -69,6 +72,9 @@ verstage-y += memmove.S verstage-y += transition.c transition_asm.S +ifneq ($(CONFIG_ARM64_CURRENT_EL),3) +verstage-y += smc.c smc_asm.S +endif endif # CONFIG_ARCH_VERSTAGE_ARM64 @@ -88,6 +94,9 @@ romstage-y += ramdetect.c romstage-y += romstage.c romstage-y += transition.c transition_asm.S +ifneq ($(CONFIG_ARM64_CURRENT_EL),3) +romstage-y += smc.c smc_asm.S +endif rmodules_arm64-y += memset.S rmodules_arm64-y += memcpy.S @@ -109,6 +118,7 @@ ramstage-y += div0.c ramstage-y += eabi_compat.c ramstage-y += boot.c +ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-y += tables.c ramstage-y += ramdetect.c ramstage-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c @@ -117,6 +127,9 @@ ramstage-y += memmove.S ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31.c ramstage-y += transition.c transition_asm.S +ifneq ($(CONFIG_ARM64_CURRENT_EL),3) +ramstage-y += smc.c smc_asm.S +endif ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += dma.c diff --git a/src/arch/arm64/include/armv8/arch/smc.h b/src/arch/arm64/include/armv8/arch/smc.h new file mode 100644 index 0000000..2e7cc8a --- /dev/null +++ b/src/arch/arm64/include/armv8/arch/smc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ARM_ARM64_SMC_H +#define ARM_ARM64_SMC_H + +#include <types.h> + +uint64_t smc(uint32_t function_id, uint64_t arg1, uint64_t arg2, uint64_t arg3, + uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7); + +#define smc_call0(function_id) smc(function_id, 0, 0, 0, 0, 0, 0, 0) +#define smc_call1(function_id, a1) smc(function_id, a1, 0, 0, 0, 0, 0, 0) +#define smc_call2(function_id, a1, a2) smc(function_id, a1, a2, 0, 0, 0, 0, 0) +#define smc_call3(function_id, a1, a2, a3) smc(function_id, a1, a2, a3, 0, 0, 0, 0) + +/* Documented in https://developer.arm.com/documentation/den0022/ */ +enum psci_return_values { + PSCI_SUCCESS = 0, + PSCI_NOT_SUPPORTED = -1, + PSCI_INVALID_PARAMETERS = -2, + PSCI_DENIED = -3, + PSCI_ALREADY_ON = -4, + PSCI_ON_PENDING = -5, + PSCI_INTERNAL_FAILURE = -6, + PSCI_NOT_PRESENT = -7, + PSCI_DISABLED = -8, + PSCI_INVALID_ADDRESS = -9, +}; + +/* PSCI functions */ +#define PSCI_VERSION 0x84000000 +#define PSCI_FEATURES 0x8400000a + +/* Documented in https://developer.arm.com/documentation/den0028/ */ +enum smccc_return_values { + SMC_SUCCESS = 0, + SMC_NOT_SUPPORTED = -1, + SMC_NOT_REQUIRED = -2, + SMC_INVALID_PARAMETER = -3, +}; + +/* SMCCC functions */ +#define SMCCC_VERSION 0x80000000 +#define SMCCC_ARCH_FEATURES 0x80000001 +#define SMCCC_ARCH_SOC_ID 0x80000002 +#define SMCCC_GET_SOC_VERSION 0 +#define SMCCC_GET_SOC_REVISION 1 + +uint8_t smccc_supports_arch_soc_id(void); +enum cb_err smccc_arch_soc_id(uint32_t *jep106code, uint32_t *soc_revision); + +#endif /* ARM_ARM64_SMC_H */ diff --git a/src/arch/arm64/smc.c b/src/arch/arm64/smc.c new file mode 100644 index 0000000..9a8883f --- /dev/null +++ b/src/arch/arm64/smc.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/smc.h> +#include <console/console.h> +#include <types.h> + +/* Assumes at least a PSCI implementation is present */ +uint8_t smccc_supports_arch_soc_id(void) +{ + static uint8_t supported = 0xff; + uint64_t smc_ret; + + if (supported != 0xff) + return supported; + + // PSCI_FEATURES mandatory from PSCI 1.0 + smc_ret = smc_call0(PSCI_VERSION); + if (smc_ret < 0x10000) + goto fail; + + smc_ret = smc_call1(PSCI_FEATURES, SMCCC_VERSION); + if (smc_ret == PSCI_NOT_SUPPORTED) + goto fail; + + // SMCCC_ARCH_FEATURES supported from SMCCC 1.1 + smc_ret = smc_call0(SMCCC_VERSION); + if (smc_ret < 0x10001) + goto fail; + + smc_ret = smc_call1(SMCCC_ARCH_FEATURES, SMCCC_ARCH_SOC_ID); + if (smc_ret != SMC_SUCCESS) + goto fail; + + supported = 1; + return supported; + +fail: + supported = 0; + return supported; +} + +enum cb_err smccc_arch_soc_id(uint32_t *jep106code, uint32_t *soc_revision) +{ + uint64_t smc_ret; + + if (jep106code == NULL || soc_revision == NULL) + return CB_ERR_ARG; + + smc_ret = smc_call1(SMCCC_ARCH_SOC_ID, SMCCC_GET_SOC_VERSION); + if (smc_ret != SMC_INVALID_PARAMETER) + *jep106code = smc_ret; + else + *jep106code = -1; + + smc_ret = smc_call1(SMCCC_ARCH_SOC_ID, SMCCC_GET_SOC_REVISION); + if (smc_ret != SMC_INVALID_PARAMETER) + *soc_revision = smc_ret; + else + *soc_revision = -1; + + if (*jep106code == -1 || *soc_revision == -1) { + printk(BIOS_ERR, "SMCCC_ARCH_SOC_ID failed!\n"); + return CB_ERR; + } else + return CB_SUCCESS; +} diff --git a/src/arch/arm64/smc_asm.S b/src/arch/arm64/smc_asm.S new file mode 100644 index 0000000..74b62c1 --- /dev/null +++ b/src/arch/arm64/smc_asm.S @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/asm.h> + +ENTRY(smc) + /* W0, X1-X7 passed as arguments. Function ID is always W0. */ + smc #0 + ret /* X0 passed back as return value */ +ENDPROC(smc) -- To view, visit https://review.coreboot.org/c/coreboot/+/78284?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I158db0b971aba722b3995d52162146aa406d1644 Gerrit-Change-Number: 78284 Gerrit-PatchSet: 20 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>

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[L] Change in coreboot[main]: libpayload: Add x86_64 (64-bit) support
by Julius Werner (Code Review) 24 May '24

24 May '24

Attention is currently required from: Arthur Heymans, Kapil Porwal, Subrata Banik. Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/81968?usp=email ) Change subject: libpayload: Add x86_64 (64-bit) support ...................................................................... Patch Set 77: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81968?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Gerrit-Change-Number: 81968 Gerrit-PatchSet: 77 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 25 May 2024 01:37:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: libpayload: Add x86_64 (64-bit) support
by Subrata Banik (Code Review) 24 May '24

24 May '24

Attention is currently required from: Arthur Heymans, Julius Werner, Kapil Porwal. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/81968?usp=email ) Change subject: libpayload: Add x86_64 (64-bit) support ...................................................................... Patch Set 76: (1 comment) File payloads/libpayload/arch/x86/head_64.S: https://review.coreboot.org/c/coreboot/+/81968/comment/8e7b52fa_691f9f01?us… : PS76, Line 59: #include "multiboot_header.inc" > Sorry, I just realized this doesn't work because `rdmsr` clobbers EAX (and there's no way to get tha […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81968?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Gerrit-Change-Number: 81968 Gerrit-PatchSet: 76 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 25 May 2024 01:36:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[L] Change in coreboot[main]: libpayload: Add x86_64 (64-bit) support
by Subrata Banik (Code Review) 24 May '24

24 May '24

Attention is currently required from: Arthur Heymans, Julius Werner, Kapil Porwal. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81968?usp=email to look at the new patch set (#77). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: libpayload: Add x86_64 (64-bit) support ...................................................................... libpayload: Add x86_64 (64-bit) support This patch introduces x86_64 (64-bit) support to the payload, building upon the existing x86 (32-bit) architecture. Files necessary for 64-bit compilation are now guarded by the `CONFIG_LP_ARCH_X86_64` Kconfig option. BUG=b:242829490 TEST=Able to verify all valid combinations between coreboot and payload with this patch. Payload Entry Point Behavior with below code. +----------------+--------------------+----------------------------+ | LP_ARCH_X86_64 | Payload Entry Mode | Description | +----------------+--------------------+----------------------------+ | No | 32-bit | Direct protected mode init | +----------------+--------------------+----------------------------+ | Yes | 32-bit | Protected to long mode | +----------------+--------------------+----------------------------+ | Yes | 64-bit | Long mode initialization | +----------------+--------------------+----------------------------+ Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.mk M payloads/libpayload/arch/x86/Makefile.mk M payloads/libpayload/arch/x86/exception.c A payloads/libpayload/arch/x86/exception_asm_64.S R payloads/libpayload/arch/x86/exec.c M payloads/libpayload/arch/x86/gdb.c A payloads/libpayload/arch/x86/head_64.S M payloads/libpayload/arch/x86/libpayload.ldscript A payloads/libpayload/arch/x86/pt.S M payloads/libpayload/arch/x86/string.c M payloads/libpayload/bin/lpgcc M payloads/libpayload/drivers/storage/ahci_common.c M payloads/libpayload/drivers/usb/uhci.c M payloads/libpayload/include/x86/arch/exception.h M payloads/libpayload/libc/Makefile.mk M payloads/libpayload/vboot/Makefile.mk 18 files changed, 686 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/81968/77 -- To view, visit https://review.coreboot.org/c/coreboot/+/81968?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Gerrit-Change-Number: 81968 Gerrit-PatchSet: 77 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[L] Change in coreboot[main]: libpayload: Add x86_64 (64-bit) support
by Julius Werner (Code Review) 24 May '24

24 May '24

Attention is currently required from: Arthur Heymans, Kapil Porwal, Subrata Banik. Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/81968?usp=email ) Change subject: libpayload: Add x86_64 (64-bit) support ...................................................................... Patch Set 76: (1 comment) File payloads/libpayload/arch/x86/head_64.S: https://review.coreboot.org/c/coreboot/+/81968/comment/d75f3207_f2e9e613?us… : PS76, Line 59: #include "multiboot_header.inc" Sorry, I just realized this doesn't work because `rdmsr` clobbers EAX (and there's no way to get that instruction to use a different register, right?). So the loader_eax/loader_ebx saving needs to happen before that. I think that's fine because all the included file does is a jump and two moves, that should be fine in both 32 and 64-bit mode. So need to move this `#include` to the top of `_entry`. -- To view, visit https://review.coreboot.org/c/coreboot/+/81968?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Gerrit-Change-Number: 81968 Gerrit-PatchSet: 76 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 25 May 2024 01:21:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/*: Copy bd82x6x boards' USB port config into devicetree
by Keith Hui (Code Review) 24 May '24

24 May '24

Attention is currently required from: Alexander Couzens, Angel Pons, Evgeny Zinoviev, Kevin Keijzer. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/81879?usp=email ) Change subject: mb/*: Copy bd82x6x boards' USB port config into devicetree ...................................................................... Patch Set 2: (1 comment) File src/mainboard/apple/macbookair4_2/devicetree.cb: https://review.coreboot.org/c/coreboot/+/81879/comment/49c8315f_d4dac889?us… : PS2, Line 36: }" > Would be good to end the array on a new line. Working to address these. Then again mb/google/puff has lots of such array ends. -- To view, visit https://review.coreboot.org/c/coreboot/+/81879?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8a967eb3466106f3a34e024260e13d02f449a25 Gerrit-Change-Number: 81879 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Sat, 25 May 2024 00:17:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: mb/razer/blade_stealth_kbl: Add H3Q variant
by Reagan (Code Review) 24 May '24

24 May '24

Attention is currently required from: Paul Menzel. Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82506?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/razer/blade_stealth_kbl: Add H3Q variant ...................................................................... mb/razer/blade_stealth_kbl: Add H3Q variant The Razer Blade Stealth Kaby Lake has 2 variants. One is the H2U variant, as originally commited, with the SKU number RZ09-01962, also known as the 2016 model, and the H3Q model with SKU numbers RZ09-01963 and RZ09-01964, known as the Mid 2017 model. This commit adds support for the H3Q model. With respect to coreboot, there are few known differences: 1. Only the H2U has TPM. 2. The USB ports are different. 3. The screen size (and therefore VBIOS Table) is different. 4. The hda_verb is very slightly different. Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4 Signed-off-by: Reagan Bohan <xbjfk.github(a)gmail.com> --- M src/mainboard/razer/blade_stealth_kbl/Kconfig M src/mainboard/razer/blade_stealth_kbl/Kconfig.name M src/mainboard/razer/blade_stealth_kbl/Makefile.mk M src/mainboard/razer/blade_stealth_kbl/board_info.txt M src/mainboard/razer/blade_stealth_kbl/devicetree.cb A src/mainboard/razer/blade_stealth_kbl/variants/h2u/board_info.txt R src/mainboard/razer/blade_stealth_kbl/variants/h2u/hda_verb.c A src/mainboard/razer/blade_stealth_kbl/variants/h2u/overridetree.cb A src/mainboard/razer/blade_stealth_kbl/variants/h3q/board_info.txt C src/mainboard/razer/blade_stealth_kbl/variants/h3q/hda_verb.c A src/mainboard/razer/blade_stealth_kbl/variants/h3q/overridetree.cb 11 files changed, 110 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/82506/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/82506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4 Gerrit-Change-Number: 82506 Gerrit-PatchSet: 5 Gerrit-Owner: Reagan <xbjfk.github(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Make space for USB port config in devicetree
by Keith Hui (Code Review) 24 May '24

24 May '24

Attention is currently required from: Angel Pons. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/81878?usp=email ) Change subject: sb/intel/bd82x6x: Make space for USB port config in devicetree ...................................................................... Patch Set 2: (1 comment) File src/southbridge/intel/bd82x6x/chip.h: https://review.coreboot.org/c/coreboot/+/81878/comment/0c11dc25_487c5d6b?us… : PS2, Line 12: USB_GAIN_1 > There's something similar in coreboot `pch_is_mobile` and `pch_silicon_type`. […] Recently it has become clear to me that the relation is relatively simple: Mobile PCHs: MRC 0x40/0x80 -> native 0/1 Desktop PCHs: MRC 0x40/0x80 -> native 1/2 I may not need these enums at all, but keeping them just in case. Without hardware to test with, best I can do is maintain status quo, making sure things aren't worse than when I found them. I'm now sorting out later patches in the train. -- To view, visit https://review.coreboot.org/c/coreboot/+/81878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59af466d41790e2163342cac8676457ac19371ea Gerrit-Change-Number: 81878 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 24 May 2024 23:25:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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