coreboot-gerrit May 2024

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[S] Change in coreboot[main]: soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility
by Appukuttan V K (Code Review) 24 May '24

24 May '24

Attention is currently required from: Paul Menzel, Subrata Banik. Appukuttan V K has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82177?usp=email ) Change subject: soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility ...................................................................... Patch Set 16: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82177/comment/30959191_c622eb5f?us… : PS14, Line 10: Meteorlake > Meteor Lake Done https://review.coreboot.org/c/coreboot/+/82177/comment/c008959d_37314f0e?us… : PS14, Line 13: has been > is Done https://review.coreboot.org/c/coreboot/+/82177/comment/f1ac53c8_86b11bd9?us… : PS14, Line 18: has been > is Done https://review.coreboot.org/c/coreboot/+/82177/comment/02772f18_a744785c?us… : PS14, Line 18: In meminit.c, the type for SPD pointers has been changed from : uint32_t to efi_uintn_t to support both 32-bit and 64-bit builds. > What does that have to do with FSP2. […] x64 build is enabled with FSP2.4. The changes are made such a way that it will build for x32 and x64 architecture also with different fsp spec versions. updated the commit message to indicate the x32 and x64 part as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/82177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a Gerrit-Change-Number: 82177 Gerrit-PatchSet: 16 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 24 May 2024 18:34:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: vc/intel/fsp/mtl: Organize FSP headers into x86_32 directory
by Subrata Banik (Code Review) 24 May '24

24 May '24

Attention is currently required from: Appukuttan V K, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Ronak Kanabar, Tarun. Subrata Banik has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82424?usp=email ) Change subject: vc/intel/fsp/mtl: Organize FSP headers into x86_32 directory ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82424/comment/25f6ddcf_61567d4f?us… : PS10, Line 9: files please specify the FSP version just for record -- To view, visit https://review.coreboot.org/c/coreboot/+/82424?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id30186a8b1b5a9082f498e18a3378f5e9907b668 Gerrit-Change-Number: 82424 Gerrit-PatchSet: 10 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 24 May 2024 18:25:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/pcengines/apu2/mainboard: fix up ECC scrubber configuration
by Felix Held (Code Review) 24 May '24

24 May '24

Attention is currently required from: Krystian Hebel, Michał Żygowski, Nico Huber, Piotr Król. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/79612?usp=email ) Change subject: mb/pcengines/apu2/mainboard: fix up ECC scrubber configuration ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > Which version of AGESA binary (version, hash, source) are you testing with? i think i just used what's in the blob repo and iirc that also matched what i pulled form a pre-built binary; don't remember changing any config for that, so should just be the default one in upstream coreboot. would need to re-check to say for sure though. if you're using some other agesa binary, try applying this patch, or just use the prebuilt image that's built from the repo/branch this patch is based on, and then check the dram ecc enable bit 22 in D18F3x44. if that bit is 0, the dram won't be using ecc. i'd expect that bit being written long before fixup_dram_ecc_scrubber is called. just had a look and the public bkdg says in the description of the DramEccEn bit in D18F3x44 MCA NB Configuration "This bit does not affect ECC checking in the northbridge arrays.". since the northbridge arrays seem to be where the error injection is done, i wonder if just having the error injection working doesn't imply that the dram controller is using ecc on the dram interface. but yeah, i don't know for sure how the error injection is working exactly, but the DramEccEn bit not being set should be a rather clear indicator of ecc not being used in the dram controller -- To view, visit https://review.coreboot.org/c/coreboot/+/79612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifb0cb117bedf900642e93c556a64800e1e52b6ea Gerrit-Change-Number: 79612 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 24 May 2024 18:14:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility
by Appukuttan V K (Code Review) 24 May '24

24 May '24

Attention is currently required from: Appukuttan V K, Dinesh Gehlot, Ronak Kanabar, Subrata Banik. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Ronak Kanabar, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82177?usp=email to look at the new patch set (#16). Change subject: soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility ...................................................................... soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility This commit updates the type definitions for FSP parameters in the Meteor Lake platform to ensure compatibility with the FSP2.4 specification and also ensures that parameter types works for both 32-bit and 64-bit builds. - In fsp_params.c, FSPS_ARCH_UPD macro is changed to FSPS_ARCHx_UPD which supports FSP2.4 and older specifications. Special handling is added for FspEventHandler assignment to handle as the variable type is different in both cases. - In meminit.c, the type for SPD pointers is changed from uint32_t to efi_uintn_t to support both 32-bit and 64-bit builds. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/meteorlake/meminit.c M src/soc/intel/meteorlake/romstage/fsp_params.c 3 files changed, 15 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/82177/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/82177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a Gerrit-Change-Number: 82177 Gerrit-PatchSet: 16 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility
by Appukuttan V K (Code Review) 24 May '24

24 May '24

Attention is currently required from: Appukuttan V K, Dinesh Gehlot, Ronak Kanabar, Subrata Banik. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Ronak Kanabar, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82177?usp=email to look at the new patch set (#15). Change subject: soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility ...................................................................... soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility This commit updates the type definitions for FSP parameters in the Meteor Lake platform to ensure compatibility with the FSP2.4 specification - In fsp_params.c, FSPS_ARCH_UPD macro is changed to FSPS_ARCHx_UPD which supports FSP2.4 and older specifications. Special handling is added for FspEventHandler assignment to handle as the variable type is different in both cases. - In meminit.c, the type for SPD pointers is changed from uint32_t to efi_uintn_t to support both 32-bit and 64-bit builds. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/meteorlake/meminit.c M src/soc/intel/meteorlake/romstage/fsp_params.c 3 files changed, 15 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/82177/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/82177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a Gerrit-Change-Number: 82177 Gerrit-PatchSet: 15 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com>

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[XS] Change in coreboot[main]: acpi/acpi_apic: use generic MADT IRQ override function for SCI override
by Felix Held (Code Review) 24 May '24

24 May '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82644?usp=email ) Change subject: acpi/acpi_apic: use generic MADT IRQ override function for SCI override ...................................................................... acpi/acpi_apic: use generic MADT IRQ override function for SCI override Call acpi_create_madt_irqoverride from acpi_create_madt_sci_override with the correct parameters instead or re-implementing the same functionality. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7e6ee0eed837c2d46da62092b7cc5669dc177d8d --- M src/acpi/acpi_apic.c 1 file changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/82644/1 diff --git a/src/acpi/acpi_apic.c b/src/acpi/acpi_apic.c index 4b5b0fe..45d642a 100644 --- a/src/acpi/acpi_apic.c +++ b/src/acpi/acpi_apic.c @@ -132,14 +132,7 @@ if (CONFIG(ACPI_NO_PCAT_8259)) irq = gsi; - irqoverride->type = IRQ_SOURCE_OVERRIDE; /* Interrupt source override */ - irqoverride->length = sizeof(acpi_madt_irqoverride_t); - irqoverride->bus = MP_BUS_ISA; - irqoverride->source = irq; - irqoverride->gsirq = gsi; - irqoverride->flags = flags; - - return irqoverride->length; + return acpi_create_madt_irqoverride(irqoverride, MP_BUS_ISA, irq, gsi, flags); } static unsigned long acpi_create_madt_ioapic_gsi0_default(unsigned long current) -- To view, visit https://review.coreboot.org/c/coreboot/+/82644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e6ee0eed837c2d46da62092b7cc5669dc177d8d Gerrit-Change-Number: 82644 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: acpi/acpi_apic;arch/x86/acpi: better document ACPI_NO_PCAT_8259 case
by Tim Wawrzynczak (Code Review) 24 May '24

24 May '24

Attention is currently required from: Cliff Huang, Felix Held, Jérémy Compostella, Lance Zhao. Tim Wawrzynczak has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/82643?usp=email ) Change subject: acpi/acpi_apic;arch/x86/acpi: better document ACPI_NO_PCAT_8259 case ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6dcf59d5ab9226c61e9c4af95a73a07771b71d1 Gerrit-Change-Number: 82643 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 24 May 2024 15:51:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: acpi: drop sort-of duplicate ACPI_HAVE_PCAT_8259 option
by Felix Held (Code Review) 24 May '24

24 May '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Lance Zhao, Tim Wawrzynczak. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/82642?usp=email ) Change subject: acpi: drop sort-of duplicate ACPI_HAVE_PCAT_8259 option ...................................................................... Patch Set 1: (1 comment) File src/acpi/acpi_apic.c: https://review.coreboot.org/c/coreboot/+/82642/comment/92e46a5a_fcaff2ed?us… : PS1, Line 130: ACPI_HAVE_PCAT_8259 > the spec says this in the explanation of the SCI_INT FADT field: "System vector the SCI interrupt is […] pushed a follow-up adding comments with a bit of documentation -- To view, visit https://review.coreboot.org/c/coreboot/+/82642?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I246ecfda5bb156d151512e5dbf432a113fad51a2 Gerrit-Change-Number: 82642 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Fri, 24 May 2024 15:46:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: acpi/acpi_apic;arch/x86/acpi: better document ACPI_NO_PCAT_8259 case
by Felix Held (Code Review) 24 May '24

24 May '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82643?usp=email ) Change subject: acpi/acpi_apic;arch/x86/acpi: better document ACPI_NO_PCAT_8259 case ...................................................................... acpi/acpi_apic;arch/x86/acpi: better document ACPI_NO_PCAT_8259 case Both acpi_create_madt_sci_override and acpi_sci_int have special handling for the ACPI_NO_PCAT_8259 case, but those cases weren't exactly obvious, so add a comment with the reason for that. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia6dcf59d5ab9226c61e9c4af95a73a07771b71d1 --- M src/acpi/acpi_apic.c M src/arch/x86/acpi.c 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/82643/1 diff --git a/src/acpi/acpi_apic.c b/src/acpi/acpi_apic.c index f367581..4b5b0fe 100644 --- a/src/acpi/acpi_apic.c +++ b/src/acpi/acpi_apic.c @@ -127,6 +127,8 @@ ioapic_get_sci_pin(&gsi, &irq, &flags); + /* In systems without 8259, the SCI_INT field in the FADT contains the SCI GSI number + instead of the 8259 IRQ number */ if (CONFIG(ACPI_NO_PCAT_8259)) irq = gsi; diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index bb61cd7..38efe13 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -12,7 +12,8 @@ ioapic_get_sci_pin(&gsi, &irq, &flags); - /* ACPI Release 6.5, 5.2.9 and 5.2.15.5. */ + /* In systems without 8259, the SCI_INT field in the FADT contains the SCI GSI number + instead of the 8259 IRQ number */ if (CONFIG(ACPI_NO_PCAT_8259)) return gsi; -- To view, visit https://review.coreboot.org/c/coreboot/+/82643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6dcf59d5ab9226c61e9c4af95a73a07771b71d1 Gerrit-Change-Number: 82643 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: acpi: drop sort-of duplicate ACPI_HAVE_PCAT_8259 option
by Felix Held (Code Review) 24 May '24

24 May '24

Attention is currently required from: Cliff Huang, Felix Held, Jérémy Compostella, Lance Zhao, Tim Wawrzynczak. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/82642?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: acpi: drop sort-of duplicate ACPI_HAVE_PCAT_8259 option ...................................................................... Patch Set 1: (1 comment) File src/acpi/acpi_apic.c: https://review.coreboot.org/c/coreboot/+/82642/comment/e16f5ab6_05104d78?us… : PS1, Line 130: ACPI_HAVE_PCAT_8259 > i'm not sure what you mean here. […] the spec says this in the explanation of the SCI_INT FADT field: "System vector the SCI interrupt is wired to in 8259 mode. On systems that do not contain the 8259, this field contains the Global System interrupt number of the SCI interrupt." there's also this explanation in the interrupt source override structure "You must have an interrupt source override entry for the IRQ mapped to the SCI interrupt if this IRQ is not identity mapped. This entry will override the value in SCI_INT in FADT. For example, if SCI is connected to IRQ 9 in PIC mode and IRQ 9 is connected to INTIN11 in APIC mode, you should have 9 in SCI_INT in the FADT and an interrupt source override entry mapping IRQ 9 to INTIN11.". so while this part of the code does look rather odd, this seems to be correct. i guess those are also the sections of the acpi spec referenced in src/arch/x86/acpi.c -- To view, visit https://review.coreboot.org/c/coreboot/+/82642?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I246ecfda5bb156d151512e5dbf432a113fad51a2 Gerrit-Change-Number: 82642 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 24 May 2024 15:14:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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