coreboot-gerrit May 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: arch/arm64: Support FEAT_CCIDX
by Yidi Lin (Code Review) 24 May '24

24 May '24

Attention is currently required from: Julius Werner, Paul Menzel. Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/82635?usp=email ) Change subject: arch/arm64: Support FEAT_CCIDX ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82635/comment/17a0b9f8_f168f8b2?us… : PS1, Line 21: TEST=mmu_disable works on the FEAT_CCIDX supported SoC. > List one concrete example device you tested with? No. -- To view, visit https://review.coreboot.org/c/coreboot/+/82635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieadd0d9dfb8911039b3d36c9419af4ae04ed814c Gerrit-Change-Number: 82635 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 24 May 2024 13:21:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: device/pci_rom: handle non-remapped VGA_BIOS_ID
by Felix Held (Code Review) 24 May '24

24 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82592?usp=email ) Change subject: device/pci_rom: handle non-remapped VGA_BIOS_ID ...................................................................... device/pci_rom: handle non-remapped VGA_BIOS_ID While the SoC-level defaults for VGA_BIOS_ID are the expected correctly remapped PCI VID/PID of the GPU which matches the PCI VID/DID inside the VBIOS file, some mainboards override the VGA_BIOS_ID setting to the non-remapped PCI ID. This resulted in coreboot not finding the VBIOS file after commit 42f0396a1028 ("device/pci_rom: rework PCI ID remapping in pci_rom_probe"). The proper solution would be to not override this SoC-level config in neither the mainboard code nor some external config file. This however requires adding/using some mechanism to tell SeaBIOS which VBIOS image to use for the GPU device. Once this is implemented, the SoC default for VGA_BIOS_ID shouldn't be overridden any more and this patch can be reverted again. This sort-of reverts parts of commit 42f0396a1028 ("device/pci_rom: rework PCI ID remapping in pci_rom_probe"), but it still tries to find the VBIOS image with the expected remapped PCI ID and only adds trying the non-remapped PCI ID as a fallback when the file with the remapped PCI ID doesn't exist and prints a notice in that case. Before the patch referenced above, using the correct remapped PCI VID/DID resulted in a warning about the CBFS file with the non-remapped name not being found, but first checking the remapped version solves that problem. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7cd8e2036250f4ca2239b04cd070bbf0778b13aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/82592 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/device/pci_rom.c 1 file changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index b9210b0..7679552 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -49,6 +49,17 @@ mapped_vendev = map_oprom_vendev(vendev); rom_header = cbfs_boot_map_optionrom(mapped_vendev >> 16, mapped_vendev & 0xffff); + /* Handle the case of VGA_BIOS_ID not being set to the remapped PCI ID. This is a + workaround that should be removed once the underlying issue is fixed. */ + if (!rom_header && vendev != mapped_vendev) { + rom_header = cbfs_boot_map_optionrom(vendev >> 16, vendev & 0xffff); + if (rom_header) { + printk(BIOS_NOTICE, "VGA_BIOS_ID should be the remapped PCI ID " + "%04hx,%04hx in the VBIOS file\n", + mapped_vendev >> 16, mapped_vendev & 0xffff); + } + } + if (rom_header) { printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n", dev_path(dev), rom_header); -- To view, visit https://review.coreboot.org/c/coreboot/+/82592?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7cd8e2036250f4ca2239b04cd070bbf0778b13aa Gerrit-Change-Number: 82592 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/qemu-{i440fx,q35}: reduce default ROM size to 8M
by Maciej Pijanowski (Code Review) 24 May '24

24 May '24

Attention is currently required from: Krystian Hebel, Michał Kopeć, Michał Żygowski, Patrick Rudolph, Sergii Dmytruk. Maciej Pijanowski has posted comments on this change by Krystian Hebel. ( https://review.coreboot.org/c/coreboot/+/82639?usp=email ) Change subject: mb/qemu-{i440fx,q35}: reduce default ROM size to 8M ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82639/comment/8e671cdd_637970be?us… : PS1, Line 9: QEMU doesn't allow to use bigger images with '-drive if=pflash', which What is the effect here? Do we know why it is not supported? -- To view, visit https://review.coreboot.org/c/coreboot/+/82639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If36cb754a8e75e23bce49ff568dd88e5db279bb8 Gerrit-Change-Number: 82639 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Fri, 24 May 2024 13:07:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: acpi: drop sort-of duplicate ACPI_HAVE_PCAT_8259 option
by Felix Held (Code Review) 24 May '24

24 May '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Lance Zhao, Tim Wawrzynczak. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82642?usp=email ) Change subject: acpi: drop sort-of duplicate ACPI_HAVE_PCAT_8259 option ...................................................................... acpi: drop sort-of duplicate ACPI_HAVE_PCAT_8259 option Apollo Lake SoC is the only SoC that selects ACPI_NO_PCAT_8259 and ACPI_HAVE_PCAT_8259 was automatically selected when ACPI_NO_PCAT_8259 wasn't selected, so drop the ACPI_HAVE_PCAT_8259 Kconfig option and use ACPI_NO_PCAT_8259 in the code instead. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I246ecfda5bb156d151512e5dbf432a113fad51a2 --- M src/acpi/Kconfig M src/acpi/acpi_apic.c M src/arch/x86/acpi.c 3 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/82642/1 diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 2bb56ba..7dd75f9 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -22,9 +22,6 @@ pressed. A value of 0 is ignored, which is the default since most keyboards do not emit a scancode for the Fn key. -config ACPI_HAVE_PCAT_8259 - def_bool y if !ACPI_NO_PCAT_8259 - config ACPI_INTEL_HARDWARE_SLEEP_VALUES def_bool n help diff --git a/src/acpi/acpi_apic.c b/src/acpi/acpi_apic.c index ebff44f..f367581 100644 --- a/src/acpi/acpi_apic.c +++ b/src/acpi/acpi_apic.c @@ -127,7 +127,7 @@ ioapic_get_sci_pin(&gsi, &irq, &flags); - if (!CONFIG(ACPI_HAVE_PCAT_8259)) + if (CONFIG(ACPI_NO_PCAT_8259)) irq = gsi; irqoverride->type = IRQ_SOURCE_OVERRIDE; /* Interrupt source override */ @@ -233,7 +233,7 @@ { madt->lapic_addr = cpu_get_lapic_addr(); - if (CONFIG(ACPI_HAVE_PCAT_8259)) + if (!CONFIG(ACPI_NO_PCAT_8259)) madt->flags |= ACPI_MADT_PCAT_COMPAT; if (CONFIG(ACPI_COMMON_MADT_LAPIC)) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 2497143..bb61cd7 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -13,7 +13,7 @@ ioapic_get_sci_pin(&gsi, &irq, &flags); /* ACPI Release 6.5, 5.2.9 and 5.2.15.5. */ - if (!CONFIG(ACPI_HAVE_PCAT_8259)) + if (CONFIG(ACPI_NO_PCAT_8259)) return gsi; assert(irq < 16); -- To view, visit https://review.coreboot.org/c/coreboot/+/82642?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I246ecfda5bb156d151512e5dbf432a113fad51a2 Gerrit-Change-Number: 82642 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>

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[XS] Change in coreboot[main]: acpi: add and use defines for LAPIC feature flags
by Felix Held (Code Review) 24 May '24

24 May '24

Attention is currently required from: Cliff Huang, Lance Zhao, Tim Wawrzynczak. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82641?usp=email ) Change subject: acpi: add and use defines for LAPIC feature flags ...................................................................... acpi: add and use defines for LAPIC feature flags Both the processor local APIC structure and the processor local x2APIC structure use the same flag bit definitions. ACPI spec 6.4 was used as a reference. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8101c2ea874c8b12b130dbe9a0a7e0f0d94adffa --- M src/acpi/acpi_apic.c M src/include/acpi/acpi.h 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/82641/1 diff --git a/src/acpi/acpi_apic.c b/src/acpi/acpi_apic.c index 9098811..ebff44f 100644 --- a/src/acpi/acpi_apic.c +++ b/src/acpi/acpi_apic.c @@ -11,7 +11,7 @@ { lapic->type = LOCAL_APIC; /* Local APIC structure */ lapic->length = sizeof(acpi_madt_lapic_t); - lapic->flags = (1 << 0); /* Processor/LAPIC enabled */ + lapic->flags = ACPI_MADT_LAPIC_ENABLED; lapic->processor_id = cpu; lapic->apic_id = apic; @@ -23,7 +23,7 @@ lapic->type = LOCAL_X2APIC; /* Local APIC structure */ lapic->reserved = 0; lapic->length = sizeof(acpi_madt_lx2apic_t); - lapic->flags = (1 << 0); /* Processor/LAPIC enabled */ + lapic->flags = ACPI_MADT_LAPIC_ENABLED; lapic->processor_id = cpu; lapic->x2apic_id = apic; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 0e5b4b2..4a71aef 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -726,6 +726,10 @@ #define ACPI_MADT_MAX_LAPIC_ID 0xfe +/* MADT Local APIC Feature Flags */ +#define ACPI_MADT_LAPIC_ENABLED (1 << 0) +#define ACPI_MADT_LAPIC_ONLINE_CAPABLE (1 << 1) + /* MADT: Local APIC NMI Structure */ typedef struct acpi_madt_lapic_nmi { u8 type; /* Type (4) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/82641?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8101c2ea874c8b12b130dbe9a0a7e0f0d94adffa Gerrit-Change-Number: 82641 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>

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[XS] Change in coreboot[main]: acpi: introduce and use ACPI_MADT_PCAT_COMPAT define
by Felix Held (Code Review) 24 May '24

24 May '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82640?usp=email ) Change subject: acpi: introduce and use ACPI_MADT_PCAT_COMPAT define ...................................................................... acpi: introduce and use ACPI_MADT_PCAT_COMPAT define The multiple APIC flags table from the ACPI specification version 6.4 was used as a reference. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I36f67ca21465bc8753bb36896ee05669de6de333 --- M src/acpi/acpi_apic.c M src/include/acpi/acpi.h 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/82640/1 diff --git a/src/acpi/acpi_apic.c b/src/acpi/acpi_apic.c index 2b3402a..9098811 100644 --- a/src/acpi/acpi_apic.c +++ b/src/acpi/acpi_apic.c @@ -234,7 +234,7 @@ madt->lapic_addr = cpu_get_lapic_addr(); if (CONFIG(ACPI_HAVE_PCAT_8259)) - madt->flags |= 1; + madt->flags |= ACPI_MADT_PCAT_COMPAT; if (CONFIG(ACPI_COMMON_MADT_LAPIC)) current = acpi_create_madt_lapics_with_nmis(current); diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index d6c30c1..0e5b4b2 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -458,6 +458,9 @@ u32 flags; /* Multiple APIC flags */ } __packed acpi_madt_t; +/* MADT Feature Flags */ +#define ACPI_MADT_PCAT_COMPAT (1 << 0) + /* * LPIT (Low Power Idle Table) * Conforms to "Intel Low Power S0 Idle" specification, rev 002 from July 2017. -- To view, visit https://review.coreboot.org/c/coreboot/+/82640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36f67ca21465bc8753bb36896ee05669de6de333 Gerrit-Change-Number: 82640 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flash
by Krystian Hebel (Code Review) 24 May '24

24 May '24

Attention is currently required from: Michał Kopeć, Michał Żygowski, Patrick Rudolph, Paul Menzel, Sergii Dmytruk. Krystian Hebel has posted comments on this change by Krystian Hebel. ( https://review.coreboot.org/c/coreboot/+/82555?usp=email ) Change subject: mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flash ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82555/comment/e6969ffc_73d38479?us… : PS4, Line 18: 8 > The default is BOARD_ROMSIZE_KB_16384. […] Changed in CB:82639. QEMU bails out immediately, but only for `-drive if=pflash`, `-bios` can use up to 16M images. File src/mainboard/emulation/qemu-i440fx/rom_media.c: https://review.coreboot.org/c/coreboot/+/82555/comment/fbfa09dc_18be5128?us… : PS4, Line 138: uintptr_t > base is a pointer, no need for cast here Acknowledged https://review.coreboot.org/c/coreboot/+/82555/comment/477887e3_29e5d495?us… : PS4, Line 158: flash_ops > Should there be a readat() implementation that is always available? `mdev_readat` is used for all 3 options, it is copied in line 131 from `mem_rdev_rw_ops`. -- To view, visit https://review.coreboot.org/c/coreboot/+/82555?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ab9f22c6165064a769881d4be5eab13a0a2f519 Gerrit-Change-Number: 82555 Gerrit-PatchSet: 5 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Fri, 24 May 2024 12:23:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[S] Change in coreboot[main]: mb/qemu-{i440fx,q35}: reduce default ROM size to 8M
by Krystian Hebel (Code Review) 24 May '24

24 May '24

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82639?usp=email ) Change subject: mb/qemu-{i440fx,q35}: reduce default ROM size to 8M ...................................................................... mb/qemu-{i440fx,q35}: reduce default ROM size to 8M QEMU doesn't allow to use bigger images with '-drive if=pflash', which is required to make use of writable flash introduced in CB:82555. This changes both default size in Kconfig as well as FMAP layouts. Change-Id: If36cb754a8e75e23bce49ff568dd88e5db279bb8 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/mainboard/emulation/qemu-i440fx/Kconfig R src/mainboard/emulation/qemu-i440fx/vboot-rwa-8M.fmd M src/mainboard/emulation/qemu-q35/Kconfig D src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd C src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd R src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd 6 files changed, 15 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/82639/1 diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 842c053..6d6181c 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -12,7 +12,7 @@ select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 if !VBOOT - select BOARD_ROMSIZE_KB_16384 if VBOOT + select BOARD_ROMSIZE_KB_8192 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_ASAN_IN_ROMSTAGE @@ -52,7 +52,7 @@ endif config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa-8M.fmd" if VBOOT_SLOTS_RW_A config VBOOT_VBNV_OFFSET hex diff --git a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-8M.fmd similarity index 65% rename from src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd rename to src/mainboard/emulation/qemu-i440fx/vboot-rwa-8M.fmd index 0d2c9da..55a38b7 100644 --- a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-8M.fmd @@ -1,8 +1,8 @@ -FLASH@0xff000000 0x1000000 { - SI_BIOS 0x1000000 { - RW_SECTION_A 0x7c0000 { +FLASH@0xff800000 0x800000 { + SI_BIOS 0x800000 { + RW_SECTION_A 0x3c0000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) 0x74ffc0 + FW_MAIN_A(CBFS) RW_FWID_A 0x40 } RW_VPD(PRESERVE) 0x1000 diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 2fb180b..70a7437 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -10,7 +10,7 @@ select HAVE_OPTION_TABLE # select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_16384 + select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT if !CHROMEOS select MEMORY_MAPPED_TPM @@ -29,8 +29,8 @@ select GBB_FLAG_DISABLE_FWMP config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab-16M.fmd" if VBOOT_SLOTS_RW_AB + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa-8M.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab-8M.fmd" if VBOOT_SLOTS_RW_AB if ARCH_BOOTBLOCK_X86_64 diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd deleted file mode 100644 index 0d2c9da..0000000 --- a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd +++ /dev/null @@ -1,19 +0,0 @@ -FLASH@0xff000000 0x1000000 { - SI_BIOS 0x1000000 { - RW_SECTION_A 0x7c0000 { - VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) 0x74ffc0 - RW_FWID_A 0x40 - } - RW_VPD(PRESERVE) 0x1000 - - WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 - RO_VPD(PRESERVE) 0x1000 - GBB 0x1e000 - COREBOOT(CBFS) - } - } -} diff --git a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd similarity index 65% copy from src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd copy to src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd index 0d2c9da..55a38b7 100644 --- a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd @@ -1,8 +1,8 @@ -FLASH@0xff000000 0x1000000 { - SI_BIOS 0x1000000 { - RW_SECTION_A 0x7c0000 { +FLASH@0xff800000 0x800000 { + SI_BIOS 0x800000 { + RW_SECTION_A 0x3c0000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) 0x74ffc0 + FW_MAIN_A(CBFS) RW_FWID_A 0x40 } RW_VPD(PRESERVE) 0x1000 diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd similarity index 89% rename from src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd rename to src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd index fcbfa95..8064fdf 100644 --- a/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd @@ -1,5 +1,5 @@ -FLASH@0xff000000 0x1000000 { - SI_BIOS 0x1000000 { +FLASH@0xff800000 0x800000 { + SI_BIOS 0x800000 { RW_SECTION_A 0x1c0000 { VBLOCK_A 0x10000 FW_MAIN_A(CBFS) -- To view, visit https://review.coreboot.org/c/coreboot/+/82639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If36cb754a8e75e23bce49ff568dd88e5db279bb8 Gerrit-Change-Number: 82639 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com>

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[M] Change in coreboot[main]: mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flash
by Krystian Hebel (Code Review) 24 May '24

24 May '24

Attention is currently required from: Krystian Hebel, Michał Kopeć, Michał Żygowski, Patrick Rudolph, Paul Menzel, Sergii Dmytruk. Hello Michał Kopeć, Michał Żygowski, Patrick Rudolph, Sergii Dmytruk, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82555?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+2 by Patrick Rudolph, Verified+1 by build bot (Jenkins) Change subject: mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flash ...................................................................... mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flash Depending on how firmware image was passed to QEMU, it may behave as: - ROM - memory mapped reads, writes are ignored (FW image mounted with '-bios'); - RAM - memory mapped reads and writes (FW image mounted with e.g. '-device loader'); - flash - memory mapped reads, write and erase possible through commands. Contrary to physical flash devices erase is not required before writing, but it also doesn't hurt. Flash may be split into read-only and read-write parts, like OVMF_CODE.fd and OVMF_VARS.fd. Combined size of system firmware must not exceed 8 MiB (FW image(s) mounted with '-drive if=pflash'). This function detects which of the above applies and fills region_device_ops accordingly. Tested by starting QEMU with firmware passed as '-drive if=pflash', '-drive if=pflash,readonly=on' and '-bios'. When started with firmware passed through '-device loader', coreboot complains about corrupted FMAP, but this is the same behavior as without this change: [ERROR] Invalid FMAP at 0x40000 [EMERG] Cannot locate primary CBFS Writable pflash support was added about 17 years ago, so it should be supported by all QEMU versions currently in use. Change-Id: I3ab9f22c6165064a769881d4be5eab13a0a2f519 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/Makefile.mk A src/mainboard/emulation/qemu-i440fx/rom_media.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/Makefile.mk 5 files changed, 204 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/82555/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/82555?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ab9f22c6165064a769881d4be5eab13a0a2f519 Gerrit-Change-Number: 82555 Gerrit-PatchSet: 5 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>

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[XS] Change in coreboot[main]: Makefile: Identify deprecated one-element or zero-length arrays
by Maximilian Brune (Code Review) 24 May '24

24 May '24

Attention is currently required from: Elyes Haouas, Jan Samek, Martin L Roth. Maximilian Brune has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/77147?usp=email ) Change subject: Makefile: Identify deprecated one-element or zero-length arrays ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/77147/comment/4cfa41d9_c5789cff?us… : PS8, Line 11: Use -Wflex-array-member-not-at-end to identify them. > it should, I guess […] If I read that correctly it only mentions to warn about flexible array members that are not at the end, but not about zero-length arrays. -- To view, visit https://review.coreboot.org/c/coreboot/+/77147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib704f7659d3b431ce7eebb4432c5b1a4272de3d2 Gerrit-Change-Number: 77147 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <samekh(a)email.cz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jan Samek <samekh(a)email.cz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 24 May 2024 11:18:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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