coreboot-gerrit May 2024

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[S] Change in coreboot[main]: mb/google/nissa/var/sundance: Adjust the eMMC DLL delay setting accor...
by Paul Menzel (Code Review) 24 May '24

24 May '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Roger Wang, Shou-Chieh Hsu, Subrata Banik. Paul Menzel has posted comments on this change by Roger Wang. ( https://review.coreboot.org/c/coreboot/+/82602?usp=email ) Change subject: mb/google/nissa/var/sundance: Adjust the eMMC DLL delay setting according to Intel's suggestion ...................................................................... Patch Set 12: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82602/comment/9abf8fae_41bc1a6d?us… : PS12, Line 2: Author: roger2.wang <roger2.wang(a)lcfc.corp-partner.google.com> Same comment as in https://review.coreboot.org/c/coreboot/+/82427. https://review.coreboot.org/c/coreboot/+/82602/comment/0fe71ac1_1183c5d8?us… : PS12, Line 7: Adjust the eMMC DLL delay setting according to Intel's suggestion That’s quite long. Maybe: > Tune eMMC DLL delays to support more devices or > Make eMMC DLL delays compatible with more devices https://review.coreboot.org/c/coreboot/+/82602/comment/d1365630_5539c4df?us… : PS12, Line 9: Currently some eMMC can't power on to OS nomally. Please list the problematic eMMC models. https://review.coreboot.org/c/coreboot/+/82602/comment/96eed82c_14cf6484?us… : PS12, Line 9: Use the Intel provides eMMC DLL delay patch to modify some system can't boot to OS problem Please add a dot/period at the end of sentences. Please document, how Intel provided this data. File src/mainboard/google/brya/variants/sundance/overridetree.cb: https://review.coreboot.org/c/coreboot/+/82602/comment/369aa856_08a069e5?us… : PS12, Line 10: register "sagv" = "SaGv_Enabled" Please remove the leading space. https://review.coreboot.org/c/coreboot/+/82602/comment/f647613e_28d2271e?us… : PS12, Line 53: 1(HS400 Mode) Add add space before the (. https://review.coreboot.org/c/coreboot/+/82602/comment/51ba1ed6_bc7e5e49?us… : PS12, Line 12: # EMMC Tx CMD Delay : # Refer to EDS-Vol2-42.3.7. : # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. : # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. : register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" : : # EMMC TX DATA Delay 1 : # Refer to EDS-Vol2-42.3.8. : # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. : # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. : register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" : : # EMMC TX DATA Delay 2 : # Refer to EDS-Vol2-42.3.9. : # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. : # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. : # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. : # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. : register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" : : # EMMC RX CMD/DATA Delay 1 : # Refer to EDS-Vol2-42.3.10. : # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. : # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. : # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. : # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. : register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1A1B" : : # EMMC RX CMD/DATA Delay 2 : # Refer to EDS-Vol2-42.3.12. : # [17:16] stands for Rx Clock before Output Buffer, : # 00: Rx clock after output buffer, : # 01: Rx clock before output buffer, : # 10: Automatic selection based on working mode. : # 11: Reserved : # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. : # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. : register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10028" : : # EMMC Rx Strobe Delay : # Refer to EDS-Vol2-42.3.11. : # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. : # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. : register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" Please remove the leading space before the tab. Also, to save time converting the hex values to timings, could a comment be added, what value was chosen? -- To view, visit https://review.coreboot.org/c/coreboot/+/82602?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57 Gerrit-Change-Number: 82602 Gerrit-PatchSet: 12 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Varshit Pandya <15mece14(a)nirmauni.ac.in> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Fri, 24 May 2024 10:39:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/nissa/var/pujjoga: Update touchscreen IC settings
by Paul Menzel (Code Review) 24 May '24

24 May '24

Attention is currently required from: Dinesh Gehlot, Felix Held, Kapil Porwal, Nick Vaccaro, Roger Wang, Shou-Chieh Hsu, Subrata Banik. Paul Menzel has posted comments on this change by Roger Wang. ( https://review.coreboot.org/c/coreboot/+/82427?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/pujjoga: Update touchscreen IC settings ...................................................................... Patch Set 10: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82427/comment/d62c2b24_2f089146?us… : PS10, Line 2: roger2.wang Use Roger Wang? $ git config --global user.name "Roger Wang" $ git commit --amend --author="Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com>" -s https://review.coreboot.org/c/coreboot/+/82427/comment/c144ed62_7e28b873?us… : PS10, Line 9: remove 3 unused : touchscreens. According to the information provided by the key-part : team. Excuse my ignorance. That means, there were no devices sold with the three removed touchscreens? -- To view, visit https://review.coreboot.org/c/coreboot/+/82427?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e6349e80431aadf27cd72b8439b01f95348071d Gerrit-Change-Number: 82427 Gerrit-PatchSet: 10 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 24 May 2024 10:33:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: libpayload: Add x86_64 (64-bit) support
by Subrata Banik (Code Review) 24 May '24

24 May '24

Attention is currently required from: Arthur Heymans, Julius Werner, Kapil Porwal. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81968?usp=email to look at the new patch set (#76). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: libpayload: Add x86_64 (64-bit) support ...................................................................... libpayload: Add x86_64 (64-bit) support This patch introduces x86_64 (64-bit) support to the payload, building upon the existing x86 (32-bit) architecture. Files necessary for 64-bit compilation are now guarded by the `CONFIG_LP_ARCH_X86_64` Kconfig option. BUG=b:242829490 TEST=Able to verify all valid combinations between coreboot and payload with this patch. Payload Entry Point Behavior with below code. +----------------+--------------------+----------------------------+ | LP_ARCH_X86_64 | Payload Entry Mode | Description | +----------------+--------------------+----------------------------+ | No | 32-bit | Direct protected mode init | +----------------+--------------------+----------------------------+ | Yes | 32-bit | Protected to long mode | +----------------+--------------------+----------------------------+ | Yes | 64-bit | Long mode initialization | +----------------+--------------------+----------------------------+ Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.mk M payloads/libpayload/arch/x86/Makefile.mk M payloads/libpayload/arch/x86/exception.c A payloads/libpayload/arch/x86/exception_asm_64.S R payloads/libpayload/arch/x86/exec.c M payloads/libpayload/arch/x86/gdb.c A payloads/libpayload/arch/x86/head_64.S M payloads/libpayload/arch/x86/libpayload.ldscript A payloads/libpayload/arch/x86/pt.S M payloads/libpayload/arch/x86/string.c M payloads/libpayload/bin/lpgcc M payloads/libpayload/drivers/storage/ahci_common.c M payloads/libpayload/drivers/usb/uhci.c M payloads/libpayload/include/x86/arch/exception.h M payloads/libpayload/libc/Makefile.mk M payloads/libpayload/vboot/Makefile.mk 18 files changed, 686 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/81968/76 -- To view, visit https://review.coreboot.org/c/coreboot/+/81968?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Gerrit-Change-Number: 81968 Gerrit-PatchSet: 76 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[S] Change in coreboot[main]: mb/google/trulo: Refactor gpio pad configuration
by Paul Menzel (Code Review) 24 May '24

24 May '24

Paul Menzel has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/82629?usp=email ) Change subject: mb/google/trulo: Refactor gpio pad configuration ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Nice work! Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/82629?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ab88ac094a45c608cd894feb5eeec24b867527a Gerrit-Change-Number: 82629 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 24 May 2024 10:22:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: security/memory_clear: fix wrong size of reserved memory range
by Paul Menzel (Code Review) 24 May '24

24 May '24

Attention is currently required from: Krystian Hebel, Michał Żygowski. Paul Menzel has posted comments on this change by Krystian Hebel. ( https://review.coreboot.org/c/coreboot/+/82397?usp=email ) Change subject: security/memory_clear: fix wrong size of reserved memory range ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82397/comment/d5d4a6b3_6a26fd4f?us… : PS1, Line 22: Sorry for the late response. Feel free to mark my comments as resolved, when you answer. > Found-by: Sergii … could be added, or > Found by Sergii during code review. -- To view, visit https://review.coreboot.org/c/coreboot/+/82397?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0df15b0d1767196fe70be14d94428ccdf8dbd5d3 Gerrit-Change-Number: 82397 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Fri, 24 May 2024 10:20:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com>

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Drop GPIO by I/O
by Paul Menzel (Code Review) 24 May '24

24 May '24

Attention is currently required from: Fabian Groffen, Felix Held, Keith Hui. Paul Menzel has posted comments on this change by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/75145?usp=email ) Change subject: mb/asus/p8z77-m: Drop GPIO by I/O ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75145?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22654f3c77082bf163ab7000ec467ab7085a0534 Gerrit-Change-Number: 75145 Gerrit-PatchSet: 4 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Comment-Date: Fri, 24 May 2024 10:18:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: sio/nuvoton: Add Kconfig for shared PS/2 port
by Paul Menzel (Code Review) 24 May '24

24 May '24

Attention is currently required from: Keith Hui. Paul Menzel has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82631?usp=email ) Change subject: sio/nuvoton: Add Kconfig for shared PS/2 port ...................................................................... Patch Set 1: (2 comments) File src/superio/nuvoton/common/Kconfig: https://review.coreboot.org/c/coreboot/+/82631/comment/896cc02e_c5cecd93?us… : PS1, Line 15: HAVE_SHARED_PS2_PORT Should this be namespaced, or could it be moved to `src/superio/Kconfig`? https://review.coreboot.org/c/coreboot/+/82631/comment/6d8e552b_9dbebb05?us… : PS1, Line 19: Select this option if your mainboard has a single PS/2 port for both keyboard and : mouse. Add an nvram option to cmos.layout for PS/2 mouse support. Maybe elaborate and use the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/82631?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I156b15c6ba233cbe8b9ba4d2cfbca6836ad7483a Gerrit-Change-Number: 82631 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Fri, 24 May 2024 10:17:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: sio/nuvoton: Add Kconfig for shared PS/2 port
by Paul Menzel (Code Review) 24 May '24

24 May '24

Attention is currently required from: Keith Hui. Paul Menzel has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82631?usp=email ) Change subject: sio/nuvoton: Add Kconfig for shared PS/2 port ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82631/comment/27bdef06_9ab0b4fd?us… : PS1, Line 11: On these boards (where a Y-cable cannot allow both : keyboard and mouse to work off the same port), if a PS/2 keyboard is : not present, SIO should be configured to swap its role to mouse, to : allow the OS to find and initialize any mouse connected. Just to avoid misunderstandings. Using a Y-cable will always get both to work, or is it board dependent if the PS/2 port can support both at the same time? -- To view, visit https://review.coreboot.org/c/coreboot/+/82631?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I156b15c6ba233cbe8b9ba4d2cfbca6836ad7483a Gerrit-Change-Number: 82631 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Fri, 24 May 2024 10:16:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: sio/nuvoton: Implement a common ramstage ACPI LDN helper
by Paul Menzel (Code Review) 24 May '24

24 May '24

Attention is currently required from: Keith Hui. Paul Menzel has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82632?usp=email ) Change subject: sio/nuvoton: Implement a common ramstage ACPI LDN helper ...................................................................... Patch Set 1: Code-Review+1 (3 comments) Patchset: PS1: Great work! File src/superio/nuvoton/common/common.c: https://review.coreboot.org/c/coreboot/+/82632/comment/a2dcd896_4d53d718?us… : PS1, Line 42: /* Set power state after power fail */ : /* Important: Make sure the definitions in mainboard/Kconfig around : * MAINBOARD_POWER_FAILURE_STATE and your board's cmos.layout match. : * And if MAINBOARD_POWER_FAILURE_STATE deviates from the chip's : * expectation (ie. 0=off, 1=on, 2=keep), this code must be adapted. : */ Please use one of the recommended multi-line commenting styles. I’d use: /* * … */ https://review.coreboot.org/c/coreboot/+/82632/comment/cf054ced_6814f205?us… : PS1, Line 55: } else : byte = 0; if one branch has to use {} all branches need to. -- To view, visit https://review.coreboot.org/c/coreboot/+/82632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaddcaa2d77c5b06ddfbb6dbaac00df5e72dd4bd Gerrit-Change-Number: 82632 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Fri, 24 May 2024 10:14:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox: Add romstage early graphics
by Paul Menzel (Code Review) 24 May '24

24 May '24

Attention is currently required from: Ashish Kumar Mishra, Karthik Ramasubramanian, Krishna P Bhat D, Shelley Chen, Sowmya Aralguppe. Paul Menzel has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/81931?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/brox: Add romstage early graphics ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81931/comment/ba1e4d89_55d97bfe?us… : PS10, Line 16: [0m[DEBUG] Boot Count incremented to 21[0m : [0m[INFO ] CBFS: Found 'fspm.bin' @0x90f80 size 0xd0000 in mcache @0xfef89b10[0m : [0m[INFO ] VB2:vb2_digest_init() 851968 bytes, hash algo 2, HW acceleration enabled[0m : [0m[DEBUG] FMAP: area RW_MRC_CACHE found @ f10000 (65536 bytes)[0m : [1m[NOTE ] MRC: no data in 'RW_MRC_CACHE'[0m : [0m[SPEW ] bootmode is set to: 0 (boot with full config)[0m : [0.384818] DP PHY mode status not complete : [0.388911] DP PHY mode status not complete : [0.393197] DP PHY mode status not complete : [0.397484] DP PHY mode status not complete : [0.401771] DP PHY mode status not complete : [0.406057] DP PHY mode status not complete : [0.410345] DP PHY mode status not complete : [0.414632] DP PHY mode status not complete : [0.418916] DP PHY mode status not complete : [0.423203] DP PHY mode status not complete : [0.427491] DP PHY mode status not complete : [0.431777] DP PHY mode status not complete : [0m[INFO ] Informing user on-display of memory training.[0m : [0m[DEBUG] FMAP: area COREBOOT found @ 1877000 (7901184 bytes)[0m : [1;4m[WARN ] CBFS: 'preram_locales' not found.[0m : [7m[ERROR] ux_locales_get_text: preram_locales not found.[0m : [0m[DEBUG] FMAP: area RW_ELOG found @ f20000 (16384 bytes)[0m : [0m[INFO ] ELOG: NV offset 0xf20000 size 0x4000[0m : [0m[INFO ] ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024[0m : Remove the terminal control sequences? -- To view, visit https://review.coreboot.org/c/coreboot/+/81931?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d4795825960bc58f8f7ef494b01aa975f3bc346 Gerrit-Change-Number: 81931 Gerrit-PatchSet: 10 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 24 May 2024 10:11:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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