coreboot-gerrit May 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: libpayload: Add x86_64 (64-bit) support
by Subrata Banik (Code Review) 25 May '24

25 May '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81968?usp=email ) Change subject: libpayload: Add x86_64 (64-bit) support ...................................................................... libpayload: Add x86_64 (64-bit) support This patch introduces x86_64 (64-bit) support to the payload, building upon the existing x86 (32-bit) architecture. Files necessary for 64-bit compilation are now guarded by the `CONFIG_LP_ARCH_X86_64` Kconfig option. BUG=b:242829490 TEST=Able to verify all valid combinations between coreboot and payload with this patch. Payload Entry Point Behavior with below code. +----------------+--------------------+----------------------------+ | LP_ARCH_X86_64 | Payload Entry Mode | Description | +----------------+--------------------+----------------------------+ | No | 32-bit | Direct protected mode init | +----------------+--------------------+----------------------------+ | Yes | 32-bit | Protected to long mode | +----------------+--------------------+----------------------------+ | Yes | 64-bit | Long mode initialization | +----------------+--------------------+----------------------------+ Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81968 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.mk M payloads/libpayload/arch/x86/Makefile.mk M payloads/libpayload/arch/x86/exception.c A payloads/libpayload/arch/x86/exception_asm_64.S R payloads/libpayload/arch/x86/exec.c M payloads/libpayload/arch/x86/gdb.c A payloads/libpayload/arch/x86/head_64.S M payloads/libpayload/arch/x86/libpayload.ldscript A payloads/libpayload/arch/x86/pt.S M payloads/libpayload/arch/x86/string.c M payloads/libpayload/bin/lpgcc M payloads/libpayload/drivers/storage/ahci_common.c M payloads/libpayload/drivers/usb/uhci.c M payloads/libpayload/include/x86/arch/exception.h M payloads/libpayload/libc/Makefile.mk M payloads/libpayload/vboot/Makefile.mk 18 files changed, 686 insertions(+), 58 deletions(-) Approvals: Julius Werner: Looks good to me, approved build bot (Jenkins): Verified diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 39d316b..0c07ecd 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -106,17 +106,22 @@ choice prompt "Target Architecture" - default ARCH_X86 + default ARCH_X86_32 config ARCH_ARM bool "ARM" help Support the ARM architecture -config ARCH_X86 - bool "x86" +config ARCH_X86_32 + bool "x86_32" help - Support the x86 architecture + Support the x86_32 architecture + +config ARCH_X86_64 + bool "x86_64" + help + Support the x86_64 architecture config ARCH_ARM64 bool "ARM64" @@ -133,6 +138,12 @@ endchoice +config ARCH_X86 + bool + default y if ARCH_X86_32 || ARCH_X86_64 + help + Support the x86 architecture + config MULTIBOOT bool "Multiboot header support" depends on ARCH_X86 diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 71d60bc..afe38dc 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -118,7 +118,8 @@ # override here. ARCH-$(CONFIG_LP_ARCH_ARM) := arm ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 -ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 +ARCH-$(CONFIG_LP_ARCH_X86_32) := x86_32 +ARCH-$(CONFIG_LP_ARCH_X86_64) := x86_64 ARCH-$(CONFIG_LP_ARCH_MOCK) := mock # Five cases where we don't need fully populated $(obj) lists: diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk index d654995..d5a9a81 100644 --- a/payloads/libpayload/Makefile.mk +++ b/payloads/libpayload/Makefile.mk @@ -96,7 +96,7 @@ cmp $@ $< 2>/dev/null || cp $< $@ library-targets = $(addsuffix .a,$(addprefix $(obj)/,$(libraries))) $(obj)/libpayload.a -lib: $$(library-targets) +lib: $$(library-targets) $(obj)/libpayload.ldscript extract_nth=$(word $(1), $(subst |, ,$(2))) @@ -115,11 +115,15 @@ printf " AR $(subst $(CURDIR)/,,$(@))\n" printf "create $@\n$(foreach objc,$(filter-out %.a,$^),addmod $(objc)\n)$(foreach lib,$(filter %.a,$^),addlib $(lib)\n)save\nend\n" | $(AR) -M +$(obj)/libpayload.ldscript: arch/$(ARCHDIR-y)/libpayload.ldscript + @printf " LDSCRIPT $@\n" + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -E -P -x assembler-with-cpp -undef -o $@ $< + install: real-target printf " INSTALL $(DESTDIR)/libpayload/lib\n" install -m 755 -d $(DESTDIR)/libpayload/lib install -m 644 $(library-targets) $(DESTDIR)/libpayload/lib/ - install -m 644 arch/$(ARCHDIR-y)/libpayload.ldscript $(DESTDIR)/libpayload/lib/ + install -m 644 $(obj)/libpayload.ldscript $(DESTDIR)/libpayload/lib/ install -m 755 -d $(DESTDIR)/libpayload/lib/$(ARCHDIR-y) printf " INSTALL $(DESTDIR)/libpayload/include\n" install -m 755 -d $(DESTDIR)/libpayload/include diff --git a/payloads/libpayload/arch/x86/Makefile.mk b/payloads/libpayload/arch/x86/Makefile.mk index d2c33b4..35e69cb 100644 --- a/payloads/libpayload/arch/x86/Makefile.mk +++ b/payloads/libpayload/arch/x86/Makefile.mk @@ -27,16 +27,26 @@ ## ifneq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y) +ifeq ($(CONFIG_LP_ARCH_X86_64),y) +CFLAGS += -mpreferred-stack-boundary=4 +else CFLAGS += -mpreferred-stack-boundary=2 endif +endif -libc-y += head.S +libc-$(CONFIG_LP_ARCH_X86_32) += head.S +libc-$(CONFIG_LP_ARCH_X86_64) += head_64.S +libc-$(CONFIG_LP_ARCH_X86_64) += pt.S libc-y += main.c sysinfo.c libc-y += timer.c coreboot.c util.S -libc-y += exec.S virtual.c +libc-y += virtual.c libc-y += selfboot.c cache.c -libc-y += exception_asm.S exception.c +libc-y += exception.c libc-y += delay.c +libc-$(CONFIG_LP_ARCH_X86_32) += exec.c +libc-$(CONFIG_LP_ARCH_X86_32) += exec.S +libc-$(CONFIG_LP_ARCH_X86_32) += exception_asm.S +libc-$(CONFIG_LP_ARCH_X86_64) += exception_asm_64.S # Will fall back to default_memXXX() in libc/memory.c if GPL not allowed. libc-$(CONFIG_LP_GPL) += string.c diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c index 23d1b05..a43a993 100644 --- a/payloads/libpayload/arch/x86/exception.c +++ b/payloads/libpayload/arch/x86/exception.c @@ -34,7 +34,13 @@ #define IF_FLAG (1 << 9) -u32 exception_stack[0x400] __attribute__((aligned(8))); +#if CONFIG(LP_ARCH_X86_64) +#define REGISTER_FMT "0x%016zx" +#else +#define REGISTER_FMT "0x%08zx" +#endif + +u8 exception_stack[0x400] __aligned(16); static interrupt_handler handlers[256]; @@ -143,17 +149,27 @@ break; } printf("\n"); - printf("EIP: 0x%08x\n", exception_state->regs.eip); + printf("REG_IP: " REGISTER_FMT "\n", exception_state->regs.reg_ip); + printf("REG_FLAGS: " REGISTER_FMT "\n", exception_state->regs.reg_flags); + printf("REG_AX: " REGISTER_FMT "\n", exception_state->regs.reg_ax); + printf("REG_BX: " REGISTER_FMT "\n", exception_state->regs.reg_bx); + printf("REG_CX: " REGISTER_FMT "\n", exception_state->regs.reg_cx); + printf("REG_DX: " REGISTER_FMT "\n", exception_state->regs.reg_dx); + printf("REG_SP: " REGISTER_FMT "\n", exception_state->regs.reg_sp); + printf("REG_BP: " REGISTER_FMT "\n", exception_state->regs.reg_bp); + printf("REG_SI: " REGISTER_FMT "\n", exception_state->regs.reg_si); + printf("REG_DI: " REGISTER_FMT "\n", exception_state->regs.reg_di); +#if CONFIG(LP_ARCH_X86_64) + printf("REG_R8: 0x%016zx\n", exception_state->regs.reg_r8); + printf("REG_R9: 0x%016zx\n", exception_state->regs.reg_r9); + printf("REG_R10: 0x%016zx\n", exception_state->regs.reg_r10); + printf("REG_R11: 0x%016zx\n", exception_state->regs.reg_r11); + printf("REG_R12: 0x%016zx\n", exception_state->regs.reg_r12); + printf("REG_R13: 0x%016zx\n", exception_state->regs.reg_r13); + printf("REG_R14: 0x%016zx\n", exception_state->regs.reg_r14); + printf("REG_R15: 0x%016zx\n", exception_state->regs.reg_r15); +#endif printf("CS: 0x%04x\n", exception_state->regs.cs); - printf("EFLAGS: 0x%08x\n", exception_state->regs.eflags); - printf("EAX: 0x%08x\n", exception_state->regs.eax); - printf("ECX: 0x%08x\n", exception_state->regs.ecx); - printf("EDX: 0x%08x\n", exception_state->regs.edx); - printf("EBX: 0x%08x\n", exception_state->regs.ebx); - printf("ESP: 0x%08x\n", exception_state->regs.esp); - printf("EBP: 0x%08x\n", exception_state->regs.ebp); - printf("ESI: 0x%08x\n", exception_state->regs.esi); - printf("EDI: 0x%08x\n", exception_state->regs.edi); printf("DS: 0x%04x\n", exception_state->regs.ds); printf("ES: 0x%04x\n", exception_state->regs.es); printf("SS: 0x%04x\n", exception_state->regs.ss); @@ -164,7 +180,7 @@ void exception_dispatch(void) { die_if(exception_state->vector >= ARRAY_SIZE(handlers), - "Invalid vector %u\n", exception_state->vector); + "Invalid vector %zu\n", exception_state->vector); u8 vec = exception_state->vector; @@ -184,7 +200,7 @@ vec); dump_exception_state(); - dump_stack(exception_state->regs.esp, 512); + dump_stack(exception_state->regs.reg_sp, 512); /* We don't call apic_eoi because we don't want to ack the interrupt and allow another interrupt to wake the processor. */ halt(); @@ -197,6 +213,10 @@ void exception_init(void) { + /* TODO: Add exception init code for x64, currently only supporting 32-bit code */ + if (CONFIG(LP_ARCH_X86_64)) + return; + exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack); exception_init_asm(); } @@ -206,6 +226,17 @@ handlers[vector] = handler; } +#if CONFIG(LP_ARCH_X86_64) +static uint64_t eflags(void) +{ + uint64_t eflags; + asm volatile( + "pushfq\n\t" + "popq %0\n\t" + : "=rm" (eflags)); + return eflags; +} +#else static uint32_t eflags(void) { uint32_t eflags; @@ -215,6 +246,7 @@ : "=rm" (eflags)); return eflags; } +#endif void enable_interrupts(void) { diff --git a/payloads/libpayload/arch/x86/exception_asm_64.S b/payloads/libpayload/arch/x86/exception_asm_64.S new file mode 100644 index 0000000..ee4e9e5 --- /dev/null +++ b/payloads/libpayload/arch/x86/exception_asm_64.S @@ -0,0 +1,221 @@ +/* + * + * Copyright 2024 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + .align 16 + .global exception_stack_end +exception_stack_end: + .quad 0 + .global exception_state +exception_state: + .quad 0 + +/* Some temporary variables which are used while saving exception state. */ +vector: + .quad 0 +error_code: + .quad 0 +old_rsp: + .quad 0 +old_rax: + .quad 0 + + .align 16 + +/* + * Each exception vector has a small stub associated with it which sets aside + * the error code, if any, records which vector we entered from, and calls + * the common exception entry point. Some exceptions have error codes and some + * don't, so we have a macro for each type. + */ + + .macro stub num +exception_stub_\num: + movq $0, error_code + movq $\num, vector + jmp exception_common + .endm + + .macro stub_err num +exception_stub_\num: + pop error_code + movq $\num, vector + jmp exception_common + .endm + + .altmacro + .macro user_defined_stubs from, to + stub \from + .if \to-\from + user_defined_stubs %(from+1),\to + .endif + .endm + + stub 0 + stub 1 + stub 2 + stub 3 + stub 4 + stub 5 + stub 6 + stub 7 + stub_err 8 + stub 9 + stub_err 10 + stub_err 11 + stub_err 12 + stub_err 13 + stub_err 14 + stub 15 + stub 16 + stub_err 17 + stub 18 + stub 19 + stub 20 + stub 21 + stub 22 + stub 23 + stub 24 + stub 25 + stub 26 + stub 27 + stub 28 + stub 29 + stub_err 30 + stub 31 + /* Split the macro so we avoid a stack overflow. */ + user_defined_stubs 32, 63 + user_defined_stubs 64, 127 + user_defined_stubs 128, 191 + user_defined_stubs 192, 255 + +exception_common: + + /* Return from the exception. */ + iretl + +/* + * We need segment selectors for the IDT, so we need to know where things are + * in the GDT. We set one up here which is pretty standard and largely copied + * from coreboot. + */ + .align 16 +gdt: + /* selgdt 0, unused */ + .word 0x0000, 0x0000 + .byte 0x00, 0x00, 0x00, 0x00 + + /* selgdt 8, unused */ + .word 0x0000, 0x0000 + .byte 0x00, 0x00, 0x00, 0x00 + + /* selgdt 0x10, flat 4GB code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 + + /* selgdt 0x18, flat 4GB data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x92, 0xcf, 0x00 + + /* selgdt 0x20, flat x64 code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 +gdt_end: + +/* GDT pointer for use with lgdt */ +.global gdt_ptr +gdt_ptr: + .word gdt_end - gdt - 1 + .quad gdt + + /* + * Record the target and construct the actual entry at init time. This + * is necessary because the linker doesn't want to construct the entry + * for us. + */ + .macro interrupt_gate target + .quad \target + .quad \target + .endm + + .altmacro + .macro user_defined_gates from, to + interrupt_gate exception_stub_\from + .if \to-\from + user_defined_gates %(from+1),\to + .endif + .endm + + .align 16 + .global idt +idt: + interrupt_gate exception_stub_0 + interrupt_gate exception_stub_1 + interrupt_gate exception_stub_2 + interrupt_gate exception_stub_3 + interrupt_gate exception_stub_4 + interrupt_gate exception_stub_5 + interrupt_gate exception_stub_6 + interrupt_gate exception_stub_7 + interrupt_gate exception_stub_8 + interrupt_gate exception_stub_9 + interrupt_gate exception_stub_10 + interrupt_gate exception_stub_11 + interrupt_gate exception_stub_12 + interrupt_gate exception_stub_13 + interrupt_gate exception_stub_14 + interrupt_gate exception_stub_15 + interrupt_gate exception_stub_16 + interrupt_gate exception_stub_17 + interrupt_gate exception_stub_18 + interrupt_gate exception_stub_19 + interrupt_gate exception_stub_20 + interrupt_gate exception_stub_21 + interrupt_gate exception_stub_22 + interrupt_gate exception_stub_23 + interrupt_gate exception_stub_24 + interrupt_gate exception_stub_25 + interrupt_gate exception_stub_26 + interrupt_gate exception_stub_27 + interrupt_gate exception_stub_28 + interrupt_gate exception_stub_29 + interrupt_gate exception_stub_30 + interrupt_gate exception_stub_31 + user_defined_gates 32, 63 + user_defined_gates 64, 127 + user_defined_gates 128, 191 + user_defined_gates 192, 255 +idt_end: + +/* IDT pointer for use with lidt */ +idt_ptr: + .word idt_end - idt - 1 + .quad idt + + .global exception_init_asm +exception_init_asm: + ret diff --git a/payloads/libpayload/libc/exec.c b/payloads/libpayload/arch/x86/exec.c similarity index 94% rename from payloads/libpayload/libc/exec.c rename to payloads/libpayload/arch/x86/exec.c index ae75a3e..06a5ed2 100644 --- a/payloads/libpayload/libc/exec.c +++ b/payloads/libpayload/arch/x86/exec.c @@ -29,8 +29,10 @@ #include <libpayload-config.h> #include <libpayload.h> -#if CONFIG(LP_ARCH_X86) +#if CONFIG(LP_ARCH_X86_32) extern void i386_do_exec(long addr, int argc, char **argv, int *ret); +#else +#error "exec does not currently support x86_64." #endif /** @@ -45,7 +47,7 @@ { int val = -1; -#if CONFIG(LP_ARCH_X86) +#if CONFIG(LP_ARCH_X86_32) i386_do_exec(addr, argc, argv, &val); #endif return val; diff --git a/payloads/libpayload/arch/x86/gdb.c b/payloads/libpayload/arch/x86/gdb.c index 7d29512..ad249b8 100644 --- a/payloads/libpayload/arch/x86/gdb.c +++ b/payloads/libpayload/arch/x86/gdb.c @@ -15,6 +15,7 @@ #include <exception.h> #include <gdb.h> #include <libpayload.h> +#include <stddef.h> static const u8 type_to_signal[] = { [EXC_DE] = GDB_SIGFPE, @@ -53,12 +54,15 @@ void gdb_arch_enter(void) { - u32 *esp; - - asm volatile ("mov %%esp, %0" : "=r"(esp) ); + u8 *stack_pointer; +#if CONFIG(LP_ARCH_X86_64) + asm volatile ("movq %%rsp, %0" : "=r"(stack_pointer)); +#else + asm volatile ("mov %%esp, %0" : "=r"(stack_pointer)); +#endif /* Avoid reentrant exceptions, just call the hook if in one already. */ - if (esp >= exception_stack && esp <= exception_stack_end) + if (stack_pointer >= exception_stack && stack_pointer <= exception_stack_end) gdb_exception_hook(EXC_BP); else asm volatile ("int3"); @@ -66,12 +70,12 @@ int gdb_arch_set_single_step(int on) { - const u32 tf_bit = 1 << 8; + const size_t tf_bit = 1 << 8; if (on) - exception_state->regs.eflags |= tf_bit; + exception_state->regs.reg_flags |= tf_bit; else - exception_state->regs.eflags &= ~tf_bit; + exception_state->regs.reg_flags &= ~tf_bit; return 0; } diff --git a/payloads/libpayload/arch/x86/head_64.S b/payloads/libpayload/arch/x86/head_64.S new file mode 100644 index 0000000..6524274 --- /dev/null +++ b/payloads/libpayload/arch/x86/head_64.S @@ -0,0 +1,141 @@ +/* + * + * Copyright (C) 2024 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define IA32_EFER 0xC0000080 +#define EFER_LME (1 << 8) + + .code32 + .global _entry + .section .text._entry + .align 4 + +/* + * WARNING: Critical Code Section - 32/64-bit Compatibility + * This code between `_entry` and `jnz _init64` is executed during system initialization. + * It MUST function correctly regardless of whether the system is booting in: + * - 32-bit protected mode + * - 64-bit long mode + * To achieve this, ONLY use instructions that produce identical binary output in both modes. + * Thoroughly test ALL modifications to this section in BOTH 32-bit and 64-bit boot + * environments. + */ + +_entry: + + /* Add multiboot header and jump around it when building with multiboot support. */ +#if CONFIG(LP_MULTIBOOT) + #include "multiboot_header.inc" +#endif + /* No interrupts, please. */ + cli + + movl $IA32_EFER, %ecx + rdmsr + testl $EFER_LME, %eax + jnz _init64 + + lgdt %cs:gdt_ptr + + /* save pointer to coreboot tables */ + movl 4(%esp), %eax + /* + * NOTE: coreboot tables has passed over the top of the stack + * while calling in protected mode. + */ + movl %eax, cb_header_ptr + + call init_page_table + movl $pm4le, %eax + + /* load identity mapped page tables */ + movl %eax, %cr3 + + /* enable PAE */ + movl %cr4, %eax + btsl $5, %eax + movl %eax, %cr4 + + /* enable long mode */ + movl $(IA32_EFER), %ecx + rdmsr + btsl $8, %eax + wrmsr + + /* enable paging */ + movl %cr0, %eax + btsl $31, %eax + movl %eax, %cr0 + + /* Jump to selgdt 0x20, flat x64 code segment */ + ljmp $0x20, $_entry64 + +.code64 +.align 16 +_init64: + movabs $gdt_ptr, %rax + lgdt (%rax) + + /* + * Note: The `cb_header_ptr` has passed as the first argument + * to the x86-64 calling convention. + */ + movq %rdi, cb_header_ptr + + call init_page_table + movq $pm4le, %rax + + /* load identity mapped page tables */ + movq %rax, %cr3 + +_entry64: + /* Store current stack pointer and set up new stack. */ + movq %rsp, %rax + movabs $_estack, %rsp + + push %rax + + fninit + movq %cr0, %rax + andq $0xFFFFFFFFFFFFFFFB, %rax /* clear EM */ + orq $0x00000022, %rax /* set MP, NE */ + movq %rax, %cr0 + + movq %cr4, %rax + orq $0x00000600, %rax /* set OSFXSR, OSXMMEXCPT */ + movq %rax, %cr4 + + /* Let's rock. */ + call start_main + + /* %rax has the return value - pass it on unmolested */ +_leave: + /* Restore old stack. */ + pop %rsp + + /* Return to the original context. */ + ret diff --git a/payloads/libpayload/arch/x86/libpayload.ldscript b/payloads/libpayload/arch/x86/libpayload.ldscript index 0f27ed9..49c7e37 100644 --- a/payloads/libpayload/arch/x86/libpayload.ldscript +++ b/payloads/libpayload/arch/x86/libpayload.ldscript @@ -26,8 +26,13 @@ * SUCH DAMAGE. */ +#if CONFIG(LP_ARCH_X86_64) +OUTPUT_FORMAT(elf64-x86-64) +OUTPUT_ARCH(x86_64) +#else OUTPUT_FORMAT(elf32-i386) OUTPUT_ARCH(i386) +#endif ENTRY(_entry) diff --git a/payloads/libpayload/arch/x86/pt.S b/payloads/libpayload/arch/x86/pt.S new file mode 100644 index 0000000..9b085e5 --- /dev/null +++ b/payloads/libpayload/arch/x86/pt.S @@ -0,0 +1,149 @@ +/* + * + * Copyright 2024 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * For reference see "AMD64 Architecture Programmer's Manual Volume 2", + * Document 24593-Rev. 3.31-July 2019 Chapter 5.3.4 + * + * Page table attributes: WB, User+Supervisor, Present, Writeable, Accessed, Dirty + */ + +.section .bss +#define _PRES (1ULL << 0) +#define _RW (1ULL << 1) +#define _US (1ULL << 2) +#define _A (1ULL << 5) +#define _D (1ULL << 6) +#define _PS (1ULL << 7) + +.section .bss.pm4le +.global pm4le +.align 4096 +pm4le: +.skip 8 + +.section .bss.main_page_table +.global main_page_table +.align 4096 +main_page_table: +.skip 8192 + +.section .bss.extra_page_table +.global extra_page_table +.align 4096 +extra_page_table: +.skip 32 + +/* + * WARNING: 32-bit/64-bit Mode Compatibility for Page Table Initialization + * This `init_page_table` function is designed to work in both 32-bit protected + * mode AND 64-bit long mode. + * + * Key Considerations: + * - Assembly Instructions: Use ONLY instructions that have the SAME binary representation + * in both 32-bit and 64-bit modes. + * - `.code64` Directive: We're compiling with `.code64` to ensure the assembler uses + * the correct 64-bit version of instructions (e.g., `inc`). + * - Register Notation: + * - Use 64-bit register names (like `%rsi`) for register-indirect addressing to avoid + * incorrect address size prefixes. + * - It's safe to use `%esi` with `mov` instructions, as the high 32 bits are zeroed + * in 64-bit mode. + * + * IMPORTANT: + * Thoroughly test ANY changes to this function in BOTH 32-bit and 64-bit boot environments. + */ + +.code64 +.section .text.init_page_table +.globl init_page_table +.type init_page_table, @function + +init_page_table: + mov $0x80000001, %eax + cpuid + test $(1 << 26), %edx + jnz setup_1gb + +setup_2mb: + mov $2048, %edi + mov $(_PRES + _RW + _US + _PS + _A + _D), %eax + mov $0, %ecx + mov $main_page_table, %esi + +loop_2mb: + mov %eax, (%rsi, %rcx, 8) + mov $0, 4(%rsi, %rcx, 8) + add $0x200000, %eax + inc %ecx + cmp %edi, %ecx + jb loop_2mb + + mov $4, %edi + mov $main_page_table, %eax + add $(_PRES + _RW + _US + _A), %eax + mov $0, %ecx + mov $extra_page_table, %esi + +fill_extra_page_table: + mov %eax, (%rsi, %rcx, 8) + mov $0, 4(%rsi, %rcx, 8) + add $4096, %eax + inc %ecx + cmp %edi, %ecx + jb fill_extra_page_table + + mov $extra_page_table, %eax + jmp leave + +setup_1gb: + mov $512, %edi + mov $(_PRES + _RW + _US + _PS + _A + _D), %eax + mov $0, %ebx + mov $0, %ecx + mov $main_page_table, %esi + +loop_1gb: + mov %eax, (%rsi, %rcx, 8) + mov %ebx, 4(%rsi, %rcx, 8) + add $0x40000000, %eax + cmp $0x40000000, %eax + ja no_overflow_1gb + inc %ebx +no_overflow_1gb: + inc %ecx + cmp %edi, %ecx + jb loop_1gb + + mov $main_page_table, %eax + +leave: + or $(_PRES + _RW + _US + _A), %eax + mov %eax, pm4le + + ret diff --git a/payloads/libpayload/arch/x86/string.c b/payloads/libpayload/arch/x86/string.c index 836d049..11bcae7 100644 --- a/payloads/libpayload/arch/x86/string.c +++ b/payloads/libpayload/arch/x86/string.c @@ -81,6 +81,16 @@ { unsigned long d0, d1, d2; +#if CONFIG(LP_ARCH_X86_64) + asm volatile( + "rep ; movsq\n\t" + "mov %4,%%rcx\n\t" + "rep ; movsb\n\t" + : "=&c" (d0), "=&D" (d1), "=&S" (d2) + : "0" (n >> 3), "g" (n & 7), "1" (dest), "2" (src) + : "memory" + ); +#else asm volatile( "rep ; movsl\n\t" "movl %4,%%ecx\n\t" @@ -89,6 +99,7 @@ : "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src) : "memory" ); +#endif return dest; } diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index a954d4f..08fcc29 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -84,7 +84,11 @@ fi if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then _ARCHDIR=x86 - _ARCHEXTRA="-m32 " + if [ "$CONFIG_LP_ARCH_X86_32" = "y" ]; then + _ARCHEXTRA="-m32 " + else + _ARCHEXTRA="-m64 " + fi fi if [ "$CONFIG_LP_ARCH_MOCK" = "y" ]; then _ARCHDIR=mock @@ -122,13 +126,10 @@ while [ $# -gt 0 ]; do case $1 in - -m32|-fno-stack-protector) + -m32|-fno-stack-protector|-m64) shift continue ;; - -m64) - error "Invalid option --64 - only 32 bit architectures are supported" - ;; -c) DOLINK=0 ;; diff --git a/payloads/libpayload/drivers/storage/ahci_common.c b/payloads/libpayload/drivers/storage/ahci_common.c index f3abc5f..abc67c3 100644 --- a/payloads/libpayload/drivers/storage/ahci_common.c +++ b/payloads/libpayload/drivers/storage/ahci_common.c @@ -66,7 +66,7 @@ u8 *const user_buf, const size_t len, const int out) { - if ((u32)user_buf & 1) { + if ((uintptr_t)user_buf & 1) { printf("ahci: Odd buffer pointer (%p).\n", user_buf); if (dev->buf) /* orphaned buffer */ free(dev->buf - *(dev->buf - 1)); @@ -76,7 +76,7 @@ dev->user_buf = user_buf; dev->write_back = !out; dev->buflen = len; - if ((u32)dev->buf & 1) { + if ((uintptr_t)dev->buf & 1) { dev->buf[0] = 1; dev->buf += 1; } else { diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index eb252cd..7590ab3 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -274,7 +274,7 @@ #define UHCI_SLEEP_TIME_US 30 #define UHCI_TIMEOUT (USB_MAX_PROCESSING_TIME_US / UHCI_SLEEP_TIME_US) -#define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf)) +#define GET_TD(x) ((void *)(((unsigned long)(x))&~0xf)) static td_t * wait_for_completed_qh(hci_t *controller, qh_t *qh) diff --git a/payloads/libpayload/include/x86/arch/exception.h b/payloads/libpayload/include/x86/arch/exception.h index d88029b..76099f2 100644 --- a/payloads/libpayload/include/x86/arch/exception.h +++ b/payloads/libpayload/include/x86/arch/exception.h @@ -29,6 +29,7 @@ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H +#include <stddef.h> #include <stdint.h> void exception_init_asm(void); @@ -38,20 +39,28 @@ /** Returns 1 if interrupts are enabled. */ int interrupts_enabled(void); -struct exception_state -{ +#if CONFIG(LP_ARCH_X86_64) +struct exception_state { /* Careful: x86/gdb.c currently relies on the size and order of regs. */ struct { - u32 eax; - u32 ecx; - u32 edx; - u32 ebx; - u32 esp; - u32 ebp; - u32 esi; - u32 edi; - u32 eip; - u32 eflags; + size_t reg_ax; + size_t reg_bx; + size_t reg_cx; + size_t reg_dx; + size_t reg_si; + size_t reg_di; + size_t reg_bp; + size_t reg_sp; + size_t reg_r8; + size_t reg_r9; + size_t reg_r10; + size_t reg_r11; + size_t reg_r12; + size_t reg_r13; + size_t reg_r14; + size_t reg_r15; + size_t reg_ip; + size_t reg_flags; u32 cs; u32 ss; u32 ds; @@ -59,13 +68,39 @@ u32 fs; u32 gs; } regs; - u32 error_code; - u32 vector; + size_t error_code; + size_t vector; } __packed; +#else +struct exception_state { + /* Careful: x86/gdb.c currently relies on the size and order of regs. */ + struct { + size_t reg_ax; + size_t reg_cx; + size_t reg_dx; + size_t reg_bx; + size_t reg_sp; + size_t reg_bp; + size_t reg_si; + size_t reg_di; + size_t reg_ip; + size_t reg_flags; + u32 cs; + u32 ss; + u32 ds; + u32 es; + u32 fs; + u32 gs; + } regs; + size_t error_code; + size_t vector; +} __packed; +#endif + extern struct exception_state *exception_state; -extern u32 exception_stack[]; -extern u32 *exception_stack_end; +extern u8 exception_stack[]; +extern u8 *exception_stack_end; enum { EXC_DE = 0, /* Divide by zero */ diff --git a/payloads/libpayload/libc/Makefile.mk b/payloads/libpayload/libc/Makefile.mk index 2840476..c9fc17a 100644 --- a/payloads/libpayload/libc/Makefile.mk +++ b/payloads/libpayload/libc/Makefile.mk @@ -29,7 +29,7 @@ libc-$(CONFIG_LP_LIBC) += malloc.c printf.c console.c string.c libc-$(CONFIG_LP_LIBC) += memory.c ctype.c lib.c libgcc.c -libc-$(CONFIG_LP_LIBC) += rand.c time.c exec.c +libc-$(CONFIG_LP_LIBC) += rand.c time.c libc-$(CONFIG_LP_LIBC) += readline.c getopt_long.c sysinfo.c libc-$(CONFIG_LP_LIBC) += args.c libc-$(CONFIG_LP_LIBC) += strlcpy.c diff --git a/payloads/libpayload/vboot/Makefile.mk b/payloads/libpayload/vboot/Makefile.mk index 554fec8..15af980 100644 --- a/payloads/libpayload/vboot/Makefile.mk +++ b/payloads/libpayload/vboot/Makefile.mk @@ -15,7 +15,8 @@ $(filter-out -I$(coreboottop)/%,$(1))))) VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM) := arm -VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86) := x86 +VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86_32) := x86 +VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86_64) := x86_64 VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 ifneq ($(CONFIG_LP_ARCH_MOCK),) -- To view, visit https://review.coreboot.org/c/coreboot/+/81968?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Gerrit-Change-Number: 81968 Gerrit-PatchSet: 78 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com>

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[M] Change in coreboot[main]: nb/sandybridge,sb/bd82x6x: Configure USB from southbridge
by Keith Hui (Code Review) 25 May '24

25 May '24

Attention is currently required from: Angel Pons, Keith Hui, Patrick Rudolph. Hello Angel Pons, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81881?usp=email to look at the new patch set (#5). Change subject: nb/sandybridge,sb/bd82x6x: Configure USB from southbridge ...................................................................... nb/sandybridge,sb/bd82x6x: Configure USB from southbridge Transfer all USB responsibilities to southbridge/intel/bd82x6x, using one set of USB port configurations supplied by mainboards in the southbridge section of their devicetree. For MRC raminit, export southbridge_fill_pei_data() as a hook for southbridge code to implement. With new code via this hook, bd82x6x fills pei_data based on this one set of USB port config. For native raminit, early_usb_init() now goes directly to the devicetree and no longer get passed an address to it. TEST=abuild passes for all affected boards. All USB ports still work on asus/p8x7x-series/v/p8z77-m. Change-Id: I38378c7ee0701abc434b030dd97873f2af63e6b0 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/sandybridge/pei_data.h M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/bd82x6x/pch.h 6 files changed, 59 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81881/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I38378c7ee0701abc434b030dd97873f2af63e6b0 Gerrit-Change-Number: 81881 Gerrit-PatchSet: 5 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

1 0

[M] Change in coreboot[main]: util/autoport: Update for two recent USB developments
by Keith Hui (Code Review) 25 May '24

25 May '24

Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82656?usp=email ) Change subject: util/autoport: Update for two recent USB developments ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Besides CB:81881 and CB:82665 which is part of this train, it also carries part of CB:82405. Make sure to get all 3 patches in before committing this one. -- To view, visit https://review.coreboot.org/c/coreboot/+/82656?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b8f44d9de19a7446e2fbcbce1aab6ec6583ebe3 Gerrit-Change-Number: 82656 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sat, 25 May 2024 23:52:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: util/autoport: Update for two recent USB developments
by Keith Hui (Code Review) 25 May '24

25 May '24

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82656?usp=email ) Change subject: util/autoport: Update for two recent USB developments ...................................................................... util/autoport: Update for two recent USB developments Update autoport for: 1. Commit xxxxxxxxxxxx ("nb/sandybridge,sb/bd82x6x: Configure USB from southbridge") 2. Commit xxxxxxxxxxxx ("sb/intel/bd82x6x: Allow actual USBIRx values in devicetree") As a side effect of #2 above, no more FIXME comment (which was broken anyway) will be written for usb_port_config. Change-Id: I3b8f44d9de19a7446e2fbcbce1aab6ec6583ebe3 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M util/autoport/bd82x6x.go 1 file changed, 39 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/82656/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 76411e7..fdb40d8 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -271,37 +271,7 @@ cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4]) } - PutPCIChip(addr, cur) - PutPCIDevParent(addr, "", "lpc") - - DSDTIncludes = append(DSDTIncludes, DSDTInclude{ - File: "southbridge/intel/common/acpi/platform.asl", - }) - DSDTIncludes = append(DSDTIncludes, DSDTInclude{ - File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", - }) - DSDTIncludes = append(DSDTIncludes, DSDTInclude{ - File: "southbridge/intel/common/acpi/sleepstates.asl", - }) - DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ - File: "southbridge/intel/bd82x6x/acpi/pch.asl", - }) - - AddBootBlockFile("early_init.c", "") - AddROMStageFile("early_init.c", "") - - sb := Create(ctx, "early_init.c") - defer sb.Close() - Add_gpl(sb) - - sb.WriteString(` -#include <bootblock_common.h> -#include <device/pci_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/bd82x6x/pch.h> - -`) - sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n") + usbPortConfig := "{\n" currentMap := map[uint32]int{ 0x20000153: 0, @@ -332,19 +302,48 @@ } } current, ok := currentMap[inteltool.RCBA[uint16(0x3500+4*port)]] - comment := "" if !ok { - comment = fmt.Sprintf("// FIXME: Unknown current: RCBA(0x%x)=0x%x", 0x3500+4*port, uint16(0x3500+4*port)) + usbPortConfig += fmt.Sprintf("\t\t\t\t{%d, 0x%x, %d},\n", + ((inteltool.RCBA[0x359c]>>port)&1)^1, + inteltool.RCBA[uint16(0x3500+4*port)] & 0xfff, + OCPin) + } else { + usbPortConfig += fmt.Sprintf("\t\t\t\t{%d, %d, %d},\n", + ((inteltool.RCBA[0x359c]>>port)&1)^1, + current, + OCPin) } - fmt.Fprintf(sb, "\t{ %d, %d, %d }, %s\n", - ((inteltool.RCBA[0x359c]>>port)&1)^1, - current, - OCPin, - comment) } - sb.WriteString("};\n") + usbPortConfig += "\t\t\t}" + cur.Registers["usb_port_config"] = usbPortConfig - guessedMap := GuessSPDMap(ctx) + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/common/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/common/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/pch.asl", + }) + + AddBootBlockFile("early_init.c", "") + AddROMStageFile("early_init.c", "") + + sb := Create(ctx, "early_init.c") + defer sb.Close() + Add_gpl(sb) + + sb.WriteString(` +#include <bootblock_common.h> +#include <device/pci_ops.h> +`) sb.WriteString(` void bootblock_mainboard_early_init(void) @@ -354,15 +353,6 @@ RestorePCI16Simple(sb, addr, 0x80) - sb.WriteString(`} - -/* FIXME: Put proper SPD map here. */ -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ -`) - for i, spd := range guessedMap { - fmt.Fprintf(sb, "\tread_spd(&spd[%d], 0x%02x, id_only);\n", i, spd) - } sb.WriteString("}\n") gnvs := Create(ctx, "acpi_tables.c") -- To view, visit https://review.coreboot.org/c/coreboot/+/82656?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b8f44d9de19a7446e2fbcbce1aab6ec6583ebe3 Gerrit-Change-Number: 82656 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Allow actual USBIRx values in devicetree
by Keith Hui (Code Review) 25 May '24

25 May '24

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82655?usp=email ) Change subject: sb/intel/bd82x6x: Allow actual USBIRx values in devicetree ...................................................................... sb/intel/bd82x6x: Allow actual USBIRx values in devicetree The need to update the USB current mapping in early_usb.c, whenever we see a previously unaccounted for value, is getting out of hand. Instead this patch will allow specifying those values, presumably taken from an inteltool dump while running vendor firmware, directly in the devicetree. Runtime code caps these values to 12 bits and turn them into the 0x20000yyy format the USBIRx registers want. We have more than enough space in the USB port config structure for this. This also opens the future possibility of using the map for a simpler mapping for boards also using MRC. Change-Id: I3d79b33bac742faa9bd4fc9852aff73fe326de4e Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_usb.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/82655/1 diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 7776994..3bf9ab2 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -17,6 +17,8 @@ /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, }; + /* Care should be taken to limit this array to not more than 80 (0x50) entries. + * See below. */ const u32 currents[] = { USBIR_TXRX_GAIN_MOBILE_LOW, USBIR_TXRX_GAIN_DEFAULT, USBIR_TXRX_GAIN_HIGH, 0x20000f51, 0x2000094a, 0x2000035f, USBIR_TXRX_GAIN_DESKTOP_LOW, 0x20000357, 0x20000353, @@ -33,6 +35,14 @@ write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN); for (i = 0; i < 14; i++) { + /* + * If the value from devicetree is beyond the highest possible current map + * index, it is meant to go directly into (bottom 12 bits of) USBIRx. + */ + if (portmap[i].current >= ARRAY_SIZE(currents)) { + RCBA32(USBIR0 + 4 * i) = 0x20000000 | (portmap[i].current & 0xfff); + continue; + } if (portmap[i].enabled && !pch_is_mobile() && currents[portmap[i].current] == USBIR_TXRX_GAIN_MOBILE_LOW) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/82655?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d79b33bac742faa9bd4fc9852aff73fe326de4e Gerrit-Change-Number: 82655 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: mb/razer/blade_stealth_kbl: Add H3Q variant
by Felix Singer (Code Review) 25 May '24

25 May '24

Attention is currently required from: Paul Menzel, Reagan. Felix Singer has posted comments on this change by Reagan. ( https://review.coreboot.org/c/coreboot/+/82506?usp=email ) Change subject: mb/razer/blade_stealth_kbl: Add H3Q variant ...................................................................... Patch Set 6: (2 comments) File src/mainboard/razer/blade_stealth_kbl/variants/h2u/overridetree.cb: PS6: Add missing SPDX license identifier. File src/mainboard/razer/blade_stealth_kbl/variants/h3q/overridetree.cb: PS6: Add missing SPDX license identifier. -- To view, visit https://review.coreboot.org/c/coreboot/+/82506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4 Gerrit-Change-Number: 82506 Gerrit-PatchSet: 6 Gerrit-Owner: Reagan <xbjfk.github(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reagan <xbjfk.github(a)gmail.com> Gerrit-Comment-Date: Sat, 25 May 2024 21:14:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM
by Felix Singer (Code Review) 25 May '24

25 May '24

Attention is currently required from: Angel Pons, Fabian Meyer, Paul Menzel. Felix Singer has posted comments on this change by Fabian Meyer. ( https://review.coreboot.org/c/coreboot/+/82203?usp=email ) Change subject: mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM ...................................................................... Patch Set 9: (6 comments) Patchset: PS9: Would you be interested in listed as a maintainer for this mainboard? If so, please add an entry to the MAINTAINERS file as well. File src/mainboard/asrock/spc741d8/Kconfig: PS9: Missing SPDX license identifier https://review.coreboot.org/c/coreboot/+/82203/comment/2e61827c_872ca6dc?us… : PS9, Line 37: config DEBUG_SMI : d Is it needed to enable that by default? File src/mainboard/asrock/spc741d8/Kconfig.name: PS9: Missing SPDX license identifier File src/mainboard/asrock/spc741d8/Makefile.mk: https://review.coreboot.org/c/coreboot/+/82203/comment/88bb0555_21c767ca?us… : PS9, Line 5: romstage-y += util.c Just a thought.. There's only one function in it, which is guarded by PP condition. You could let the build system decide if the file should be even compiled in or not, I guess. ```suggestion romstage-$(SOC_INTEL_HAS_CXL) += util.c ``` https://review.coreboot.org/c/coreboot/+/82203/comment/4023a003_72606dde?us… : PS9, Line 7: ramstage-y += util.c Same here. ```suggestion ramstage-$(SOC_INTEL_HAS_CXL) += util.c ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/82203?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84b170669873f1a168ea2b7e3be1d6071e811fa5 Gerrit-Change-Number: 82203 Gerrit-PatchSet: 9 Gerrit-Owner: Fabian Meyer <fabian(a)meyfa.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fabian Meyer <fabian(a)meyfa.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 25 May 2024 21:12:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: device_tree: Add function to get top of memory from a FDT blob
by Alper Nebi Yasak (Code Review) 25 May '24

25 May '24

Attention is currently required from: Alper Nebi Yasak, Julius Werner, Maximilian Brune, Nico Huber. Hello Julius Werner, Maximilian Brune, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80322?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: device_tree: Add function to get top of memory from a FDT blob ...................................................................... device_tree: Add function to get top of memory from a FDT blob coreboot needs to figure out top of memory to place CBMEM data. On some non-x86 QEMU virtual machines, this is achieved by probing the RAM space to find where the VM starts discarding data since it's not backed by actual RAM. This behaviour seems to have changed on the QEMU side since then, VMs using the "virt" model have started raising exceptions/errors instead of silently discarding data (likely [1] for example) which has previously broken coreboot on these emulation boards. The qemu-aarch64 and qemu-riscv mainboards are intended for the "virt" models and had this issue, which were mostly fixed by using exception handlers in the RAM detection process [2][3]. But on 32-bit RISC-V we fail to initialize CBMEM if we have 2048 MiB or more of RAM, and on 64-bit RISC-V we had to limit probing to 16383 MiB because it can run into MMIO regions otherwise. The qemu-armv7 mainboard code is intended for the "vexpress-a9" model VM which doesn't appear to suffer from this issue. Still, the issue can be observed on the ARMv7 "virt" model via a port based on qemu-aarch64. QEMU docs for ARM and RISC-V "virt" models [4][5] recommend reading the device tree blob it provides for device information (incl. RAM size). Implement functions that parse the device tree blob to find described memory regions and calculate the top of memory in order to use it in mainboard code as an alternative to probing RAM space. ARM64 code initializes CBMEM in romstage where malloc isn't available, so take care to do parsing without unflattening the blob and make the code available in romstage as well. [1] https://lore.kernel.org/qemu-devel/1504626814-23124-1-git-send-email-peter.… [2] https://review.coreboot.org/c/coreboot/+/34774 [3] https://review.coreboot.org/c/coreboot/+/36486 [4] https://qemu-project.gitlab.io/qemu/system/arm/virt.html [5] https://qemu-project.gitlab.io/qemu/system/riscv/virt.html Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> --- M src/include/device_tree.h M src/lib/Makefile.mk M src/lib/device_tree.c 3 files changed, 104 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/80322/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/80322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c Gerrit-Change-Number: 80322 Gerrit-PatchSet: 4 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com>

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[S] Change in coreboot[main]: mainboard/qemu-riscv: Get top of memory from device-tree blob
by Alper Nebi Yasak (Code Review) 25 May '24

25 May '24

Attention is currently required from: Alper Nebi Yasak, Philipp Hug, Ron Minnich. Hello Philipp Hug, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80363?usp=email to look at the new patch set (#3). Change subject: mainboard/qemu-riscv: Get top of memory from device-tree blob ...................................................................... mainboard/qemu-riscv: Get top of memory from device-tree blob Trying to probe RAM space to figure out top of memory causes an exception on RISC-V virtual machines with recent versions of QEMU, but we temporarily enable exception handlers for that and use it to help detect if a RAM address is usable or not. However, QEMU docs recommend reading device information from the device-tree blob it provides us at the start of RAM. A previous commit adds a library function to parse device-tree blob that QEMU provides us. Use it to determine top of memory in RISC-V QEMU virtual machines, but still fall back to the RAM probing approach as a last-ditch effort. Change-Id: I9e4a95f49ad373675939329eef40d7423a4132ab Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> --- M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/cbmem.c 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/80363/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e4a95f49ad373675939329eef40d7423a4132ab Gerrit-Change-Number: 80363 Gerrit-PatchSet: 3 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com>

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[XS] Change in coreboot[main]: mainboard/qemu-aarch64: Get top of memory from device-tree blob
by Alper Nebi Yasak (Code Review) 25 May '24

25 May '24

Attention is currently required from: Alper Nebi Yasak, Nico Huber. Hello Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80364?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber Change subject: mainboard/qemu-aarch64: Get top of memory from device-tree blob ...................................................................... mainboard/qemu-aarch64: Get top of memory from device-tree blob Trying to probe RAM space to figure out top of memory causes an exception on AArch64 virtual machines with recent versions of QEMU, but we temporarily enable exception handlers for that and use it to help detect if a RAM address is usable or not. However, QEMU docs recommend reading device information from the device-tree blob it provides us at the start of RAM. A previous commit adds a library function to parse device-tree blob that QEMU provides us. Use it to determine top of memory in AArch64 QEMU virtual machines, but still fall back to the RAM probing approach as a last-ditch effort. Change-Id: I4cc888b57cf98e0797ce7f9ddfa2eb34d14cd9c1 Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> --- M src/mainboard/emulation/qemu-aarch64/Kconfig M src/mainboard/emulation/qemu-aarch64/cbmem.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/80364/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80364?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4cc888b57cf98e0797ce7f9ddfa2eb34d14cd9c1 Gerrit-Change-Number: 80364 Gerrit-PatchSet: 3 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com>

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