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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa/var/sundance: Tune eMMC DLL delays to support more devices
......................................................................
mb/google/nissa/var/sundance: Tune eMMC DLL delays to support more devices
Currently some eMMC can't power on to OS nomally. Use the Intel provides eMMC DLL delay patch to modify some system can't boot to OS problem
BUG=b:342057438
TEST=Build and check each SKU eMMC can work.
Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57
Signed-off-by: roger2.wang <roger2.wang(a)lcfc.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/sundance/overridetree.cb
1 file changed, 46 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/82602/13
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Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/78888?usp=email )
Change subject: libpayload/libc/time: Fix possible overflow in multiplication
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78888/comment/104e02ff_d8db8619?us… :
PS11, Line 15: counter should never be that fast.
> > Okay, uploaded CB:80320 to doo that for now. […]
Done
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Change subject: soc/mediatek/mt8188: Decrease OP-TEE image size from 80 MB to 70 MB
......................................................................
Patch Set 4: Code-Review+2
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Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/81907?usp=email )
Change subject: util/lint: Add lint rule to avoid duplicated includes
......................................................................
Patch Set 5:
(1 comment)
File util/lint/lint-stable-031-includes:
https://review.coreboot.org/c/coreboot/+/81907/comment/7ee54566_f0e838d1?us… :
PS5, Line 56: check_duplicates '<arch/pci_ops.h>' '<device/pci_ops.h>'
> I guess if we want to enforce things, we'd first have to decide on the rules? […]
about <string.h>, I found it here https://review.coreboot.org/c/coreboot/+/39468
You are right, we need a rules for that.
The patch I've sent is based on 'IWYU pragma: export' comments in coreboot tree.
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Change subject: sio/nuvoton: Implement a common ramstage ACPI LDN helper
......................................................................
Patch Set 5:
(3 comments)
Patchset:
PS5:
Now that I think about it, in the future I'll want to make the port role swapping automatic if keyboard init fails (which would happen when initializing LDN 5), but the actual switch is in LDN A. There will have to be some data sharing (keyboard code needs to let ACPI code know keyboard init failed) but this current code may be too siloed for this purpose. Suggestions? Split the port role swapping?
File src/superio/nuvoton/common/common.c:
https://review.coreboot.org/c/coreboot/+/82632/comment/110b5e11_11c660c9?us… :
PS5, Line 53: /* TODO: Show proper message for "keep". */
> Let's do that right away? How about an array […]
Oh yeah that's how! Thanks for the tip
https://review.coreboot.org/c/coreboot/+/82632/comment/0c8983e7_a4415a34?us… :
PS5, Line 61: KB_WAKEUP_ANYKEY
> I'm not convinced this is what everybody wants/expects. In particular the "any […]
Or nvram option?
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Change subject: sio/nuvoton: Implement a common ramstage ACPI LDN helper
......................................................................
Patch Set 5: Code-Review+1
(4 comments)
File src/superio/nuvoton/common/common.c:
https://review.coreboot.org/c/coreboot/+/82632/comment/52b50741_cde55701?us… :
PS5, Line 53: /* TODO: Show proper message for "keep". */
Let's do that right away? How about an array
```
const char *const power_status_names[] = { "off", "on, "keep" };
```
Also, please skip the setting `if (power_status > 2)`.
https://review.coreboot.org/c/coreboot/+/82632/comment/0d280473_a8bd077b?us… :
PS5, Line 61: KB_WAKEUP_ANYKEY
I'm not convinced this is what everybody wants/expects. In particular the "any
button or movement"? How about putting the latter behind a Kconfig? (the "One
click of left or right button." option seems like a good default, just any move-
ment would be too much, IMHO).
https://review.coreboot.org/c/coreboot/+/82632/comment/4c5ca946_e03fc284?us… :
PS5, Line 72: KB_WAKEUP_PSOUT
At least for the mouse option, I don't see how it could be disabled otherwise.
File src/superio/nuvoton/nct5572d/superio.c:
https://review.coreboot.org/c/coreboot/+/82632/comment/ec6f2b19_72765ec2?us… :
PS5, Line 13: #define MAINBOARD_POWER_OFF 0
: #define MAINBOARD_POWER_ON 1
: #define MAINBOARD_POWER_KEEP 2
Not needed anymore.
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Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82660?usp=email )
Change subject: soc/intel/cmn/cse: Support CSE sync from payload
......................................................................
soc/intel/cmn/cse: Support CSE sync from payload
Skip CSE sync in coreboot when payload is doing it.
BUG=b:305898363
TEST=Verify CSE sync from depthcharge on Screebo
Change-Id: Ifa942576c803b8ec9e1e59c61917a14154fb94b2
Signed-off-by: Kapil Porwal <kapilporwal(a)google.com>
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse_lite.c
2 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/82660/1
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index b0524ea..edc7e23 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -150,6 +150,16 @@
In this case, the HECI interface needs to stay visible and the payload must support
sending commands to CSE.
+config SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
+ bool
+ depends on SOC_INTEL_COMMON_BLOCK_CSE
+ help
+ Use this config to specify that the payload will update the CSE RW partition instead
+ of coreboot.
+
+ In this case, CSE shall not switch to RW partition and the payload must support
+ CSE RW update.
+
config SOC_INTEL_CSE_LITE_SKU
bool
default n
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 3579bce..6e5b451 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -923,6 +923,9 @@
if (!CONFIG(SOC_INTEL_CSE_RW_UPDATE))
return false;
+ if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD))
+ return false;
+
if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE))
return !is_debug_cse_fw_update_disable();
@@ -1499,6 +1502,9 @@
void cse_fw_sync(void)
{
+ if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD))
+ return;
+
timestamp_add_now(TS_CSE_FW_SYNC_START);
do_cse_fw_sync();
timestamp_add_now(TS_CSE_FW_SYNC_END);
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Change subject: sio/nuvoton: Add Kconfig for shared PS/2 port
......................................................................
Patch Set 2: Code-Review+2
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82053?usp=email
to look at the new patch set (#9).
Change subject: [WIP] OptiPlex 3050 port
......................................................................
[WIP] OptiPlex 3050 port
- Boots Linux
- SMSC SCH5553 SIO/EC
+ Early EC init + HWM init implemented
+ Console on serial port tested
+ TODO: late HWM init for fan control (fan runs at low speed now)
- Realtek Gigabit LAN works
- WiFi slot works
- NVMe SSD slot works
- Extra: LPSS UART0
+ Stock FW sets undocumented power gating bit, RTC battery needs to
be pulled for it to work.
+ Signals exposed on test points on the back of the board.
FIXME: add documentation about this
- Has BootGuard
+ See https://codeberg.org/mkukri/optiplex-3050-bootguard-poc/
- TODO: audio
- TODO: cleanup GPIO table and device tree
Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2
Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com>
---
A src/mainboard/dell/optiplex_3050/Kconfig
A src/mainboard/dell/optiplex_3050/Kconfig.name
A src/mainboard/dell/optiplex_3050/Makefile.mk
A src/mainboard/dell/optiplex_3050/acpi/dptf.asl
A src/mainboard/dell/optiplex_3050/acpi/ec.asl
A src/mainboard/dell/optiplex_3050/acpi/mainboard.asl
A src/mainboard/dell/optiplex_3050/acpi/superio.asl
A src/mainboard/dell/optiplex_3050/board_info.txt
A src/mainboard/dell/optiplex_3050/bootblock.c
A src/mainboard/dell/optiplex_3050/cmos.default
A src/mainboard/dell/optiplex_3050/cmos.layout
A src/mainboard/dell/optiplex_3050/devicetree.cb
A src/mainboard/dell/optiplex_3050/dsdt.asl
A src/mainboard/dell/optiplex_3050/gma-mainboard.ads
A src/mainboard/dell/optiplex_3050/include/gpio.h
A src/mainboard/dell/optiplex_3050/mainboard.c
A src/mainboard/dell/optiplex_3050/ramstage.c
A src/mainboard/dell/optiplex_3050/romstage.c
A src/mainboard/dell/optiplex_3050/sch5555_ec.c
A src/mainboard/dell/optiplex_3050/sch5555_ec.h
20 files changed, 866 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/82053/9
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