coreboot-gerrit May 2024

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[L] Change in coreboot[main]: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)
by Angel Pons (Code Review) 26 May '24

26 May '24

Attention is currently required from: Federico Amedeo Izzo, Felix Held, Felix Singer, Paul Menzel. Angel Pons has posted comments on this change by Federico Amedeo Izzo. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email ) Change subject: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1) ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 16 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Brandon Weeks <bweeks(a)google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 26 May 2024 14:44:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)
by Federico Amedeo Izzo (Code Review) 26 May '24

26 May '24

Attention is currently required from: Angel Pons, Felix Held, Felix Singer, Paul Menzel. Federico Amedeo Izzo has posted comments on this change by Federico Amedeo Izzo. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email ) Change subject: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1) ...................................................................... Patch Set 15: (3 comments) Patchset: PS15: I managed to generate a `gpio.h` using high level macros as suggested by @felix-coreboot@felixheld.de, now the code looks much cleaner. There are no more open points on my side. I'm running this port on my home NAS and I'm happy with it 😊. File src/mainboard/aoostar/wtr_r1/gpio.h: PS14: > i wonder if the more high level gpio configuration macros could be used here instead of _PAD_CFG_STR […] Thank you for the heads up! I figured out running `intelp2m` with `-n` does exactly that. I tested the result and got no regressions. File src/mainboard/aoostar/wtr_r1/gpio.h: https://review.coreboot.org/c/coreboot/+/82010/comment/55954dde_cdda1306?us… : PS10, Line 14: _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | : PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* CORE_VID0 */ > Would be great if these could be translated to more readable macros, like […] I solved this, see comment by @felix-coreboot@felixheld.de -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 15 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Brandon Weeks <bweeks(a)google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 26 May 2024 14:02:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[L] Change in coreboot[main]: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)
by Federico Amedeo Izzo (Code Review) 26 May '24

26 May '24

Attention is currently required from: Angel Pons, Federico Amedeo Izzo, Felix Singer, Paul Menzel. Hello Angel Pons, Felix Singer, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82010?usp=email to look at the new patch set (#15). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1) ...................................................................... mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1) AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4-3200 SODIMM slot up to 32GB. It also comes with 2x 2.5Gb Intel NICs, Intel AX200 WiFi + BT and USB-C Alt-DP Power Delivery. Working: - DDR4 RAM (tested with Crucial 16GB 3200MHz CL22) - Automatic FAN control (IT8613E Super I/O) - M.2 NVME slot - 2x SATA ports (Issue on 3.5" HDD, see below) - USB 2.0 ports - USB 3.0 ports - USB-C port with Alt-DP and PD - HDMI / DisplayPort ports - 2x 2.5Gb NICs - WiFi + BT - MicroSD card reader - ASPM (Unavailable on stock) - Linux (Arch Linux, kernel 6.8.7-arch1-1) UEFI booting with EDK2 - Windows 10 UEFI booting with EDK2 Broken: - Power button (OFF->ON broken, ON->OFF works) - 3.5" SATA HDDs (Detected only after reboot) Untested: - Internal audio - S3 My motivation for doing this port is enabling ASPM, as it makes a great difference on idle power consumption (from 8.4W to 5W measured from the wall). The last remaining annoyance of this port is the power button not working. I spent a few hours double checking the Super I/O registers but then I gave up. A workaround for this is to use the "ON after power loss" feature and reconnect the power cord to turn on the board. It's not a big problem for a NAS that will stay ON 24/7. Any hint on the power button or 3.5" HDD issue is welcome. VBT extracted from vendor UEFI firmware version 1AXFE 0.01 x64 (Build date and time 11/29/2023 10:57:44) Compiled with FSP GOP video initialization, using IFD descriptor and ME blob extracted from vendor UEFI firmware (see above). The board can be flashed externally using a 1.8V adapter, I used a CH341a modded for 3.3V I/O. Internal flashing works, as flash is not read/write protected. Patchset 5: Re-enabled dptf, added default options to Kconfig. Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works Patchset 8: Fixed microSD card reader Patchset 13: Change Super I/O Fan configuration to reduce fan noise Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Signed-off-by: Federico Amedeo Izzo <federico(a)izzo.pro> --- A src/mainboard/aoostar/Kconfig A src/mainboard/aoostar/Kconfig.name A src/mainboard/aoostar/wtr_r1/Kconfig A src/mainboard/aoostar/wtr_r1/Kconfig.name A src/mainboard/aoostar/wtr_r1/Makefile.mk A src/mainboard/aoostar/wtr_r1/board_info.txt A src/mainboard/aoostar/wtr_r1/bootblock.c A src/mainboard/aoostar/wtr_r1/data.vbt A src/mainboard/aoostar/wtr_r1/devicetree.cb A src/mainboard/aoostar/wtr_r1/dsdt.asl A src/mainboard/aoostar/wtr_r1/gpio.h A src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c 12 files changed, 726 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/82010/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 15 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Brandon Weeks <bweeks(a)google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Federico Amedeo Izzo <federico(a)izzo.pro>

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[M] Change in coreboot[main]: util/lint: Add lint rule to avoid duplicated includes
by Nico Huber (Code Review) 26 May '24

26 May '24

Attention is currently required from: Arthur Heymans, Elyes Haouas, Julius Werner, Martin L Roth. Nico Huber has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/81907?usp=email ) Change subject: util/lint: Add lint rule to avoid duplicated includes ...................................................................... Patch Set 5: (1 comment) File util/lint/lint-stable-031-includes: https://review.coreboot.org/c/coreboot/+/81907/comment/850699c4_26ce68e6?us… : PS5, Line 56: check_duplicates '<arch/pci_ops.h>' '<device/pci_ops.h>' I guess if we want to enforce things, we'd first have to decide on the rules? Some things here look spurious to me (e.g. string.h), some things seem debatable. Is it worth to discuss it all? how badly do we miss such a linter? -- To view, visit https://review.coreboot.org/c/coreboot/+/81907?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia14c73f0bffa6ee4b73254d71836f793af8771c4 Gerrit-Change-Number: 81907 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 26 May 2024 12:58:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: Makefile: Warn if flexible array members are not at the end
by Felix Singer (Code Review) 26 May '24

26 May '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77147?usp=email ) Change subject: Makefile: Warn if flexible array members are not at the end ...................................................................... Makefile: Warn if flexible array members are not at the end Change-Id: Ib704f7659d3b431ce7eebb4432c5b1a4272de3d2 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77147 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved Maximilian Brune: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Makefile.mk b/Makefile.mk index e642ac7..0358c88 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -501,7 +501,7 @@ CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie CFLAGS_common += -Wstring-compare ifeq ($(CONFIG_COMPILER_GCC),y) -CFLAGS_common += -Wold-style-declaration +CFLAGS_common += -Wold-style-declaration -Wflex-array-member-not-at-end # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) CFLAGS_common += -Wno-packed-not-aligned -- To view, visit https://review.coreboot.org/c/coreboot/+/77147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib704f7659d3b431ce7eebb4432c5b1a4272de3d2 Gerrit-Change-Number: 77147 Gerrit-PatchSet: 10 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <samekh(a)email.cz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org>

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[XS] Change in coreboot[main]: Makefile: Warn if flexible array members are not at the end
by Felix Singer (Code Review) 26 May '24

26 May '24

Attention is currently required from: Elyes Haouas, Jan Samek, Martin L Roth. Felix Singer has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/77147?usp=email ) Change subject: Makefile: Warn if flexible array members are not at the end ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib704f7659d3b431ce7eebb4432c5b1a4272de3d2 Gerrit-Change-Number: 77147 Gerrit-PatchSet: 9 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <samekh(a)email.cz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jan Samek <samekh(a)email.cz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 26 May 2024 11:40:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Angel Pons (Code Review) 26 May '24

26 May '24

Attention is currently required from: Tim Wawrzynczak. Angel Pons has posted comments on this change by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/50857?usp=email ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 22: (1 comment) File src/southbridge/intel/common/rcba_pirq.c: https://review.coreboot.org/c/coreboot/+/50857/comment/61c6a666_a63788d5?us… : PS22, Line 61: pin_irq_map = calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX); > `nano +376 src/soc/intel/common/block/irq/irq.c` , gives […] They're equivalent -- To view, visit https://review.coreboot.org/c/coreboot/+/50857?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 22 Gerrit-Owner: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Sun, 26 May 2024 11:13:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Elyes Haouas (Code Review) 26 May '24

26 May '24

Attention is currently required from: Tim Wawrzynczak. Elyes Haouas has posted comments on this change by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/50857?usp=email ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 22: (1 comment) File src/southbridge/intel/common/rcba_pirq.c: https://review.coreboot.org/c/coreboot/+/50857/comment/e9d9abde_ba1b2236?us… : PS22, Line 61: pin_irq_map = calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX); `nano +376 src/soc/intel/common/block/irq/irq.c` , gives `pin_irq_map = calloc(MAX_SLOTS, sizeof(struct slot_pin_irq_map) * PCI_INT_MAX);` which one is correct ? -- To view, visit https://review.coreboot.org/c/coreboot/+/50857?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 22 Gerrit-Owner: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Sun, 26 May 2024 08:25:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: tree: Use Wcalloc-transposed-args command option
by Elyes Haouas (Code Review) 26 May '24

26 May '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82658?usp=email ) Change subject: tree: Use Wcalloc-transposed-args command option ...................................................................... tree: Use Wcalloc-transposed-args command option GCC-14 documentation says "The first argument to calloc is documented to be number of elements in array, while the second argument is size of each element, so calloc(n, sizeof (int)) is preferred over calloc(sizeof(int), n). If sizeof in the earlier argument and not the latter is intentional, the warning can be suppressed by using calloc(sizeof(struct S) + 0, n) or calloc(1 * sizeof(struct S), 4) or using sizeof in the later argument as well." Change-Id: I77b6f4d2eda487b087ba5665b588999633c33e8d Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/82658/1 diff --git a/Makefile.mk b/Makefile.mk index e642ac7..97de077 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -501,7 +501,7 @@ CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie CFLAGS_common += -Wstring-compare ifeq ($(CONFIG_COMPILER_GCC),y) -CFLAGS_common += -Wold-style-declaration +CFLAGS_common += -Wold-style-declaration -Wcalloc-transposed-args # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) CFLAGS_common += -Wno-packed-not-aligned -- To view, visit https://review.coreboot.org/c/coreboot/+/82658?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77b6f4d2eda487b087ba5665b588999633c33e8d Gerrit-Change-Number: 82658 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: mainboard/qemu-riscv: Get top of memory from device-tree blob
by Maximilian Brune (Code Review) 25 May '24

25 May '24

Attention is currently required from: Alper Nebi Yasak, Philipp Hug, Ron Minnich. Maximilian Brune has posted comments on this change by Alper Nebi Yasak. ( https://review.coreboot.org/c/coreboot/+/80363?usp=email ) Change subject: mainboard/qemu-riscv: Get top of memory from device-tree blob ...................................................................... Patch Set 3: (1 comment) File src/mainboard/emulation/qemu-riscv/cbmem.c: https://review.coreboot.org/c/coreboot/+/80363/comment/37d634b4_904ced63?us… : PS3, Line 11: if (CONFIG(FLATTENED_DEVICE_TREE)) { Now that there is no shared soc code anymore we don't need that anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/80363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e4a95f49ad373675939329eef40d7423a4132ab Gerrit-Change-Number: 80363 Gerrit-PatchSet: 3 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sun, 26 May 2024 02:21:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit May 2024