coreboot-gerrit May 2024

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[S] Change in coreboot[main]: util/lint: Add lint rule to warn if <stdint.h> is included but not used
by Elyes Haouas (Code Review) 30 May '24

30 May '24

Attention is currently required from: Martin L Roth. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82712?usp=email ) Change subject: util/lint: Add lint rule to warn if <stdint.h> is included but not used ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Additionally, I have created a combined script that checks <string.h>, <stdint.h>, and <stddef.h> in a single file for your review: https://review.coreboot.org/c/coreboot/+/82713 Please review the scripts and provide your feedback. We need to decide whether to opt for the individual scripts for each header or to use the combined script that handles all three headers together. -- To view, visit https://review.coreboot.org/c/coreboot/+/82712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I318189f88c4ee8803075efc4fe2cb9b58547c126 Gerrit-Change-Number: 82712 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 30 May 2024 15:15:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: util/lint: Warn if {stddef,stdint,string}.h included but not used
by Elyes Haouas (Code Review) 30 May '24

30 May '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82713?usp=email ) Change subject: util/lint: Warn if {stddef,stdint,string}.h included but not used ...................................................................... util/lint: Warn if {stddef,stdint,string}.h included but not used Change-Id: I94104df7a2e25c0197b4027eb7fddd52cbc4c6ad Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- A util/lint/lint-stable-032-includes 1 file changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/82713/1 diff --git a/util/lint/lint-stable-032-includes b/util/lint/lint-stable-032-includes new file mode 100755 index 0000000..7bc2f26 --- /dev/null +++ b/util/lint/lint-stable-032-includes @@ -0,0 +1,55 @@ +#!/usr/bin/env sh +# SPDX-License-Identifier: GPL-2.0-or-later +# +# DESCR: Verify if header files are needed in modified files +# + +# Get the list of modified files +MODIFIED_FILES=$(git diff --cached --name-only --diff-filter=ACM | grep -E '\.c$|\.h$') +if [ -z "$MODIFIED_FILES" ]; then + exit 0 +fi + +# Create temporary files to hold the lists +TMP_INCLUDE=$(mktemp) +TMP_FUNCTIONS=$(mktemp) + +# Define the headers and their associated functions/types to check +declare -A HEADERS +HEADERS["<stddef.h>"]="size_t\b\|ptrdiff_t\b\|NULL\b\|offsetof\b\|wchar_t\b" +HEADERS["<stdint.h>"]="int8_t\b\|int16_t\b\|int32_t\b\|int64_t\b\|uint8_t\b\|uint16_t\b\|uint32_t\b\|uint64_t\b\|intptr_t\b\|uintptr_t\b" +HEADERS["<string.h>"]="memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi" + +for header in "${!HEADERS[@]}"; do + INCLUDE_LIST=$(mktemp) + FUNCTION_LIST=$(mktemp) + + # Find files including the header + for file in $MODIFIED_FILES; do + if grep -q "#include $header" "$file"; then + echo "$file" >> "$INCLUDE_LIST" + fi + done + + # Find files using the functions/types associated with the header + for file in $MODIFIED_FILES; do + if grep -q "${HEADERS[$header]}" "$file"; then + echo "$file" >> "$FUNCTION_LIST" + fi + done + + # Compare the two lists to find unnecessary includes + UNNEEDED_INCLUDE=$(comm -23 <(sort "$INCLUDE_LIST") <(sort "$FUNCTION_LIST")) + + # Output warnings for unneeded includes + if [ -n "$UNNEEDED_INCLUDE" ]; then + echo "Warning: The following files include $header but do not use its functions/types:" + echo "$UNNEEDED_INCLUDE" + fi + + # Clean up temporary files + rm -f "$INCLUDE_LIST" "$FUNCTION_LIST" +done + +# Clean up temporary files +rm -f "$TMP_INCLUDE" "$TMP_FUNCTIONS" -- To view, visit https://review.coreboot.org/c/coreboot/+/82713?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94104df7a2e25c0197b4027eb7fddd52cbc4c6ad Gerrit-Change-Number: 82713 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: util/lint: Add lint rule to warn if <stdint.h> is included but not used
by Elyes Haouas (Code Review) 30 May '24

30 May '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82712?usp=email ) Change subject: util/lint: Add lint rule to warn if <stdint.h> is included but not used ...................................................................... util/lint: Add lint rule to warn if <stdint.h> is included but not used Change-Id: I318189f88c4ee8803075efc4fe2cb9b58547c126 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- A util/lint/lint-stable-034-stdint-h 1 file changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/82712/1 diff --git a/util/lint/lint-stable-034-stdint-h b/util/lint/lint-stable-034-stdint-h new file mode 100755 index 0000000..61ca04d --- /dev/null +++ b/util/lint/lint-stable-034-stdint-h @@ -0,0 +1,41 @@ +#!/usr/bin/env sh +# SPDX-License-Identifier: GPL-2.0-or-later +# +# DESCR: Verify if <stdint.h> is needed in modified files +# + +# Get the list of modified files +MODIFIED_FILES=$(git diff --cached --name-only --diff-filter=ACM | grep -E '\.c$|\.h$') +if [ -z "$MODIFIED_FILES" ]; then + exit 0 +fi + +# Create temporary files to hold the lists +TMP_INCLUDE=$(mktemp) +TMP_TYPES=$(mktemp) + +# Find files including <stdint.h> +for file in $MODIFIED_FILES; do + if grep -q '#include <stdint.h>' "$file"; then + echo "$file" >> "$TMP_INCLUDE" + fi +done + +# Find files using stdint.h types +for file in $MODIFIED_FILES; do + if grep -q '\bint8_t\b\|int16_t\b\|int32_t\b\|int64_t\b\|uint8_t\b\|uint16_t\b\|uint32_t\b\|uint64_t\b\|intptr_t\b\|uintptr_t\b' "$file"; then + echo "$file" >> "$TMP_TYPES" + fi +done + +# Compare the two lists to find unnecessary includes +UNNEEDED_INCLUDE=$(comm -23 <(sort "$TMP_INCLUDE") <(sort "$TMP_TYPES")) + +# Output warnings for unneeded includes +if [ -n "$UNNEEDED_INCLUDE" ]; then + echo "Warning: The following files include <stdint.h> but do not use its types:" + echo "$UNNEEDED_INCLUDE" +fi + +# Clean up temporary files +rm -f "$TMP_INCLUDE" "$TMP_TYPES" -- To view, visit https://review.coreboot.org/c/coreboot/+/82712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I318189f88c4ee8803075efc4fe2cb9b58547c126 Gerrit-Change-Number: 82712 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: tree: Remove duplicated <soc/gpio.h>
by Elyes Haouas (Code Review) 30 May '24

30 May '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82691?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: tree: Remove duplicated <soc/gpio.h> ...................................................................... tree: Remove duplicated <soc/gpio.h> <gpio.h> is supposed to chain-include <soc/gpio.h>. Change-Id: Ib25581bd2c8dd38cdd0396561ce5f9a782365f14 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82691 Reviewed-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/lenovo/m900_tiny/ramstage.c M src/mainboard/msi/ms7d25/die.c M src/mainboard/msi/ms7e06/die.c M src/mainboard/protectli/vault_cml/die.c M src/soc/qualcomm/common/pcie_common.c M src/soc/qualcomm/common/qspi.c M src/soc/qualcomm/sc7280/pcie.c M src/soc/rockchip/common/gpio.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/gpio.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/gpio.c M src/soc/sifive/fu740/clock.c M src/soc/sifive/fu740/gpio.c 14 files changed, 0 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Michał Kopeć: Looks good to me, approved diff --git a/src/mainboard/lenovo/m900_tiny/ramstage.c b/src/mainboard/lenovo/m900_tiny/ramstage.c index 47add6f..6e66f3a 100644 --- a/src/mainboard/lenovo/m900_tiny/ramstage.c +++ b/src/mainboard/lenovo/m900_tiny/ramstage.c @@ -5,7 +5,6 @@ #include <drivers/intel/gma/int15.h> #include <gpio.h> #include <mainboard/gpio.h> -#include <soc/gpio.h> #include <soc/ramstage.h> static void print_board_id(void) diff --git a/src/mainboard/msi/ms7d25/die.c b/src/mainboard/msi/ms7d25/die.c index 52b3338..34fa75b 100644 --- a/src/mainboard/msi/ms7d25/die.c +++ b/src/mainboard/msi/ms7d25/die.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <pc80/i8254.h> -#include <soc/gpio.h> #include <delay.h> #include <gpio.h> diff --git a/src/mainboard/msi/ms7e06/die.c b/src/mainboard/msi/ms7e06/die.c index 52b3338..34fa75b 100644 --- a/src/mainboard/msi/ms7e06/die.c +++ b/src/mainboard/msi/ms7e06/die.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <pc80/i8254.h> -#include <soc/gpio.h> #include <delay.h> #include <gpio.h> diff --git a/src/mainboard/protectli/vault_cml/die.c b/src/mainboard/protectli/vault_cml/die.c index 52b3338..34fa75b 100644 --- a/src/mainboard/protectli/vault_cml/die.c +++ b/src/mainboard/protectli/vault_cml/die.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <pc80/i8254.h> -#include <soc/gpio.h> #include <delay.h> #include <gpio.h> diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c index 65c2940..b877563 100644 --- a/src/soc/qualcomm/common/pcie_common.c +++ b/src/soc/qualcomm/common/pcie_common.c @@ -9,7 +9,6 @@ #include <device/pci_ids.h> #include <gpio.h> #include <soc/clock.h> -#include <soc/gpio.h> #include <soc/qcom_qmp_phy.h> #include <soc/pcie.h> #include <timer.h> diff --git a/src/soc/qualcomm/common/qspi.c b/src/soc/qualcomm/common/qspi.c index 3340c00..088c79d 100644 --- a/src/soc/qualcomm/common/qspi.c +++ b/src/soc/qualcomm/common/qspi.c @@ -6,7 +6,6 @@ #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/qspi_common.h> -#include <soc/gpio.h> #include <soc/clock.h> #include <symbols.h> #include <assert.h> diff --git a/src/soc/qualcomm/sc7280/pcie.c b/src/soc/qualcomm/sc7280/pcie.c index 84fa44c..e904455 100644 --- a/src/soc/qualcomm/sc7280/pcie.c +++ b/src/soc/qualcomm/sc7280/pcie.c @@ -7,7 +7,6 @@ #include <gpio.h> #include <soc/addressmap.h> #include <soc/clock.h> -#include <soc/gpio.h> #include <soc/qcom_qmp_phy.h> #include <soc/pcie.h> diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 73ddfd7..5629e6b 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <assert.h> #include <gpio.h> -#include <soc/gpio.h> #include <soc/grf.h> #include <soc/soc.h> #include <types.h> diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 9d6cca1..f9f41e2 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -13,7 +13,6 @@ #include <soc/display.h> #include <soc/edp.h> #include <soc/hdmi.h> -#include <soc/gpio.h> #include <soc/grf.h> #include <soc/soc.h> #include <soc/vop.h> diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index ed09d02..a1da1d7 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -2,7 +2,6 @@ #include <gpio.h> #include <soc/addressmap.h> -#include <soc/gpio.h> #include <soc/grf.h> #include <soc/pmu.h> #include <soc/soc.h> diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 728f45d..f0b7871 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -12,7 +12,6 @@ #include <soc/clock.h> #include <soc/display.h> #include <soc/edp.h> -#include <soc/gpio.h> #include <soc/grf.h> #include <soc/mmu_operations.h> #include <soc/mipi.h> diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c index 6c022d8..8c66987 100644 --- a/src/soc/rockchip/rk3399/gpio.c +++ b/src/soc/rockchip/rk3399/gpio.c @@ -2,7 +2,6 @@ #include <gpio.h> #include <soc/addressmap.h> -#include <soc/gpio.h> #include <soc/grf.h> #include <soc/soc.h> diff --git a/src/soc/sifive/fu740/clock.c b/src/soc/sifive/fu740/clock.c index 91e7992..299409d 100644 --- a/src/soc/sifive/fu740/clock.c +++ b/src/soc/sifive/fu740/clock.c @@ -7,7 +7,6 @@ #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/clock.h> -#include <soc/gpio.h> #include <gpio.h> #include <stdint.h> diff --git a/src/soc/sifive/fu740/gpio.c b/src/soc/sifive/fu740/gpio.c index d5576f2..a38e590 100644 --- a/src/soc/sifive/fu740/gpio.c +++ b/src/soc/sifive/fu740/gpio.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/addressmap.h> -#include <soc/gpio.h> #include <stdint.h> #include <arch/mmio.h> #include <assert.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/82691?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib25581bd2c8dd38cdd0396561ce5f9a782365f14 Gerrit-Change-Number: 82691 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: src/mainboard/google/rex: Enable Rex64 build configuration
by Kapil Porwal (Code Review) 30 May '24

30 May '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Subrata Banik, Tarun. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/82625?usp=email ) Change subject: src/mainboard/google/rex: Enable Rex64 build configuration ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Gerrit-Change-Number: 82625 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 30 May 2024 13:32:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Tailor FSP Version Selection for Architecture
by Kapil Porwal (Code Review) 30 May '24

30 May '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Subrata Banik, Tarun. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/82624?usp=email ) Change subject: soc/intel/meteorlake: Tailor FSP Version Selection for Architecture ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82624?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib77a34c6bf7bca3485a197f109d1550ac3d51cc0 Gerrit-Change-Number: 82624 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 30 May 2024 13:32:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: vc/intel/fsp/mtl: Add x86_64 FSP V3471.91 headers
by Subrata Banik (Code Review) 30 May '24

30 May '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82473?usp=email ) Change subject: vc/intel/fsp/mtl: Add x86_64 FSP V3471.91 headers ...................................................................... vc/intel/fsp/mtl: Add x86_64 FSP V3471.91 headers This commit introduces new header files of V3471.91 for the x86_64 architecture in the fsp2_0/meteorlake directory. FSP2.4 brings FSP 64-bits support and the soc Kconfig file has been updated to select this new header path when FSP2.4 is in use. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Ib41b57e794311db729ac65a968f562aa127e86c3 Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82473 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/soc/intel/meteorlake/Kconfig A src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FirmwareVersionInfo.h A src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspProducerDataHeader.h A src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/MemInfoHob.h 7 files changed, 6,942 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 43f6545..2721e0b 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -347,6 +347,7 @@ config FSP_HEADER_PATH string "Location of FSP headers" + default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/" if PLATFORM_USES_FSP2_4 default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/" config FSP_FD_PATH diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FirmwareVersionInfo.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FirmwareVersionInfo.h new file mode 100644 index 0000000..d3776cc --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FirmwareVersionInfo.h @@ -0,0 +1,55 @@ +/** @file + Intel Firmware Version Info (FVI) related definitions. + + @todo update document/spec reference + + Copyright (c) 2016, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: + System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12 + http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.p… + +**/ + +#ifndef __FIRMWARE_VERSION_INFO_H__ +#define __FIRMWARE_VERSION_INFO_H__ + +#include <IndustryStandard/SmBios.h> + +#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info" +#define INTEL_FVI_SMBIOS_TYPE 0xDD + +#pragma pack(1) + +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} INTEL_FIRMWARE_VERSION; + +/// +/// Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name + SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String + INTEL_FIRMWARE_VERSION Version; ///< Firmware version +} INTEL_FIRMWARE_VERSION_INFO; + +/// +/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_STRUCTURE Header; ///< SMBIOS structure header + UINT8 Count; ///< Number of FVI entries in this structure + INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s) +} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspProducerDataHeader.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspProducerDataHeader.h new file mode 100644 index 0000000..b7cd634 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspProducerDataHeader.h @@ -0,0 +1,80 @@ +/** @file + + Copyright (c) 2023, Intel Corporation. All rights reserved. + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ +#ifndef _FSP_PRODUCER_DATA_HEADER_H_ +#define _FSP_PRODUCER_DATA_HEADER_H_ + +#include <Guid/FspHeaderFile.h> + +#define BUILD_TIME_STAMP_SIZE 12 + +// +// FSP Header Data structure from FspHeader driver. +// +#pragma pack(1) +/// +/// FSP Producer Data Subtype - 1 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image. + /// + UINT32 RcVersion; + /// + /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM". + /// + UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE]; +} FSP_PRODUCER_DATA_TYPE1; + +/// +/// FSP Producer Data Subtype - 2 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image. + /// + UINT8 MrcVersion [4]; +} FSP_PRODUCER_DATA_TYPE2; + +typedef struct { + FSP_INFO_HEADER FspInfoHeader; + FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader; + FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1; + FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2; + FSP_PATCH_TABLE FspPatchTable; +} FSP_PRODUCER_DATA_TABLES; +#pragma pack() + +#endif // _FSP_PRODUCER_DATA_HEADER_H diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspUpd.h new file mode 100644 index 0000000..f07ee2f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2024, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C544D /* 'MTLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C544D /* 'MTLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C544D /* 'MTLUPD_S' */ + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspmUpd.h new file mode 100644 index 0000000..a19b5aa --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspmUpd.h @@ -0,0 +1,3240 @@ +/** @file + +Copyright (c) 2024, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +#include <MemInfoHob.h> + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0060 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0068 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x006A - Enable above 4GB MMIO resource support + Enable/disable above 4GB MMIO resource support + $EN_DIS +**/ + UINT8 EnableAbove4GBMmio; + +/** Offset 0x006B - Reserved +**/ + UINT8 Reserved0[5]; + +/** Offset 0x0070 - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr000; + +/** Offset 0x0078 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr001; + +/** Offset 0x0080 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr010; + +/** Offset 0x0088 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr011; + +/** Offset 0x0090 - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr020; + +/** Offset 0x0098 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr021; + +/** Offset 0x00A0 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr030; + +/** Offset 0x00A8 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr031; + +/** Offset 0x00B0 - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr100; + +/** Offset 0x00B8 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr101; + +/** Offset 0x00C0 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr110; + +/** Offset 0x00C8 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr111; + +/** Offset 0x00D0 - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr120; + +/** Offset 0x00D8 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr121; + +/** Offset 0x00E0 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr130; + +/** Offset 0x00E8 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT64 MemorySpdPtr131; + +/** Offset 0x00F0 - RcompResistor settings + Indicates RcompResistor settings: Board-dependent +**/ + UINT16 RcompResistor; + +/** Offset 0x00F2 - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x00FC - Dqs Map CPU to DRAM MC 0 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch0[2]; + +/** Offset 0x00FE - Dqs Map CPU to DRAM MC 0 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch1[2]; + +/** Offset 0x0100 - Dqs Map CPU to DRAM MC 0 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch2[2]; + +/** Offset 0x0102 - Dqs Map CPU to DRAM MC 0 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch3[2]; + +/** Offset 0x0104 - Dqs Map CPU to DRAM MC 1 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch0[2]; + +/** Offset 0x0106 - Dqs Map CPU to DRAM MC 1 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch1[2]; + +/** Offset 0x0108 - Dqs Map CPU to DRAM MC 1 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch2[2]; + +/** Offset 0x010A - Dqs Map CPU to DRAM MC 1 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch3[2]; + +/** Offset 0x010C - Dq Map CPU to DRAM MC 0 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch0[16]; + +/** Offset 0x011C - Dq Map CPU to DRAM MC 0 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch1[16]; + +/** Offset 0x012C - Dq Map CPU to DRAM MC 0 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch2[16]; + +/** Offset 0x013C - Dq Map CPU to DRAM MC 0 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch3[16]; + +/** Offset 0x014C - Dq Map CPU to DRAM MC 1 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch0[16]; + +/** Offset 0x015C - Dq Map CPU to DRAM MC 1 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch1[16]; + +/** Offset 0x016C - Dq Map CPU to DRAM MC 1 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch2[16]; + +/** Offset 0x017C - Dq Map CPU to DRAM MC 1 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch3[16]; + +/** Offset 0x018C - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x018D - Smram Mask + The SMM Regions AB-SEG and/or H-SEG reserved + 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both +**/ + UINT8 SmramMask; + +/** Offset 0x018E - MRC Fast Boot + Enables/Disable the MRC fast path thru the MRC + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x018F - Rank Margin Tool per Task + This option enables the user to execute Rank Margin Tool per major training step + in the MRC. + $EN_DIS +**/ + UINT8 RmtPerTask; + +/** Offset 0x0190 - Training Trace + This option enables the trained state tracing feature in MRC. This feature will + print out the key training parameters state across major training steps. + $EN_DIS +**/ + UINT8 TrainTrace; + +/** Offset 0x0191 - Reserved +**/ + UINT8 Reserved1[7]; + +/** Offset 0x0198 - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x019C - MMIO Size + Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB +**/ + UINT16 MmioSize; + +/** Offset 0x019E - Probeless Trace + Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. + This also requires IED to be enabled. + $EN_DIS +**/ + UINT8 ProbelessTrace; + +/** Offset 0x019F - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x01A0 - Spd Address Tabl + Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used + if SPD Address is 00 +**/ + UINT8 SpdAddressTable[16]; + +/** Offset 0x01B0 - Platform Debug Consent + Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n + \n + Enabled Trace ready: TraceHub is enabled and allowed S0ix.\n + \n + Enabled Trace power off: TraceHub is powergated, provide setting close to functional + low power state\n + \n + Manual: user needs to configure Advanced Debug Settings manually, aimed at advanced users + 0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready, 6:Enable Trace Power-Off, 7:Manual +**/ + UINT8 PlatformDebugOption; + +/** Offset 0x01B1 - DCI Enable + Determine if to enable DCI debug from host + $EN_DIS +**/ + UINT8 DciEn; + +/** Offset 0x01B2 - Reserved +**/ + UINT8 Reserved2; + +/** Offset 0x01B3 - DCI DbC Mode + Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: + Set both USB2/3DBCEN; No Change: Comply with HW value + 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change +**/ + UINT8 DciDbcMode; + +/** Offset 0x01B4 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support + This BIOS option enables kernel and platform debug for USB3 interface over a UFP + Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 DciUsb3TypecUfpDbg; + +/** Offset 0x01B5 - SOC Trace Hub Mode + Enable/Disable SOC TraceHub + $EN_DIS +**/ + UINT8 SocTraceHubMode; + +/** Offset 0x01B6 - SOC Trace Hub Memory Region 0 buffer Size + Select size of memory region 0 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 SocTraceHubMemReg0Size; + +/** Offset 0x01B8 - SOC Trace Hub Memory Region 1 buffer Size + Select size of memory region 1 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 SocTraceHubMemReg1Size; + +/** Offset 0x01BA - Reserved +**/ + UINT8 Reserved3; + +/** Offset 0x01BB - PCH Trace Hub Mode + Enable/Disable PCH TraceHub + $EN_DIS +**/ + UINT8 PchTraceHubMode; + +/** Offset 0x01BC - PCH Trace Hub Memory Region 0 buffer Size + Select size of memory region 0 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 PchTraceHubMemReg0Size; + +/** Offset 0x01BE - PCH Trace Hub Memory Region 1 buffer Size + Select size of memory region 1 buffer. Memory allocated by BIOS only applies to + ITH tool running on the host. For ITH tool running on the target, choose None/OS, + memory shall be allocated by tool. User should be cautious to choose the amount + of memory. If chosen size is larger than half of system memory, setup will automatically + rollback to default value. + 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, + 0x0C:4GB, 0x0D:8GB, 0x0E:0MB +**/ + UINT16 PchTraceHubMemReg1Size; + +/** Offset 0x01C0 - Reserved +**/ + UINT8 Reserved4[4]; + +/** Offset 0x01C4 - HD Audio DMIC Link Clock Select + Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB + 0: Both, 1: ClkA, 2: ClkB +**/ + UINT8 PchHdaAudioLinkDmicClockSelect[2]; + +/** Offset 0x01C6 - State of X2APIC_OPT_OUT bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 X2ApicOptOut; + +/** Offset 0x01C7 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 DmaControlGuarantee; + +/** Offset 0x01C8 - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + UINT32 VtdBaseAddress[9]; + +/** Offset 0x01EC - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x01ED - Vtd Programming for Igd + 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIgdEnable; + +/** Offset 0x01EE - Vtd Programming for Iop + 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIopEnable; + +/** Offset 0x01EF - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, + 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, + 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x01F0 - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x01F1 - Reserved +**/ + UINT8 Reserved5; + +/** Offset 0x01F2 - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile + Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x01F3 - Reserved +**/ + UINT8 Reserved6; + +/** Offset 0x01F4 - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, + 2133, 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 DdrFreqLimit; + +/** Offset 0x01F6 - SAGV + System Agent dynamic frequency support. + 0:Disabled, 1:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x01F7 - SAGV WP Mask + System Agent dynamic frequency workpoints that memory will be training at the enabled + frequencies. + 0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3 +**/ + UINT8 SaGvWpMask; + +/** Offset 0x01F8 - Memory Test on Warm Boot + Run Base Memory Test on Warm Boot + 0:Disable, 1:Enable +**/ + UINT8 MemTestOnWarmBoot; + +/** Offset 0x01F9 - DDR Speed Control + DDR Frequency and Gear control for all SAGV points. + 0:Auto, 1:Manual +**/ + UINT8 DdrSpeedControl; + +/** Offset 0x01FA - Controller 0 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc0Ch0; + +/** Offset 0x01FB - Controller 0 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc0Ch1; + +/** Offset 0x01FC - Controller 0 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc0Ch2; + +/** Offset 0x01FD - Controller 0 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc0Ch3; + +/** Offset 0x01FE - Controller 1 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc1Ch0; + +/** Offset 0x01FF - Controller 1 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc1Ch1; + +/** Offset 0x0200 - Controller 1 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc1Ch2; + +/** Offset 0x0201 - Controller 1 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc1Ch3; + +/** Offset 0x0202 - Scrambler Support + This option enables data scrambling in memory. + $EN_DIS +**/ + UINT8 ScramblerSupport; + +/** Offset 0x0203 - SPD Profile Selected + Select DIMM timing profile. Options are 0:Default SPD Profile, 1:Custom Profile, + 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP Profile 3, 5:XMP User Profile 4, 6:XMP + User Profile 5 + 0:Default SPD Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP + Profile 3, 5:XMP User Profile 4, 6:XMP User Profile 5 +**/ + UINT8 SpdProfileSelected; + +/** Offset 0x0204 - Reserved +**/ + UINT8 Reserved7[102]; + +/** Offset 0x026A - Memory Reference Clock + 100MHz, 133MHz. + 0:133MHz, 1:100MHz +**/ + UINT8 RefClk; + +/** Offset 0x026B - Reserved +**/ + UINT8 Reserved8[9]; + +/** Offset 0x0274 - Memory Vdd Voltage + DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM + chips) in millivolts. 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc. + 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 + Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts +**/ + UINT16 VddVoltage; + +/** Offset 0x0276 - Reserved +**/ + UINT8 Reserved9[4]; + +/** Offset 0x027A - Memory Ratio + Automatic or the frequency will equal ratio times reference clock. Set to Auto to + recalculate memory timings listed below. + 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT16 Ratio; + +/** Offset 0x027C - tCL + CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tCL; + +/** Offset 0x027D - tCWL + Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tCWL; + +/** Offset 0x027E - tFAW + Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tFAW; + +/** Offset 0x0280 - tRAS + RAS Active Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRAS; + +/** Offset 0x0282 - tRCD/tRP + RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 255. Only used + if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tRCDtRP; + +/** Offset 0x0283 - Reserved +**/ + UINT8 Reserved10; + +/** Offset 0x0284 - tREFI + Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tREFI; + +/** Offset 0x0286 - tRFC + Min Refresh Recovery Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRFC; + +/** Offset 0x0288 - tRRD + Min Row Active to Row Active Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tRRD; + +/** Offset 0x0289 - tRTP + Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 255. Only used + if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tRTP; + +/** Offset 0x028A - tWR + Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, + 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). + 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, + 34:34, 40:40 +**/ + UINT8 tWR; + +/** Offset 0x028B - tWTR + Min Internal Write to Read Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tWTR; + +/** Offset 0x028C - Reserved +**/ + UINT8 Reserved11[12]; + +/** Offset 0x0298 - NMode + System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N +**/ + UINT8 NModeSupport; + +/** Offset 0x0299 - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x029A - Enable PCH ISH Controller + 0: Disable, 1: Enable (Default) ISH Controller + $EN_DIS +**/ + UINT8 PchIshEnable; + +/** Offset 0x029B - Reserved +**/ + UINT8 Reserved12[7]; + +/** Offset 0x02A2 - SAGV Gear Ratio + Gear Selection for SAGV points. 0 - Auto, 2-Gear 2, 4-Gear 4 +**/ + UINT8 SaGvGear[4]; + +/** Offset 0x02A6 - SAGV Frequency + SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300. +**/ + UINT16 SaGvFreq[4]; + +/** Offset 0x02AE - SAGV Disabled Gear Ratio + Gear Selection for SAGV Disabled. 0 - Auto, 2-Gear 2, 2-Gear 4 +**/ + UINT8 GearRatio; + +/** Offset 0x02AF - Reserved +**/ + UINT8 Reserved13[69]; + +/** Offset 0x02F4 - MMIO size adjustment for AUTO mode + Positive number means increasing MMIO size, Negative value means decreasing MMIO + size: 0 (Default)=no change to AUTO mode MMIO size +**/ + UINT16 MmioSizeAdjustment; + +/** Offset 0x02F6 - Selection of the primary display device + 0=iGFX, 3(Default)=AUTO, 4=Hybrid Graphics + 0:iGFX, 3:AUTO, 4:Hybrid Graphics +**/ + UINT8 PrimaryDisplay; + +/** Offset 0x02F7 - Reserved +**/ + UINT8 Reserved14; + +/** Offset 0x02F8 - Temporary MMIO address for GMADR + Obsolete field now and it has been extended to 64 bit address, used LMemBar +**/ + UINT32 GmAdr; + +/** Offset 0x02FC - Temporary MMIO address for GTTMMADR + The reference code will use this as Temporary MMIO address space to access GTTMMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr + to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) +**/ + UINT32 GttMmAdr; + +/** Offset 0x0300 - Enable/Disable MRC TXT dependency + When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): + MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization + $EN_DIS +**/ + UINT8 TxtImplemented; + +/** Offset 0x0301 - Enable/Disable SA OcSupport + Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport + $EN_DIS +**/ + UINT8 SaOcSupport; + +/** Offset 0x0302 - GT slice Voltage Mode + 0(Default): Adaptive, 1: Override + 0: Adaptive, 1: Override +**/ + UINT8 GtVoltageMode; + +/** Offset 0x0303 - Maximum GTs turbo ratio override + 0(Default)=Minimal/Auto, 60=Maximum +**/ + UINT8 GtMaxOcRatio; + +/** Offset 0x0304 - The voltage offset applied to GT slice + 0(Default)=Minimal, 1000=Maximum +**/ + UINT16 GtVoltageOffset; + +/** Offset 0x0306 - The GT slice voltage override which is applied to the entire range of GT frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 GtVoltageOverride; + +/** Offset 0x0308 - adaptive voltage applied during turbo frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 GtAdaptiveVoltage; + +/** Offset 0x030A - voltage offset applied to the SA + 0(Default)=Minimal, 1000=Maximum +**/ + UINT16 SaVoltageOffset; + +/** Offset 0x030C - PCIe root port Function number for Hybrid Graphics dGPU + Root port Index number to indicate which PCIe root port has dGPU +**/ + UINT8 RootPortIndex; + +/** Offset 0x030D - Realtime Memory Timing + 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform + realtime memory timing changes after MRC_DONE. + 0: Disabled, 1: Enabled +**/ + UINT8 RealtimeMemoryTiming; + +/** Offset 0x030E - Reserved +**/ + UINT8 Reserved15; + +/** Offset 0x030F - Enable/Disable SA IPU + Enable(Default): Enable SA IPU, Disable: Disable SA IPU + $EN_DIS +**/ + UINT8 SaIpuEnable; + +/** Offset 0x0310 - IMGU CLKOUT Configuration + The configuration of IMGU CLKOUT, 0: Disable;1: Enable. + $EN_DIS +**/ + UINT8 ImguClkOutEn[6]; + +/** Offset 0x0316 - Program GPIOs for LFP on DDI port-A device + 0=Disabled,1(Default)=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortAConfig; + +/** Offset 0x0317 - Program GPIOs for LFP on DDI port-B device + 0(Default)=Disabled,1=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortBConfig; + +/** Offset 0x0318 - Enable or disable HPD of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortAHpd; + +/** Offset 0x0319 - Enable or disable HPD of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBHpd; + +/** Offset 0x031A - Enable or disable HPD of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCHpd; + +/** Offset 0x031B - Enable or disable HPD of DDI port 1 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort1Hpd; + +/** Offset 0x031C - Enable or disable HPD of DDI port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Hpd; + +/** Offset 0x031D - Enable or disable HPD of DDI port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Hpd; + +/** Offset 0x031E - Enable or disable HPD of DDI port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Hpd; + +/** Offset 0x031F - Enable or disable DDC of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortADdc; + +/** Offset 0x0320 - Enable or disable DDC of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBDdc; + +/** Offset 0x0321 - Enable or disable DDC of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCDdc; + +/** Offset 0x0322 - Enable DDC setting of DDI Port 1 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort1Ddc; + +/** Offset 0x0323 - Enable DDC setting of DDI Port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Ddc; + +/** Offset 0x0324 - Enable DDC setting of DDI Port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Ddc; + +/** Offset 0x0325 - Enable DDC setting of DDI Port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Ddc; + +/** Offset 0x0326 - GPIO PIN MUX to choose between GPP_SA and GPP_SD Group. + Default will be 0 for each Display PIN Mux which is GPP_SA Group. (0 = SA GROUP, + 1 = SD GROUP). BIT0 - EDP VDDEN, BIT1 - EDP BKLTEN, BIT2 - EDP BKLTCTRL, BIT3 + - DDI-A, BIT4 - DDI-1/HPD1, BIT5 - DDI-2/HPD2, BIT6 - DDI-3/HPD3, BIT7 - DDI-4/HPD4 +**/ + UINT8 DisplayGpioPinMux; + +/** Offset 0x0327 - Reserved +**/ + UINT8 Reserved16[17]; + +/** Offset 0x0338 - Per-core HT Disable + Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, + 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value + of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have + HT enabled. Range is 0 - 0x7F for max 8 cores. You can only disable up to MAX_CORE_COUNT - 1. +**/ + UINT16 PerCoreHtDisable; + +/** Offset 0x033A - Reserved +**/ + UINT8 Reserved17[6]; + +/** Offset 0x0340 - Thermal Velocity Boost Ratio clipping + 0: Disabled, 1(Default): Enabled. This service controls Core frequency reduction + caused by high package temperatures for processors that implement the Intel Thermal + Velocity Boost (TVB) feature + $EN_DIS +**/ + UINT8 TvbRatioClipping; + +/** Offset 0x0341 - Thermal Velocity Boost voltage optimization + 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations + for processors that implement the Intel Thermal Velocity Boost (TVB) feature. + $EN_DIS +**/ + UINT8 TvbVoltageOptimization; + +/** Offset 0x0342 - Reserved +**/ + UINT8 Reserved18[45]; + +/** Offset 0x036F - DMI Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + UINT8 DmiMaxLinkSpeed; + +/** Offset 0x0370 - PCH DMI Equalization Phase 2 + DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): + AUTO - Use the current default method + 0:Disable phase2, 1:Enable phase2, 2:Auto +**/ + UINT8 PchDmiGen3EqPh2Enable; + +/** Offset 0x0371 - PCH DMI Gen3 Equalization Phase3 + DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + UINT8 PchDmiGen3EqPh3Method; + +/** Offset 0x0372 - Enable/Disable DMI GEN3 Static EQ Phase1 programming + Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static + Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 DmiGen3ProgramStaticEq; + +/** Offset 0x0373 - PCH DMI Gen3 Root port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane +**/ + UINT8 PchDmiGen3RootPortPreset[8]; + +/** Offset 0x037B - PCH DMI Gen3 End port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane +**/ + UINT8 PchDmiGen3EndPointPreset[8]; + +/** Offset 0x0383 - PCH DMI Gen3 End port Hint values per lane + Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + UINT8 PchDmiGen3EndPointHint[8]; + +/** Offset 0x038B - DMI ASPM Configuration:{Combo + Set ASPM Configuration + 0:Disabled, 1:L0s, 2:L1, 3:L1L0s +**/ + UINT8 DmiAspm; + +/** Offset 0x038C - Reserved +**/ + UINT8 Reserved19; + +/** Offset 0x038D - Enable/Disable DMI GEN3 Hardware Eq + Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0): Disable Hardware Eq, Enabled(0x1)(Default): + Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 DmiHweq; + +/** Offset 0x038E - Enable/Disable DMI GEN3 Phase 23 Bypass + DMIGEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): + Enable Phase 23 Bypass + $EN_DIS +**/ + UINT8 Gen3EqPhase23Bypass; + +/** Offset 0x038F - Enable/Disable DMI GEN3 Phase 3 Bypass + DMIGEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): + Enable Phase 3 Bypass + $EN_DIS +**/ + UINT8 Gen3EqPhase3Bypass; + +/** Offset 0x0390 - Enable/Disable DMI Gen3 EQ Local Transmitter Coefficient Override Enable + Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0): Disable Local + Transmitter Coefficient Override, Enabled(0x1)(Default): Enable Local Transmitter + Coefficient Override + $EN_DIS +**/ + UINT8 Gen3LtcoEnable; + +/** Offset 0x0391 - Enable/Disable DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable + Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): + Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote + Transmitter Coefficient/Preset Override + $EN_DIS +**/ + UINT8 Gen3RtcoRtpoEnable; + +/** Offset 0x0392 - DMI Gen3 Transmitter Pre-Cursor Coefficient + Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10, + 2 is default for each lane +**/ + UINT8 DmiGen3Ltcpre[8]; + +/** Offset 0x039A - DMI Gen3 Transmitter Post-Cursor Coefficient + Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default + for each lane +**/ + UINT8 DmiGen3Ltcpo[8]; + +/** Offset 0x03A2 - Reserved +**/ + UINT8 Reserved20[34]; + +/** Offset 0x03C4 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable + Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable, + Manual(0x1): Enable DmiGen3DsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen3DsPresetEnable; + +/** Offset 0x03C5 - DMI Gen3 Root port preset Rx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default + for each lane +**/ + UINT8 DmiGen3DsPortRxPreset[8]; + +/** Offset 0x03CD - DMI Gen3 Root port preset Tx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen3DsPortTxPreset[8]; + +/** Offset 0x03D5 - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable + Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable, + Manual(0x1): Enable DmiGen3UsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen3UsPresetEnable; + +/** Offset 0x03D6 - DMI Gen3 Root port preset Rx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen3UsPortRxPreset[8]; + +/** Offset 0x03DE - DMI Gen3 Root port preset Tx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default + for each lane +**/ + UINT8 DmiGen3UsPortTxPreset[8]; + +/** Offset 0x03E6 - Reserved +**/ + UINT8 Reserved21[54]; + +/** Offset 0x041C - DMI ASPM L1 exit Latency + Range: 0-7, 4 is default L1 exit Latency +**/ + UINT8 DmiAspmL1ExitLatency; + +/** Offset 0x041D - Reserved +**/ + UINT8 Reserved22[63]; + +/** Offset 0x045C - BIST on Reset + Enable/Disable BIST (Built-In Self Test) on reset. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 BistOnReset; + +/** Offset 0x045D - Skip Stop PBET Timer Enable/Disable + Skip Stop PBET Timer; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 SkipStopPbet; + +/** Offset 0x045E - Over clocking support + Over clocking support; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 OcSupport; + +/** Offset 0x045F - Over clocking Lock + Lock Overclocking. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 OcLock; + +/** Offset 0x0460 - Maximum Core Turbo Ratio Override + Maximum core turbo ratio override allows to increase CPU core frequency beyond the + fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 if CoreRatioExtensionMode + is disabled. 0-120 if CoreRatioExtensionMode is enabled. +**/ + UINT8 CoreMaxOcRatio; + +/** Offset 0x0461 - Core voltage mode + Core voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 CoreVoltageMode; + +/** Offset 0x0462 - Maximum clr turbo ratio override + Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the + fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 +**/ + UINT8 RingMaxOcRatio; + +/** Offset 0x0463 - Hyper Threading Enable/Disable + Enable or Disable Hyper-Threading Technology. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 HyperThreading; + +/** Offset 0x0464 - Enable or Disable CPU Ratio Override + Enable/Disable CPU Flex Ratio Programming; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuRatioOverride; + +/** Offset 0x0465 - CPU ratio value + This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio + set by Hardware (HFM). Valid Range 0 to 63. +**/ + UINT8 CpuRatio; + +/** Offset 0x0466 - Reserved +**/ + UINT8 Reserved23; + +/** Offset 0x0467 - Number of active big cores + Number of P-cores to enable in each processor package. Note: Number of P-Cores and + E-Cores are looked at together. When both are {0,0 + 0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores +**/ + UINT8 ActiveCoreCount; + +/** Offset 0x0468 - Processor Early Power On Configuration FCLK setting + FCLK frequency can take values of 400MHz, 800MHz and 1GHz. 0: 800 MHz (ULT/ULX). + 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved + 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved +**/ + UINT8 FClkFrequency; + +/** Offset 0x0469 - Enable or Disable VMX + Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities + provided by Vanderpool Technology. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x046A - AVX2 Ratio Offset + 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio + vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. +**/ + UINT8 Avx2RatioOffset; + +/** Offset 0x046B - AVX3 Ratio Offset + DEPRECATED. 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease + AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. +**/ + UINT8 Avx3RatioOffset; + +/** Offset 0x046C - BCLK Adaptive Voltage Enable + When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: + Disable; 1: Enable + $EN_DIS +**/ + UINT8 BclkAdaptiveVoltage; + +/** Offset 0x046D - Reserved +**/ + UINT8 Reserved24; + +/** Offset 0x046E - core voltage override + The core voltage override which is applied to the entire range of cpu core frequencies. + Valid Range 0 to 2000 +**/ + UINT16 CoreVoltageOverride; + +/** Offset 0x0470 - Core Turbo Adaptive Voltage + Adaptive voltage applied to the cpu core when the cpu is operating in turbo mode. + Valid Range 0 to 2000 +**/ + UINT16 CoreAdaptiveVoltage; + +/** Offset 0x0472 - Core Turbo voltage Offset + The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 +**/ + UINT16 CoreVoltageOffset; + +/** Offset 0x0474 - Core PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 CorePllVoltageOffset; + +/** Offset 0x0475 - Ring Downbin + Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always + lower than the core ratio.0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 RingDownBin; + +/** Offset 0x0476 - Ring voltage mode + Ring voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 RingVoltageMode; + +/** Offset 0x0477 - TjMax Offset + TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support + TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 +**/ + UINT8 TjMaxOffset; + +/** Offset 0x0478 - Ring voltage override + The ring voltage override which is applied to the entire range of cpu ring frequencies. + Valid Range 0 to 2000 +**/ + UINT16 RingVoltageOverride; + +/** Offset 0x047A - Ring Turbo Adaptive Voltage + Adaptive voltage applied to the cpu ring when the cpu is operating in turbo mode. + Valid Range 0 to 2000 +**/ + UINT16 RingAdaptiveVoltage; + +/** Offset 0x047C - Ring Turbo voltage Offset + The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 +**/ + UINT16 RingVoltageOffset; + +/** Offset 0x047E - Enable or Disable TME + Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks. + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TmeEnable; + +/** Offset 0x047F - Enable CPU CrashLog + Enable or Disable CPU CrashLog; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuCrashLogEnable; + +/** Offset 0x0480 - CPU Run Control + Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: + No Change + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 DebugInterfaceEnable; + +/** Offset 0x0481 - CPU Run Control Lock + Lock or Unlock CPU Run Control; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DebugInterfaceLockEnable; + +/** Offset 0x0482 - Reserved +**/ + UINT8 Reserved25[67]; + +/** Offset 0x04C5 - Core VF Point Offset Mode + Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes. + In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, + setting a selected VF point; 0: Legacy; 1: Selection. + 0:Legacy, 1:Selection +**/ + UINT8 CoreVfPointOffsetMode; + +/** Offset 0x04C6 - Core VF Point Offset + Array used to specifies the Core Voltage Offset applied to the each selected VF + Point. This voltage is specified in millivolts. +**/ + UINT16 CoreVfPointOffset[15]; + +/** Offset 0x04E4 - Core VF Point Offset Prefix + Sets the CoreVfPointOffset value as positive or negative for corresponding core + VF Point; 0: Positive ; 1: Negative. + 0:Positive, 1:Negative +**/ + UINT8 CoreVfPointOffsetPrefix[15]; + +/** Offset 0x04F3 - Core VF Point Ratio + Array for the each selected Core VF Point to display the ration. +**/ + UINT8 CoreVfPointRatio[15]; + +/** Offset 0x0502 - Core VF Point Count + Number of supported Core Voltage & Frequency Point Offset +**/ + UINT8 CoreVfPointCount; + +/** Offset 0x0503 - Reserved +**/ + UINT8 Reserved26[25]; + +/** Offset 0x051C - Per Core Max Ratio override + Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new + favored core ratio to each Core. 0: Disable, 1: enable + $EN_DIS +**/ + UINT8 PerCoreRatioOverride; + +/** Offset 0x051D - Reserved +**/ + UINT8 Reserved27[41]; + +/** Offset 0x0546 - Per Core Current Max Ratio + Array for the Per Core Max Ratio +**/ + UINT8 PerCoreRatio[8]; + +/** Offset 0x054E - Reserved +**/ + UINT8 Reserved28[54]; + +/** Offset 0x0584 - Margin Limit Check + Margin Limit Check. Choose level of margin check + 0:Disable, 1:L1, 2:L2, 3:Both +**/ + UINT8 MarginLimitCheck; + +/** Offset 0x0585 - Reserved +**/ + UINT8 Reserved29[14]; + +/** Offset 0x0593 - Pvd Ratio Threshold for SOC/CPU die + Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio + (P0 to Pn) to select the multiplier so that the output is within the DCO frequency + range. As per the die selected, this threshold is applied to SA and MC/CMI PLL + for SOC die and SA, Ring and Atom PLL for CPU die. Range 0-63. When the threshold + is 0, static PVD ratio is selected based on the PVD Mode for SOC. 0: Default. +**/ + UINT8 PvdRatioThreshold[2]; + +/** Offset 0x0595 - Reserved +**/ + UINT8 Reserved30[68]; + +/** Offset 0x05D9 - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO + configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for use +**/ + UINT8 GpioOverride; + +/** Offset 0x05DA - Reserved +**/ + UINT8 Reserved31[10]; + +/** Offset 0x05E4 - CPU BCLK OC Frequency + CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz 0 - Auto. Range is + 40Mhz-1000Mhz. +**/ + UINT32 CpuBclkOcFrequency; + +/** Offset 0x05E8 - Reserved +**/ + UINT8 Reserved32[4]; + +/** Offset 0x05EC - Enable CPU CrashLog GPRs dump + Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only + disable Smm GPRs dump + 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled +**/ + UINT8 CrashLogGprs; + +/** Offset 0x05ED - Reserved +**/ + UINT8 Reserved33[142]; + +/** Offset 0x067B - Acoustic Noise Mitigation feature + Enabling this option will help mitigate acoustic noise on certain SKUs when the + CPU is in deeper C state. 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 AcousticNoiseMitigation; + +/** Offset 0x067C - Reserved +**/ + UINT8 Reserved34[2]; + +/** Offset 0x067E - Platform Power Pmax + PSYS PMax power, defined in 1/8 Watt increments. 0 - Auto Specified in 1/8 + Watt increments. Range 0-1024 Watts(0-8191). Value of 800 = 100W +**/ + UINT16 PsysPmax; + +/** Offset 0x0680 - Reserved +**/ + UINT8 Reserved35[12]; + +/** Offset 0x068C - AcLoadline + AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 + mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 AcLoadline[6]; + +/** Offset 0x0698 - DcLoadline + DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 + mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 DcLoadline[6]; + +/** Offset 0x06A4 - Power State 1 Threshold current + PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range + 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT16 Psi1Threshold[6]; + +/** Offset 0x06B0 - Power State 2 Threshold current + PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range + 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT16 Psi2Threshold[6]; + +/** Offset 0x06BC - Power State 3 Threshold current + PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range + 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, + [3] through [5] are Reserved. +**/ + UINT16 Psi3Threshold[6]; + +/** Offset 0x06C8 - Reserved +**/ + UINT8 Reserved36[54]; + +/** Offset 0x06FE - Thermal Design Current enable/disable + Thermal Design Current enable/disable; 0: Disable; 1: Enable. [0] for IA, + [1] for GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT8 TdcEnable[6]; + +/** Offset 0x0704 - Thermal Design Current time window + TDC Time Window, value of IA either in milliseconds or seconds, value of GT/SA is + in milliseconds. 1ms is default. Range of IA from 1ms to 448s, Range of GT/SA is + 1ms to 10ms, except for 9ms. 9ms has no valid encoding in the MSR definition. +**/ + UINT32 TdcTimeWindow[6]; + +/** Offset 0x071C - Reserved +**/ + UINT8 Reserved37[128]; + +/** Offset 0x079C - Disable Fast Slew Rate for Deep Package C States for VR domains + This option needs to be configured to reduce acoustic noise during deeper C states. + False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp + during deeper C state. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are + Reserved. 0: False; 1: True + $EN_DIS +**/ + UINT8 FastPkgCRampDisable[6]; + +/** Offset 0x07A2 - Slew Rate configuration for Deep Package C States for VR domains + Set VR IA/GT/SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate + equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew + rate to help minimize acoustic noise; divide by 16 is disabled for GT/SA. 0: + Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16; 0xFF: Ignore the configuration + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16, 0xFF: Ignore the configuration +**/ + UINT8 SlowSlewRate[6]; + +/** Offset 0x07A8 - Reserved +**/ + UINT8 Reserved38[26]; + +/** Offset 0x07C2 - VR Fast Vmode ICC Limit support + Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds + to feature disabled (no reactive protection). This value represents the current + threshold where the VR would initiate reactive protection if Fast Vmode is enabled. + The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 IccLimit[6]; + +/** Offset 0x07CE - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. + Enable/Disable VR FastVmode; 0: Disable; 1: Enable. For all VR by domain + 0: Disable, 1: Enable +**/ + UINT8 EnableFastVmode[6]; + +/** Offset 0x07D4 - Enable CEP + Enable/Disable CEP (Current Excursion Protection) Support. 0: Disable; 1: Enable. + [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. + $EN_DIS +**/ + UINT8 CepEnable[6]; + +/** Offset 0x07DA - Reserved +**/ + UINT8 Reserved39[146]; + +/** Offset 0x086C - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x086D +**/ + UINT8 BiosGuardToolsInterface; + +/** Offset 0x086E - Txt + Enables utilization of additional hardware capabilities provided by Intel (R) Trusted + Execution Technology. Changes require a full power cycle to take effect. 0: + Disable, 1: Enable + $EN_DIS +**/ + UINT8 Txt; + +/** Offset 0x086F - Reserved +**/ + UINT8 Reserved40; + +/** Offset 0x0870 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x0874 - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x0878 - Reserved +**/ + UINT8 Reserved41[8]; + +/** Offset 0x0880 - TxtDprMemoryBase + Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable +**/ + UINT64 TxtDprMemoryBase; + +/** Offset 0x0888 - TxtHeapMemorySize + Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable +**/ + UINT32 TxtHeapMemorySize; + +/** Offset 0x088C - TxtDprMemorySize + Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize + , 1: enable +**/ + UINT32 TxtDprMemorySize; + +/** Offset 0x0890 - BiosAcmBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT32 BiosAcmBase; + +/** Offset 0x0894 - BiosAcmSize + Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable +**/ + UINT32 BiosAcmSize; + +/** Offset 0x0898 - ApStartupBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT32 ApStartupBase; + +/** Offset 0x089C - TgaSize + Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable +**/ + UINT32 TgaSize; + +/** Offset 0x08A0 - TxtLcpPdBase + Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable +**/ + UINT64 TxtLcpPdBase; + +/** Offset 0x08A8 - TxtLcpPdSize + Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable +**/ + UINT64 TxtLcpPdSize; + +/** Offset 0x08B0 - IsTPMPresence + IsTPMPresence default values +**/ + UINT8 IsTPMPresence; + +/** Offset 0x08B1 - Reserved +**/ + UINT8 Reserved42[32]; + +/** Offset 0x08D1 - Enable PCH HSIO PCIE Rx Set Ctle + Enable PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtleEnable[28]; + +/** Offset 0x08ED - PCH HSIO PCIE Rx Set Ctle Value + PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtle[28]; + +/** Offset 0x0909 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28]; + +/** Offset 0x0925 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmp[28]; + +/** Offset 0x0941 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28]; + +/** Offset 0x095D - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmp[28]; + +/** Offset 0x0979 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28]; + +/** Offset 0x0995 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmp[28]; + +/** Offset 0x09B1 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DeEmphEnable[28]; + +/** Offset 0x09CD - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value + PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen1DeEmph[28]; + +/** Offset 0x09E9 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28]; + +/** Offset 0x0A05 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5[28]; + +/** Offset 0x0A21 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28]; + +/** Offset 0x0A3D - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0[28]; + +/** Offset 0x0A59 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; + +/** Offset 0x0A61 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen1EqBoostMag[8]; + +/** Offset 0x0A69 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; + +/** Offset 0x0A71 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen2EqBoostMag[8]; + +/** Offset 0x0A79 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; + +/** Offset 0x0A81 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen3EqBoostMag[8]; + +/** Offset 0x0A89 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; + +/** Offset 0x0A91 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen1DownscaleAmp[8]; + +/** Offset 0x0A99 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; + +/** Offset 0x0AA1 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen2DownscaleAmp[8]; + +/** Offset 0x0AA9 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; + +/** Offset 0x0AB1 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen3DownscaleAmp[8]; + +/** Offset 0x0AB9 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen1DeEmphEnable[8]; + +/** Offset 0x0AC1 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen1DeEmph[8]; + +/** Offset 0x0AC9 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen2DeEmphEnable[8]; + +/** Offset 0x0AD1 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen2DeEmph[8]; + +/** Offset 0x0AD9 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen3DeEmphEnable[8]; + +/** Offset 0x0AE1 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen3DeEmph[8]; + +/** Offset 0x0AE9 - PCH LPC Enhance the port 8xh decoding + Original LPC only decodes one byte of port 80h. + $EN_DIS +**/ + UINT8 PchLpcEnhancePort8xhDecoding; + +/** Offset 0x0AEA - PCH Port80 Route + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + $EN_DIS +**/ + UINT8 PchPort80Route; + +/** Offset 0x0AEB - Enable SMBus ARP support + Enable SMBus ARP support. + $EN_DIS +**/ + UINT8 SmbusArpEnable; + +/** Offset 0x0AEC - Number of RsvdSmbusAddressTable. + The number of elements in the RsvdSmbusAddressTable. +**/ + UINT8 PchNumRsvdSmbusAddresses; + +/** Offset 0x0AED - Reserved +**/ + UINT8 Reserved43; + +/** Offset 0x0AEE - SMBUS Base Address + SMBUS Base Address (IO space). +**/ + UINT16 PchSmbusIoBase; + +/** Offset 0x0AF0 - Enable SMBus Alert Pin + Enable SMBus Alert Pin. + $EN_DIS +**/ + UINT8 PchSmbAlertEnable; + +/** Offset 0x0AF1 - Usage type for SOC/IOE ClkSrc + 0-23: PCIe rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[16]; + +/** Offset 0x0B01 - Reserved +**/ + UINT8 Reserved44[16]; + +/** Offset 0x0B11 - SOC/IOE ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PcieClkSrcClkReq[16]; + +/** Offset 0x0B21 - Reserved +**/ + UINT8 Reserved45[55]; + +/** Offset 0x0B58 - Enable PCH PCIE RP Mask + Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port, + bit0 for port1, bit1 for port2, and so on. +**/ + UINT32 PchPcieRpEnableMask; + +/** Offset 0x0B5C - Enable SOC/IOE PCIE RP Mask + Enable/disable SOC/IOE PCIE Root Ports. 0: disable, 1: enable. One bit for each + port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT16 PcieRpEnableMask; + +/** Offset 0x0B5E - VC Type + Virtual Channel Type Select: 0: VC0, 1: VC1. + 0: VC0, 1: VC1 +**/ + UINT8 PchHdaVcType; + +/** Offset 0x0B5F - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 PchHdaDspUaaCompliance; + +/** Offset 0x0B60 - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHdaEnable; + +/** Offset 0x0B61 - Enable HDA SDI lanes + Enable/disable HDA SDI lanes. +**/ + UINT8 PchHdaSdiEnable[2]; + +/** Offset 0x0B63 - HDA Power/Clock Gating (PGD/CGD) + Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: + FORCE_ENABLE, 2: FORCE_DISABLE. + 0: POR, 1: Force Enable, 2: Force Disable +**/ + UINT8 PchHdaTestPowerClockGating; + +/** Offset 0x0B64 - Enable HD Audio DMIC_N Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. +**/ + UINT8 PchHdaAudioLinkDmicEnable[2]; + +/** Offset 0x0B66 - Reserved +**/ + UINT8 Reserved46[2]; + +/** Offset 0x0B68 - DMIC<N> ClkA Pin Muxing (N - DMIC number) + Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* +**/ + UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; + +/** Offset 0x0B70 - DMIC<N> ClkB Pin Muxing + Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_* +**/ + UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; + +/** Offset 0x0B78 - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x0B79 - Reserved +**/ + UINT8 Reserved47[3]; + +/** Offset 0x0B7C - DMIC<N> Data Pin Muxing + Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* +**/ + UINT32 PchHdaAudioLinkDmicDataPinMux[2]; + +/** Offset 0x0B84 - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 +**/ + UINT8 PchHdaAudioLinkSspEnable[6]; + +/** Offset 0x0B8A - Enable HD Audio SoundWire#N Link + Enable/disable HD Audio SNDW#N link. Muxed with HDA. +**/ + UINT8 PchHdaAudioLinkSndwEnable[4]; + +/** Offset 0x0B8E - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. + 4: 96MHz, 3: 48MHz +**/ + UINT8 PchHdaIDispLinkFrequency; + +/** Offset 0x0B8F - Reserved +**/ + UINT8 Reserved48; + +/** Offset 0x0B90 - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T + 0: 2T, 2: 4T, 3: 8T, 4: 16T +**/ + UINT8 PchHdaIDispLinkTmode; + +/** Offset 0x0B91 - iDisplay Audio Codec disconnection + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + $EN_DIS +**/ + UINT8 PchHdaIDispCodecDisconnect; + +/** Offset 0x0B92 - Reserved +**/ + UINT8 Reserved49[6]; + +/** Offset 0x0B98 - CNVi DDR RFI Mitigation + Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviDdrRfim; + +/** Offset 0x0B99 - Reserved +**/ + UINT8 Reserved50[11]; + +/** Offset 0x0BA4 - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x0BA5 - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x0BA6 - Serial Io Uart Debug Auto Flow + Enables UART hardware flow control, CTS and RTS lines. + $EN_DIS +**/ + UINT8 SerialIoUartDebugAutoFlow; + +/** Offset 0x0BA7 - Reserved +**/ + UINT8 Reserved51; + +/** Offset 0x0BA8 - Serial Io Uart Debug BaudRate + Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, + 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 +**/ + UINT32 SerialIoUartDebugBaudRate; + +/** Offset 0x0BAC - Serial Io Uart Debug Parity + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartDebugParity; + +/** Offset 0x0BAD - Serial Io Uart Debug Stop Bits + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 SerialIoUartDebugStopBits; + +/** Offset 0x0BAE - Serial Io Uart Debug Data Bits + Set default word length. 0: Default, 5,6,7,8 + 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS +**/ + UINT8 SerialIoUartDebugDataBits; + +/** Offset 0x0BAF - Reserved +**/ + UINT8 Reserved52; + +/** Offset 0x0BB0 - Serial Io Uart Debug Mmio Base + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode + = SerialIoUartPci. +**/ + UINT32 SerialIoUartDebugMmioBase; + +/** Offset 0x0BB4 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x0BB5 - Reserved +**/ + UINT8 Reserved53; + +/** Offset 0x0BB6 - Ring PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 RingPllVoltageOffset; + +/** Offset 0x0BB7 - System Agent PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 SaPllVoltageOffset; + +/** Offset 0x0BB8 - Reserved +**/ + UINT8 Reserved54; + +/** Offset 0x0BB9 - Memory Controller PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 McPllVoltageOffset; + +/** Offset 0x0BBA - TCSS Thunderbolt PCIE Root Port 0 Enable + Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie0En; + +/** Offset 0x0BBB - TCSS Thunderbolt PCIE Root Port 1 Enable + Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie1En; + +/** Offset 0x0BBC - TCSS Thunderbolt PCIE Root Port 2 Enable + Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie2En; + +/** Offset 0x0BBD - TCSS Thunderbolt PCIE Root Port 3 Enable + Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie3En; + +/** Offset 0x0BBE - TCSS USB HOST (xHCI) Enable + Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below + $EN_DIS +**/ + UINT8 TcssXhciEn; + +/** Offset 0x0BBF - TCSS USB DEVICE (xDCI) Enable + Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled + $EN_DIS +**/ + UINT8 TcssXdciEn; + +/** Offset 0x0BC0 - TCSS DMA0 Enable + Set TCSS DMA0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma0En; + +/** Offset 0x0BC1 - TCSS DMA1 Enable + Set TCSS DMA1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma1En; + +/** Offset 0x0BC2 - PcdSerialDebugBaudRate + Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. + 3:9600, 4:19200, 6:56700, 7:115200 +**/ + UINT8 PcdSerialDebugBaudRate; + +/** Offset 0x0BC3 - HobBufferSize + Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB + total HOB size). + 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value +**/ + UINT8 HobBufferSize; + +/** Offset 0x0BC4 - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x0BC5 - SenseAmp Offset Training + Enables/Disable SenseAmp Offset Training + $EN_DIS +**/ + UINT8 SOT; + +/** Offset 0x0BC6 - Early ReadMPR Timing Centering 2D + Enables/Disable Early ReadMPR Timing Centering 2D + $EN_DIS +**/ + UINT8 ERDMPRTC2D; + +/** Offset 0x0BC7 - Read MPR Training + Enables/Disable Read MPR Training + $EN_DIS +**/ + UINT8 RDMPRT; + +/** Offset 0x0BC8 - Receive Enable Training + Enables/Disable Receive Enable Training + $EN_DIS +**/ + UINT8 RCVET; + +/** Offset 0x0BC9 - Jedec Write Leveling + Enables/Disable Jedec Write Leveling + $EN_DIS +**/ + UINT8 JWRL; + +/** Offset 0x0BCA - Early Write Time Centering 2D + Enables/Disable Early Write Time Centering 2D + $EN_DIS +**/ + UINT8 EWRTC2D; + +/** Offset 0x0BCB - Early Read Time Centering 2D + Enables/Disable Early Read Time Centering 2D + $EN_DIS +**/ + UINT8 ERDTC2D; + +/** Offset 0x0BCC - Reserved +**/ + UINT8 Reserved55; + +/** Offset 0x0BCD - Write Timing Centering 1D + Enables/Disable Write Timing Centering 1D + $EN_DIS +**/ + UINT8 WRTC1D; + +/** Offset 0x0BCE - Write Voltage Centering 1D + Enables/Disable Write Voltage Centering 1D + $EN_DIS +**/ + UINT8 WRVC1D; + +/** Offset 0x0BCF - Read Timing Centering 1D + Enables/Disable Read Timing Centering 1D + $EN_DIS +**/ + UINT8 RDTC1D; + +/** Offset 0x0BD0 - Read Voltage Centering 1D + Enable/Disable Read Voltage Centering 1D + $EN_DIS +**/ + UINT8 RDVC1D; + +/** Offset 0x0BD1 - Reserved +**/ + UINT8 Reserved56[10]; + +/** Offset 0x0BDB - Read Equalization Training + Enables/Disable Read Equalization Training + $EN_DIS +**/ + UINT8 RDEQT; + +/** Offset 0x0BDC - Reserved +**/ + UINT8 Reserved57[2]; + +/** Offset 0x0BDE - Write Timing Centering 2D + Enables/Disable Write Timing Centering 2D + $EN_DIS +**/ + UINT8 WRTC2D; + +/** Offset 0x0BDF - Read Timing Centering 2D + Enables/Disable Read Timing Centering 2D + $EN_DIS +**/ + UINT8 RDTC2D; + +/** Offset 0x0BE0 - Write Voltage Centering 2D + Enables/Disable Write Voltage Centering 2D + $EN_DIS +**/ + UINT8 WRVC2D; + +/** Offset 0x0BE1 - Read Voltage Centering 2D + Enables/Disable Read Voltage Centering 2D + $EN_DIS +**/ + UINT8 RDVC2D; + +/** Offset 0x0BE2 - Reserved +**/ + UINT8 Reserved58; + +/** Offset 0x0BE3 - Command Voltage Centering + Enables/Disable Command Voltage Centering + $EN_DIS +**/ + UINT8 CMDVC; + +/** Offset 0x0BE4 - Late Command Training + Enables/Disable Late Command Training + $EN_DIS +**/ + UINT8 LCT; + +/** Offset 0x0BE5 - Turn Around Timing Training + Enables/Disable Turn Around Timing Training + $EN_DIS +**/ + UINT8 TAT; + +/** Offset 0x0BE6 - Rank Margin Tool + Enable/disable Rank Margin Tool + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x0BE7 - Reserved +**/ + UINT8 Reserved59; + +/** Offset 0x0BE8 - DIMM SPD Alias Test + Enables/Disable DIMM SPD Alias Test + $EN_DIS +**/ + UINT8 ALIASCHK; + +/** Offset 0x0BE9 - Retrain Margin Check + Enables/Disable Retrain Margin Check + $EN_DIS +**/ + UINT8 RMC; + +/** Offset 0x0BEA - Row Hammering Prevention + Enables/Disable Row Hammering Prevention + $EN_DIS +**/ + UINT8 ROWHAMMER; + +/** Offset 0x0BEB - Dimm ODT Training + Enables/Disable Dimm ODT Training + $EN_DIS +**/ + UINT8 DIMMODTT; + +/** Offset 0x0BEC - DIMM RON Training + Enables/Disable DIMM RON Training + $EN_DIS +**/ + UINT8 DIMMRONT; + +/** Offset 0x0BED - TxDqTCO Comp Training + Enable/Disable TxDqTCO Comp Training + $EN_DIS +**/ + UINT8 TXTCO; + +/** Offset 0x0BEE - ClkTCO Comp Training + Enable/Disable ClkTCO Comp Training + $EN_DIS +**/ + UINT8 CLKTCO; + +/** Offset 0x0BEF - CMD Slew Rate Training + Enable/Disable CMD Slew Rate Training + $EN_DIS +**/ + UINT8 CMDSR; + +/** Offset 0x0BF0 - Reserved +**/ + UINT8 Reserved60[2]; + +/** Offset 0x0BF2 - DIMM CA ODT Training + Enable/Disable DIMM CA ODT Training + $EN_DIS +**/ + UINT8 DIMMODTCA; + +/** Offset 0x0BF3 - Reserved +**/ + UINT8 Reserved61[3]; + +/** Offset 0x0BF6 - Read Vref Decap Training + Enable/Disable Read Vref Decap Training + $EN_DIS +**/ + UINT8 RDVREFDC; + +/** Offset 0x0BF7 - Vddq Training + Enable/Disable Vddq Training + $EN_DIS +**/ + UINT8 VDDQT; + +/** Offset 0x0BF8 - Rank Margin Tool Per Bit + Enable/Disable Rank Margin Tool Per Bit + $EN_DIS +**/ + UINT8 RMTBIT; + +/** Offset 0x0BF9 - Reserved +**/ + UINT8 Reserved62[4]; + +/** Offset 0x0BFD - Duty Cycle Correction Training + Enable/Disable Duty Cycle Correction Training + $EN_DIS +**/ + UINT8 DCC; + +/** Offset 0x0BFE - Reserved +**/ + UINT8 Reserved63[17]; + +/** Offset 0x0C0F - ECC Support + Enables/Disable ECC Support + $EN_DIS +**/ + UINT8 EccSupport; + +/** Offset 0x0C10 - Ibecc + In-Band ECC Support + $EN_DIS +**/ + UINT8 Ibecc; + +/** Offset 0x0C11 - IbeccParity + In-Band ECC Parity Control + $EN_DIS +**/ + UINT8 IbeccParity; + +/** Offset 0x0C12 - IbeccOperationMode + In-Band ECC Operation Mode + 0:Protect base on address range, 1: Non-protected, 2: All protected +**/ + UINT8 IbeccOperationMode; + +/** Offset 0x0C13 - IbeccProtectedRegionEnable + In-Band ECC Protected Region Enable + $EN_DIS +**/ + UINT8 IbeccProtectedRegionEnable[8]; + +/** Offset 0x0C1B - Reserved +**/ + UINT8 Reserved64; + +/** Offset 0x0C1C - IbeccProtectedRegionBases + IBECC Protected Region Bases per IBECC instance +**/ + UINT16 IbeccProtectedRegionBase[8]; + +/** Offset 0x0C2C - IbeccProtectedRegionMasks + IBECC Protected Region Masks +**/ + UINT16 IbeccProtectedRegionMask[8]; + +/** Offset 0x0C3C - IbeccProtectedRegionOverallBases + IBECC Protected Region Bases based on enabled IBECC instance +**/ + UINT16 IbeccProtectedRegionOverallBase[8]; + +/** Offset 0x0C4C - Memory Remap + Enables/Disable Memory Remap + $EN_DIS +**/ + UINT8 RemapEnable; + +/** Offset 0x0C4D - Rank Interleave support + Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at + the same time. + $EN_DIS +**/ + UINT8 RankInterleave; + +/** Offset 0x0C4E - Enhanced Interleave support + Enables/Disable Enhanced Interleave support + $EN_DIS +**/ + UINT8 EnhancedInterleave; + +/** Offset 0x0C4F - Ch Hash Support + Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode + $EN_DIS +**/ + UINT8 ChHashEnable; + +/** Offset 0x0C50 - Extern Therm Status + Enables/Disable Extern Therm Status + $EN_DIS +**/ + UINT8 EnableExtts; + +/** Offset 0x0C51 - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDn; + +/** Offset 0x0C52 - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDnLpddr; + +/** Offset 0x0C53 - SelfRefresh Enable + Enables/Disable SelfRefresh Enable + $EN_DIS +**/ + UINT8 SrefCfgEna; + +/** Offset 0x0C54 - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeatLpddr; + +/** Offset 0x0C55 - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeat; + +/** Offset 0x0C56 - Row Hammer Select + Row Hammer Select + 0:Disable, 1:RFM, 2:pTRR +**/ + UINT8 RhSelect; + +/** Offset 0x0C57 - Exit On Failure (MRC) + Enables/Disable Exit On Failure (MRC) + $EN_DIS +**/ + UINT8 ExitOnFailure; + +/** Offset 0x0C58 - Reserved +**/ + UINT8 Reserved65[4]; + +/** Offset 0x0C5C - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP + ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP + $EN_DIS +**/ + UINT8 Ddr4DdpSharedZq; + +/** Offset 0x0C5D - Ch Hash Interleaved Bit + Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave + the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 + 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 +**/ + UINT8 ChHashInterleaveBit; + +/** Offset 0x0C5E - Ch Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x30CC +**/ + UINT16 ChHashMask; + +/** Offset 0x0C60 - Base reference clock value + Base reference clock value, in Hertz(Default is 125Hz) + 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz +**/ + UINT32 BClkFrequency; + +/** Offset 0x0C64 - EPG DIMM Idd3N + Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on + a per DIMM basis. Default is 26 +**/ + UINT16 Idd3n; + +/** Offset 0x0C66 - EPG DIMM Idd3P + Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated + on a per DIMM basis. Default is 11 +**/ + UINT16 Idd3p; + +/** Offset 0x0C68 - CMD Normalization + Enable/Disable CMD Normalization + $EN_DIS +**/ + UINT8 CMDNORM; + +/** Offset 0x0C69 - Early DQ Write Drive Strength and Equalization Training + Enable/Disable Early DQ Write Drive Strength and Equalization Training + $EN_DIS +**/ + UINT8 EWRDSEQ; + +/** Offset 0x0C6A - Idle Energy Mc0Ch0Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch0Dimm0; + +/** Offset 0x0C6B - Idle Energy Mc0Ch0Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch0Dimm1; + +/** Offset 0x0C6C - Idle Energy Mc0Ch1Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch1Dimm0; + +/** Offset 0x0C6D - Idle Energy Mc0Ch1Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch1Dimm1; + +/** Offset 0x0C6E - Idle Energy Mc1Ch0Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch0Dimm0; + +/** Offset 0x0C6F - Idle Energy Mc1Ch0Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch0Dimm1; + +/** Offset 0x0C70 - Idle Energy Mc1Ch1Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch1Dimm0; + +/** Offset 0x0C71 - Idle Energy Mc1Ch1Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch1Dimm1; + +/** Offset 0x0C72 - PowerDown Energy Mc0Ch0Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch0Dimm0; + +/** Offset 0x0C73 - PowerDown Energy Mc0Ch0Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch0Dimm1; + +/** Offset 0x0C74 - PowerDown Energy Mc0Ch1Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch1Dimm0; + +/** Offset 0x0C75 - PowerDown Energy Mc0Ch1Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch1Dimm1; + +/** Offset 0x0C76 - PowerDown Energy Mc1Ch0Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch0Dimm0; + +/** Offset 0x0C77 - PowerDown Energy Mc1Ch0Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch0Dimm1; + +/** Offset 0x0C78 - PowerDown Energy Mc1Ch1Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch1Dimm0; + +/** Offset 0x0C79 - PowerDown Energy Mc1Ch1Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch1Dimm1; + +/** Offset 0x0C7A - Activate Energy Mc0Ch0Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch0Dimm0; + +/** Offset 0x0C7B - Activate Energy Mc0Ch0Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch0Dimm1; + +/** Offset 0x0C7C - Activate Energy Mc0Ch1Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch1Dimm0; + +/** Offset 0x0C7D - Activate Energy Mc0Ch1Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch1Dimm1; + +/** Offset 0x0C7E - Activate Energy Mc1Ch0Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch0Dimm0; + +/** Offset 0x0C7F - Activate Energy Mc1Ch0Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch0Dimm1; + +/** Offset 0x0C80 - Activate Energy Mc1Ch1Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch1Dimm0; + +/** Offset 0x0C81 - Activate Energy Mc1Ch1Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch1Dimm1; + +/** Offset 0x0C82 - Read Energy Mc0Ch0Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch0Dimm0; + +/** Offset 0x0C83 - Read Energy Mc0Ch0Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch0Dimm1; + +/** Offset 0x0C84 - Read Energy Mc0Ch1Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch1Dimm0; + +/** Offset 0x0C85 - Read Energy Mc0Ch1Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch1Dimm1; + +/** Offset 0x0C86 - Read Energy Mc1Ch0Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch0Dimm0; + +/** Offset 0x0C87 - Read Energy Mc1Ch0Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch0Dimm1; + +/** Offset 0x0C88 - Read Energy Mc1Ch1Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch1Dimm0; + +/** Offset 0x0C89 - Read Energy Mc1Ch1Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch1Dimm1; + +/** Offset 0x0C8A - Write Energy Mc0Ch0Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch0Dimm0; + +/** Offset 0x0C8B - Write Energy Mc0Ch0Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch0Dimm1; + +/** Offset 0x0C8C - Write Energy Mc0Ch1Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch1Dimm0; + +/** Offset 0x0C8D - Write Energy Mc0Ch1Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch1Dimm1; + +/** Offset 0x0C8E - Write Energy Mc1Ch0Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch0Dimm0; + +/** Offset 0x0C8F - Write Energy Mc1Ch0Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch0Dimm1; + +/** Offset 0x0C90 - Write Energy Mc1Ch1Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch1Dimm0; + +/** Offset 0x0C91 - Write Energy Mc1Ch1Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch1Dimm1; + +/** Offset 0x0C92 - Throttler CKEMin Timer + Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). + Dfault is 0x00 +**/ + UINT8 ThrtCkeMinTmr; + +/** Offset 0x0C93 - Reserved +**/ + UINT8 Reserved66[2]; + +/** Offset 0x0C95 - Rapl Power Floor Ch0 + Power budget ,range[255;0],(0= 5.3W Def) +**/ + UINT8 RaplPwrFlCh0; + +/** Offset 0x0C96 - Rapl Power Floor Ch1 + Power budget ,range[255;0],(0= 5.3W Def) +**/ + UINT8 RaplPwrFlCh1; + +/** Offset 0x0C97 - Command Rate Support + CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs + 0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS +**/ + UINT8 EnCmdRate; + +/** Offset 0x0C98 - MC_REFRESH_RATE + Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh + 0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh +**/ + UINT8 McRefreshRate; + +/** Offset 0x0C99 - Energy Performance Gain + Enable/disable Energy Performance Gain. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EpgEnable; + +/** Offset 0x0C9A - RH pTRR LFSR0 Mask + Row Hammer pTRR LFSR0 Mask, 1/2^(value) +**/ + UINT8 Lfsr0Mask; + +/** Offset 0x0C9B - User Manual Threshold + Disabled: Predefined threshold will be used.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserThresholdEnable; + +/** Offset 0x0C9C - User Manual Budget + Disabled: Configuration of memories will defined the Budget value.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserBudgetEnable; + +/** Offset 0x0C9D - Reserved +**/ + UINT8 Reserved67; + +/** Offset 0x0C9E - Power Down Mode + This option controls command bus tristating during idle periods + 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto +**/ + UINT8 PowerDownMode; + +/** Offset 0x0C9F - Pwr Down Idle Timer + The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means + AUTO: 64 for ULX/ULT, 128 for DT/Halo +**/ + UINT8 PwdwnIdleCounter; + +/** Offset 0x0CA0 - Page Close Idle Timeout + This option controls Page Close Idle Timeout + 0:Enabled, 1:Disabled +**/ + UINT8 DisPgCloseIdleTimeout; + +/** Offset 0x0CA1 - Bitmask of ranks that have CA bus terminated + Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, + Rank0 is terminating and Rank1 is non-terminating +**/ + UINT8 CmdRanksTerminated; + +/** Offset 0x0CA2 - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x0CA3 - Reserved +**/ + UINT8 Reserved68[8]; + +/** Offset 0x0CAB - Ask MRC to clear memory content + Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. + $EN_DIS +**/ + UINT8 CleanMemory; + +/** Offset 0x0CAC - TCSS USB Port Enable + Bitmap for per port enabling +**/ + UINT8 UsbTcPortEnPreMem; + +/** Offset 0x0CAD - Reserved +**/ + UINT8 Reserved69; + +/** Offset 0x0CAE - Post Code Output Port + This option configures Post Code Output Port +**/ + UINT16 PostCodeOutputPort; + +/** Offset 0x0CB0 - RMTLoopCount + Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO +**/ + UINT8 RMTLoopCount; + +/** Offset 0x0CB1 - Enable/Disable SA CRID + Enable: SA CRID, Disable (Default): SA CRID + $EN_DIS +**/ + UINT8 CridEnable; + +/** Offset 0x0CB2 - Reserved +**/ + UINT8 Reserved70[2]; + +/** Offset 0x0CB4 - BCLK RFI Frequency + Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No + RFI Tuning. Range is 98Mhz-100Mhz. +**/ + UINT32 BclkRfiFreq[4]; + +/** Offset 0x0CC4 - Size of PCIe IMR. + Size of PCIe IMR in megabytes +**/ + UINT16 PcieImrSize; + +/** Offset 0x0CC6 - Enable PCIe IMR + 0: Disable(AUTO), 1: Enable + $EN_DIS +**/ + UINT8 PcieImrEnabled; + +/** Offset 0x0CC7 - Enable PCIe IMR + 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select + the Root port location from PCH PCIe or SA PCIe + $EN_DIS +**/ + UINT8 PcieImrRpLocation; + +/** Offset 0x0CC8 - Root port number for IMR. + Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port + from 0 to 23 and if it is SA PCIe then select root port from 0 to 3 +**/ + UINT8 PcieImrRpSelection; + +/** Offset 0x0CC9 - SerialDebugMrcLevel + MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 SerialDebugMrcLevel; + +/** Offset 0x0CCA - Reserved +**/ + UINT8 Reserved71[11]; + +/** Offset 0x0CD5 - RH pTRR LFSR1 Mask + Row Hammer pTRR LFSR1 Mask, 1/2^(value) +**/ + UINT8 Lfsr1Mask; + +/** Offset 0x0CD6 - Reserved +**/ + UINT8 Reserved72; + +/** Offset 0x0CD7 - Command Pins Mapping + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. +**/ + UINT8 Lp5CccConfig; + +/** Offset 0x0CD8 - Command Pins Mirrored + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror. +**/ + UINT8 CmdMirror; + +/** Offset 0x0CD9 - Reserved +**/ + UINT8 Reserved73[3]; + +/** Offset 0x0CDC - LowerBasicMemTestSize + Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 LowerBasicMemTestSize; + +/** Offset 0x0CDD - Reserved +**/ + UINT8 Reserved74[20]; + +/** Offset 0x0CF1 - Skip external display device scanning + Enable: Do not scan for external display device, Disable (Default): Scan external + display devices + $EN_DIS +**/ + UINT8 SkipExtGfxScan; + +/** Offset 0x0CF2 - Generate BIOS Data ACPI Table + Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it + $EN_DIS +**/ + UINT8 BdatEnable; + +/** Offset 0x0CF3 - Lock PCU Thermal Management registers + Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 + $EN_DIS +**/ + UINT8 LockPTMregs; + +/** Offset 0x0CF4 - Panel Power Enable + Control for enabling/disabling VDD force bit (Required only for early enabling of + eDP panel). 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 PanelPowerEnable; + +/** Offset 0x0CF5 - BdatTestType + Indicates the type of Memory Training data to populate into the BDAT ACPI table. + 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D +**/ + UINT8 BdatTestType; + +/** Offset 0x0CF6 - Reserved +**/ + UINT8 Reserved75[2]; + +/** Offset 0x0CF8 - PMR Size + Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot +**/ + UINT32 DmaBufferSize; + +/** Offset 0x0CFC - The policy for VTd driver behavior + BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS +**/ + UINT8 PreBootDmaMask; + +/** Offset 0x0CFD - Reserved +**/ + UINT8 Reserved76[5]; + +/** Offset 0x0D02 - Platform LID Status for LFP Displays. + LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. + 0: LidClosed, 1: LidOpen +**/ + UINT8 LidStatus; + +/** Offset 0x0D03 - Control VGA Initialition sequence + Initialise VGA Init, Set BIT0 - 0 (No VGA Support), BIT0 = 1 (VGA Supported) BIT1 + = 1 (VGA Exit) + 0x0: NO VGA Init, 0x1: VGA Init, 0x3: VGA Init and VGA Exit +**/ + UINT8 VgaInitControl; + +/** Offset 0x0D04 - Graphics Configuration Ptr + Points to VBT +**/ + UINT32 VbtPtr; + +/** Offset 0x0D08 - Intel Graphics VBT (Video BIOS Table) Size + Size of Graphics VBT Image +**/ + UINT32 VbtSize; + +/** Offset 0x0D0C - VGA Training Message Pointer + Points to VGA Message Array +**/ + UINT32 VgaMessage; + +/** Offset 0x0D10 - Reserved +**/ + UINT8 Reserved77[124]; + +/** Offset 0x0D8C - TotalFlashSize + Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable +**/ + UINT16 TotalFlashSize; + +/** Offset 0x0D8E - BiosSize + The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != + 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected + Range) so that a BIOS Update Script can be stored in the DPR. +**/ + UINT16 BiosSize; + +/** Offset 0x0D90 - Reserved +**/ + UINT8 Reserved78[28]; + +/** Offset 0x0DAC - Smbus dynamic power gating + Disable or Enable Smbus dynamic power gating. + $EN_DIS +**/ + UINT8 SmbusDynamicPowerGating; + +/** Offset 0x0DAD - Disable and Lock Watch Dog Register + Set 1 to clear WDT status, then disable and lock WDT registers. + $EN_DIS +**/ + UINT8 WdtDisableAndLock; + +/** Offset 0x0DAE - Reserved +**/ + UINT8 Reserved79[2]; + +/** Offset 0x0DB0 - SMBUS SPD Write Disable + Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write + Disable bit. For security recommendations, SPD write disable bit must be set. + $EN_DIS +**/ + UINT8 SmbusSpdWriteDisable; + +/** Offset 0x0DB1 - Reserved +**/ + UINT8 Reserved80[34]; + +/** Offset 0x0DD3 - HECI Timeouts + 0: Disable, 1: Enable (Default) timeout check for HECI + $EN_DIS +**/ + UINT8 HeciTimeouts; + +/** Offset 0x0DD4 - Force ME DID Init Status + Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set + ME DID init stat value + $EN_DIS +**/ + UINT8 DidInitStat; + +/** Offset 0x0DD5 - CPU Replaced Polling Disable + Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop + $EN_DIS +**/ + UINT8 DisableCpuReplacedPolling; + +/** Offset 0x0DD6 - Check HECI message before send + Test, 0: disable, 1: enable, Enable/Disable message check. + $EN_DIS +**/ + UINT8 DisableMessageCheck; + +/** Offset 0x0DD7 - Skip MBP HOB + Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob. + $EN_DIS +**/ + UINT8 SkipMbpHob; + +/** Offset 0x0DD8 - HECI2 Interface Communication + Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. + $EN_DIS +**/ + UINT8 HeciCommunication2; + +/** Offset 0x0DD9 - Enable KT device + Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device. + $EN_DIS +**/ + UINT8 KtDeviceEnable; + +/** Offset 0x0DDA - Skip CPU replacement check + Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check + $EN_DIS +**/ + UINT8 SkipCpuReplacementCheck; + +/** Offset 0x0DDB - Reserved +**/ + UINT8 Reserved81[100]; + +/** Offset 0x0E3F - Avx2 Voltage Guardband Scaling Factor + AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in + 1/100 units, where a value of 125 would apply a 1.25 scale factor. +**/ + UINT8 Avx2VoltageScaleFactor; + +/** Offset 0x0E40 - Avx512 Voltage Guardband Scaling Factor + DEPRECATED. AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range + is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. +**/ + UINT8 Avx512VoltageScaleFactor; + +/** Offset 0x0E41 - Serial Io Uart Debug Mode + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartDebugMode; + +/** Offset 0x0E42 - Reserved +**/ + UINT8 Reserved82[2]; + +/** Offset 0x0E44 - SerialIoUartDebugRxPinMux - FSPM + Select RX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugRxPinMux; + +/** Offset 0x0E48 - SerialIoUartDebugTxPinMux - FSPM + Select TX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugTxPinMux; + +/** Offset 0x0E4C - SerialIoUartDebugRtsPinMux - FSPM + Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartDebugRtsPinMux; + +/** Offset 0x0E50 - SerialIoUartDebugCtsPinMux - FSPM + Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartDebugCtsPinMux; + +/** Offset 0x0E54 - Reserved +**/ + UINT8 Reserved83[164]; + +/** Offset 0x0EF8 - TME Exclude Base Address + TME Exclude Base Address. +**/ + UINT64 TmeExcludeBase; + +/** Offset 0x0F00 - TME Exclude Size Value + TME Exclude Size Value. +**/ + UINT64 TmeExcludeSize; + +/** Offset 0x0F08 - Generate New TME Key + Enable: Generate New TME Key, Disable(Default): TME key determine by type of reset + $EN_DIS +**/ + UINT8 GenerateNewTmeKey; + +/** Offset 0x0F09 - Reserved +**/ + UINT8 Reserved84[23]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH2_UPD FspmArchUpd; + +/** Offset 0x0060 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0F20 +**/ + UINT8 Rsvd500[6]; + +/** Offset 0x0F26 +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspsUpd.h new file mode 100644 index 0000000..45c411f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/FspsUpd.h @@ -0,0 +1,3174 @@ +/** @file + +Copyright (c) 2024, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + + +/** Fsp S Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Logo Pointer + Points to PEI Display Logo Image +**/ + UINT64 LogoPtr; + +/** Offset 0x0048 - Logo Size + Size of PEI Display Logo Image +**/ + UINT32 LogoSize; + +/** Offset 0x004C - Reserved +**/ + UINT8 Reserved0[4]; + +/** Offset 0x0050 - Blt Buffer Address + Address of Blt buffer +**/ + UINT64 BltBufferAddress; + +/** Offset 0x0058 - Blt Buffer Size + Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of + EFI_GRAPHICS_OUTPUT_BLT_PIXEL) +**/ + UINT64 BltBufferSize; + +/** Offset 0x0060 - Graphics Configuration Ptr + Points to VBT +**/ + UINT64 GraphicsConfigPtr; + +/** Offset 0x0068 - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x0069 - Show SPI controller + Enable/disable to show SPI controller. + $EN_DIS +**/ + UINT8 ShowSpiController; + +/** Offset 0x006A - Reserved +**/ + UINT8 Reserved1[6]; + +/** Offset 0x0070 - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + UINT64 MicrocodeRegionBase; + +/** Offset 0x0078 - MicrocodeRegionSize + Size of Microcode Updates +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x007C - Turbo Mode + Enable/Disable processor Turbo Mode. 0:disable, 1: Enable + $EN_DIS +**/ + UINT8 TurboMode; + +/** Offset 0x007D - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x007E - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, + and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x0086 - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each + port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x008E - Reserved +**/ + UINT8 Reserved2[34]; + +/** Offset 0x00B0 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x00C0 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x00CA - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x00CB - Reserved +**/ + UINT8 Reserved3; + +/** Offset 0x00CC - Address of PCH_DEVICE_INTERRUPT_CONFIG table. + The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. +**/ + UINT32 DevIntConfigPtr; + +/** Offset 0x00D0 - Number of DevIntConfig Entry + Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr + must not be NULL. +**/ + UINT8 NumOfDevIntConfig; + +/** Offset 0x00D1 - PIRQx to IRQx Map Config + PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for + PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy + 8259 PCI mode. +**/ + UINT8 PxRcConfig[8]; + +/** Offset 0x00D9 - Select GPIO IRQ Route + GPIO IRQ Select. The valid value is 14 or 15. +**/ + UINT8 GpioIrqRoute; + +/** Offset 0x00DA - Select SciIrqSelect + SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. +**/ + UINT8 SciIrqSelect; + +/** Offset 0x00DB - Select TcoIrqSelect + TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. +**/ + UINT8 TcoIrqSelect; + +/** Offset 0x00DC - Enable/Disable Tco IRQ + Enable/disable TCO IRQ + $EN_DIS +**/ + UINT8 TcoIrqEnable; + +/** Offset 0x00DD - PCH HDA Verb Table Entry Number + Number of Entries in Verb Table. +**/ + UINT8 PchHdaVerbTableEntryNum; + +/** Offset 0x00DE - Reserved +**/ + UINT8 Reserved4[2]; + +/** Offset 0x00E0 - PCH HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. +**/ + UINT64 PchHdaVerbTablePtr; + +/** Offset 0x00E8 - PCH HDA Codec Sx Wake Capability + Capability to detect wake initiated by a codec in Sx +**/ + UINT8 PchHdaCodecSxWakeCapability; + +/** Offset 0x00E9 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 SataEnable; + +/** Offset 0x00EA - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x00EB - SPIn Device Mode + Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available + modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden +**/ + UINT8 SerialIoSpiMode[7]; + +/** Offset 0x00F2 - SPI<N> Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, + 1:SerialIoSpiCsActiveHigh +**/ + UINT8 SerialIoSpiCsPolarity[14]; + +/** Offset 0x0100 - SPI<N> Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled +**/ + UINT8 SerialIoSpiCsEnable[14]; + +/** Offset 0x010E - SPIn Default Chip Select Output + Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available + options: 0:CS0, 1:CS1 +**/ + UINT8 SerialIoSpiDefaultCsOutput[7]; + +/** Offset 0x0115 - SPIn Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, + SPI1, ... Available options: 0:HW, 1:SW +**/ + UINT8 SerialIoSpiCsMode[7]; + +/** Offset 0x011C - SPIn Default Chip Select State Low/High + Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... + Available options: 0:Low, 1:High +**/ + UINT8 SerialIoSpiCsState[7]; + +/** Offset 0x0123 - Reserved +**/ + UINT8 Reserved5[141]; + +/** Offset 0x01B0 - UARTn Device Mode + Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available + modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartMode[7]; + +/** Offset 0x01B7 - Reserved +**/ + UINT8 Reserved6; + +/** Offset 0x01B8 - Default BaudRate for each Serial IO UART + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 SerialIoUartBaudRate[7]; + +/** Offset 0x01D4 - Default ParityType for each Serial IO UART + Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartParity[7]; + +/** Offset 0x01DB - Default DataBits for each Serial IO UART + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 SerialIoUartDataBits[7]; + +/** Offset 0x01E2 - Default StopBits for each Serial IO UART + Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: + TwoStopBits +**/ + UINT8 SerialIoUartStopBits[7]; + +/** Offset 0x01E9 - Power Gating mode for each Serial IO UART that works in COM mode + Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto +**/ + UINT8 SerialIoUartPowerGating[7]; + +/** Offset 0x01F0 - Enable Dma for each Serial IO UART that supports it + Set DMA/PIO mode. 0: Disabled, 1: Enabled +**/ + UINT8 SerialIoUartDmaEnable[7]; + +/** Offset 0x01F7 - Enables UART hardware flow control, CTS and RTS lines + Enables UART hardware flow control, CTS and RTS lines. +**/ + UINT8 SerialIoUartAutoFlow[7]; + +/** Offset 0x01FE - Reserved +**/ + UINT8 Reserved7[2]; + +/** Offset 0x0200 - SerialIoUartRtsPinMuxPolicy + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartRtsPinMuxPolicy[7]; + +/** Offset 0x021C - SerialIoUartCtsPinMuxPolicy + Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartCtsPinMuxPolicy[7]; + +/** Offset 0x0238 - SerialIoUartRxPinMuxPolicy + Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for + possible values. +**/ + UINT32 SerialIoUartRxPinMuxPolicy[7]; + +/** Offset 0x0254 - SerialIoUartTxPinMuxPolicy + Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for + possible values. +**/ + UINT32 SerialIoUartTxPinMuxPolicy[7]; + +/** Offset 0x0270 - Serial IO UART DBG2 table + Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; + 1: Enable. +**/ + UINT8 SerialIoUartDbg2[7]; + +/** Offset 0x0277 - I2Cn Device Mode + Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available + modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden +**/ + UINT8 SerialIoI2cMode[8]; + +/** Offset 0x027F - Reserved +**/ + UINT8 Reserved8; + +/** Offset 0x0280 - Serial IO I2C SDA Pin Muxing + Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for + possible values. +**/ + UINT32 PchSerialIoI2cSdaPinMux[8]; + +/** Offset 0x02A0 - Serial IO I2C SCL Pin Muxing + Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for + possible values. +**/ + UINT32 PchSerialIoI2cSclPinMux[8]; + +/** Offset 0x02C0 - PCH SerialIo I2C Pads Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination + respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. +**/ + UINT8 PchSerialIoI2cPadsTermination[8]; + +/** Offset 0x02C8 - I3C Device Mode + Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci, + 2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling) +**/ + UINT8 SerialIoI3cMode[2]; + +/** Offset 0x02CA - Reserved +**/ + UINT8 Reserved9[38]; + +/** Offset 0x02F0 - ISH GP GPIO Pin Muxing + Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER +**/ + UINT32 IshGpGpioPinMuxing[12]; + +/** Offset 0x0320 - ISH UART Rx Pin Muxing + Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_* +**/ + UINT32 IshUartRxPinMuxing[3]; + +/** Offset 0x032C - ISH UART Tx Pin Muxing + Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_* +**/ + UINT32 IshUartTxPinMuxing[3]; + +/** Offset 0x0338 - ISH UART Rts Pin Muxing + Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values. +**/ + UINT32 IshUartRtsPinMuxing[3]; + +/** Offset 0x0344 - ISH UART Rts Pin Muxing + Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values. +**/ + UINT32 IshUartCtsPinMuxing[3]; + +/** Offset 0x0350 - ISH I2C SDA Pin Muxing + Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values. +**/ + UINT32 IshI2cSdaPinMuxing[3]; + +/** Offset 0x035C - ISH I2C SCL Pin Muxing + Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values. +**/ + UINT32 IshI2cSclPinMuxing[3]; + +/** Offset 0x0368 - Reserved +**/ + UINT8 Reserved10[8]; + +/** Offset 0x0370 - ISH SPI MOSI Pin Muxing + Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values. +**/ + UINT32 IshSpiMosiPinMuxing[2]; + +/** Offset 0x0378 - ISH SPI MISO Pin Muxing + Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values. +**/ + UINT32 IshSpiMisoPinMuxing[2]; + +/** Offset 0x0380 - ISH SPI CLK Pin Muxing + Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values. +**/ + UINT32 IshSpiClkPinMuxing[2]; + +/** Offset 0x0388 - ISH SPI CS#N Pin Muxing + Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS<N>_* for possible + values. N-SPI number, 0-1. +**/ + UINT32 IshSpiCsPinMuxing[4]; + +/** Offset 0x0398 - ISH GP GPIO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination + respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index + 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31 +**/ + UINT8 IshGpGpioPadTermination[12]; + +/** Offset 0x03A4 - ISH UART Rx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1 + Rx, and so on. +**/ + UINT8 IshUartRxPadTermination[3]; + +/** Offset 0x03A7 - ISH UART Tx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1 + Tx, and so on. +**/ + UINT8 IshUartTxPadTermination[3]; + +/** Offset 0x03AA - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1 + Rts, and so on. +**/ + UINT8 IshUartRtsPadTermination[3]; + +/** Offset 0x03AD - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1 + Cts, and so on. +**/ + UINT8 IshUartCtsPadTermination[3]; + +/** Offset 0x03B0 - ISH I2C SDA Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, + and so on. +**/ + UINT8 IshI2cSdaPadTermination[3]; + +/** Offset 0x03B3 - Reserved +**/ + UINT8 Reserved11; + +/** Offset 0x03B4 - ISH I2C SCL Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, + and so on. +**/ + UINT8 IshI2cSclPadTermination[3]; + +/** Offset 0x03B7 - Reserved +**/ + UINT8 Reserved12; + +/** Offset 0x03B8 - ISH SPI MOSI Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1 + Mosi, and so on. +**/ + UINT8 IshSpiMosiPadTermination[2]; + +/** Offset 0x03BA - ISH SPI MISO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1 + Miso, and so on. +**/ + UINT8 IshSpiMisoPadTermination[2]; + +/** Offset 0x03BC - ISH SPI CLK Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk, + and so on. +**/ + UINT8 IshSpiClkPadTermination[2]; + +/** Offset 0x03BE - ISH SPI CS#N Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination + respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1 + Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3 +**/ + UINT8 IshSpiCsPadTermination[4]; + +/** Offset 0x03C2 - Enable PCH ISH SPI Cs#N pins assigned + Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs + number: 0-1 +**/ + UINT8 PchIshSpiCsEnable[4]; + +/** Offset 0x03C6 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2PhyPetxiset[16]; + +/** Offset 0x03D6 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2PhyTxiset[16]; + +/** Offset 0x03E6 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2PhyPredeemp[16]; + +/** Offset 0x03F6 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT8 Usb2PhyPehalfbit[16]; + +/** Offset 0x0406 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x0410 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], + Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x041A - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x0424 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default + = 00h. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x042E +**/ + UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10]; + +/** Offset 0x0438 +**/ + UINT8 PchUsb3HsioFilterSelNEnable[10]; + +/** Offset 0x0442 +**/ + UINT8 PchUsb3HsioFilterSelPEnable[10]; + +/** Offset 0x044C +**/ + UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10]; + +/** Offset 0x0456 +**/ + UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10]; + +/** Offset 0x0460 +**/ + UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10]; + +/** Offset 0x046A +**/ + UINT8 PchUsb3HsioFilterSelN[10]; + +/** Offset 0x0474 +**/ + UINT8 PchUsb3HsioFilterSelP[10]; + +/** Offset 0x047E - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 PchLanEnable; + +/** Offset 0x047F - Enable PCH TSN + Enable/disable TSN on the PCH. + $EN_DIS +**/ + UINT8 PchTsnEnable; + +/** Offset 0x0480 - TSN Link Speed + Set TSN Link Speed. + 0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps +**/ + UINT8 PchTsnLinkSpeed; + +/** Offset 0x0481 - Reserved +**/ + UINT8 Reserved13[19]; + +/** Offset 0x0494 - PCIe PTM enable/disable + Enable/disable Precision Time Measurement for PCIE Root Ports. +**/ + UINT8 PciePtm[29]; + +/** Offset 0x04B1 - Reserved +**/ + UINT8 Reserved14[29]; + +/** Offset 0x04CE - USB PDO Programming + Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming + during later phase. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 UsbPdoProgramming; + +/** Offset 0x04CF - Reserved +**/ + UINT8 Reserved15[5]; + +/** Offset 0x04D4 - Power button debounce configuration + Debounce time for PWRBTN in microseconds. For values not supported by HW, they will + be rounded down to closest supported on. 0: disable, 250-1024000us: supported range +**/ + UINT32 PmcPowerButtonDebounce; + +/** Offset 0x04D8 - Reserved +**/ + UINT8 Reserved16; + +/** Offset 0x04D9 - PCH eSPI Link Configuration Lock (SBLCL) + Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target + addresseses from range 0x0 - 0x7FF + $EN_DIS +**/ + UINT8 PchEspiLockLinkConfiguration; + +/** Offset 0x04DA - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states + Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtV1p05RailEnabledStates; + +/** Offset 0x04DB - Mask to enable the platform configuration of external V1p05 VR rail + External V1P05 Rail Supported Configuration +**/ + UINT8 PchFivrExtV1p05RailSupportedVoltageStates; + +/** Offset 0x04DC - External V1P05 Voltage Value that will be used in S0i2/S0i3 states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtV1p05RailVoltage; + +/** Offset 0x04DE - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtV1p05RailIccMax; + +/** Offset 0x04DF - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states + Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtVnnRailEnabledStates; + +/** Offset 0x04E0 - Mask to enable the platform configuration of external Vnn VR rail + External Vnn Rail Supported Configuration +**/ + UINT8 PchFivrExtVnnRailSupportedVoltageStates; + +/** Offset 0x04E1 - Reserved +**/ + UINT8 Reserved17; + +/** Offset 0x04E2 - External Vnn Voltage Value that will be used in S0ix/Sx states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 +**/ + UINT16 PchFivrExtVnnRailVoltage; + +/** Offset 0x04E4 - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailIccMax; + +/** Offset 0x04E5 - Mask to enable the usage of external Vnn VR rail in Sx states + Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in + Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtVnnRailSxEnabledStates; + +/** Offset 0x04E6 - External Vnn Voltage Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments + (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtVnnRailSxVoltage; + +/** Offset 0x04E8 - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailSxIccMax; + +/** Offset 0x04E9 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to low current mode voltage. +**/ + UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; + +/** Offset 0x04EA - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; + +/** Offset 0x04EB - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; + +/** Offset 0x04EC - Transition time in microseconds from Off (0V) to High Current Mode Voltage + This field has 1us resolution. When value is 0 Transition to 0V is disabled. +**/ + UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; + +/** Offset 0x04EE - PMC Debug Message Enable + When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW + will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix + $EN_DIS +**/ + UINT8 PmcDbgMsgEn; + +/** Offset 0x04EF - Reserved +**/ + UINT8 Reserved18; + +/** Offset 0x04F0 - Pointer to ChipsetInit Binary + ChipsetInit Binary Pointer. +**/ + UINT32 ChipsetInitBinPtr; + +/** Offset 0x04F4 - Length of ChipsetInit Binary + ChipsetInit Binary Length. +**/ + UINT32 ChipsetInitBinLen; + +/** Offset 0x04F8 - Reserved +**/ + UINT8 Reserved19[16]; + +/** Offset 0x0508 - FIVR Dynamic Power Management + Enable/Disable FIVR Dynamic Power Management. + $EN_DIS +**/ + UINT8 PchFivrDynPm; + +/** Offset 0x0509 - Reserved +**/ + UINT8 Reserved20; + +/** Offset 0x050A - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtV1p05RailIccMaximum; + +/** Offset 0x050C - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtVnnRailIccMaximum; + +/** Offset 0x050E - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtVnnRailSxIccMaximum; + +/** Offset 0x0510 - Reserved +**/ + UINT8 Reserved21[14]; + +/** Offset 0x051E - CNVi Configuration + This option allows for automatic detection of Connectivity Solution. [Auto Detection] + assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. + 0:Disable, 1:Auto +**/ + UINT8 CnviMode; + +/** Offset 0x051F - CNVi Wi-Fi Core + Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviWifiCore; + +/** Offset 0x0520 - CNVi BT Core + Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtCore; + +/** Offset 0x0521 - CNVi BT Audio Offload + Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtAudioOffload; + +/** Offset 0x0522 - Reserved +**/ + UINT8 Reserved22[2]; + +/** Offset 0x0524 - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default) + or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. +**/ + UINT32 CnviRfResetPinMux; + +/** Offset 0x0528 - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default) + or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in + GpioPins*.h. +**/ + UINT32 CnviClkreqPinMux; + +/** Offset 0x052C - Enable Host C10 reporting through eSPI + Enable/disable Host C10 reporting to Device via eSPI Virtual Wire. + $EN_DIS +**/ + UINT8 PchEspiHostC10ReportEnable; + +/** Offset 0x052D - PCH USB2 PHY Power Gating enable + 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY + Sus Well PG + $EN_DIS +**/ + UINT8 PmcUsb2PhySusPgEnable; + +/** Offset 0x052E - PCH USB OverCurrent mapping enable + 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin + mapping allow for NOA usage of OC pins + $EN_DIS +**/ + UINT8 PchUsbOverCurrentEnable; + +/** Offset 0x052F - Espi Lgmr Memory Range decode + This option enables or disables espi lgmr + $EN_DIS +**/ + UINT8 PchEspiLgmrEnable; + +/** Offset 0x0530 - External V1P05 Control Ramp Timer value + Hold off time to be used when changing the v1p05_ctrl for external bypass value in us +**/ + UINT8 PchFivrExtV1p05RailCtrlRampTmr; + +/** Offset 0x0531 - External VNN Control Ramp Timer value + Hold off time to be used when changing the vnn_ctrl for external bypass value in us +**/ + UINT8 PchFivrExtVnnRailCtrlRampTmr; + +/** Offset 0x0532 - Set SATA DEVSLP GPIO Reset Config + Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, + 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte + for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlpResetConfig[8]; + +/** Offset 0x053A - PCHHOT# pin + Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchHotEnable; + +/** Offset 0x053B - SATA LED + SATA LED indicating SATA controller activity. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 SataLedEnable; + +/** Offset 0x053C - VRAlert# Pin + When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling + to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchPmVrAlert; + +/** Offset 0x053D - AMT Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. + $EN_DIS +**/ + UINT8 AmtEnabled; + +/** Offset 0x053E - WatchDog Timer Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting + is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 WatchDogEnabled; + +/** Offset 0x053F - PET Progress + Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive + PET Events. Setting is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 FwProgress; + +/** Offset 0x0540 - SOL Switch + Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. + Setting is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 AmtSolEnabled; + +/** Offset 0x0541 - Reserved +**/ + UINT8 Reserved23; + +/** Offset 0x0542 - OS Timer + 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. +**/ + UINT16 WatchDogTimerOs; + +/** Offset 0x0544 - BIOS Timer + 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. +**/ + UINT16 WatchDogTimerBios; + +/** Offset 0x0546 - PCH PCIe root port connection type + 0: built-in device, 1:slot +**/ + UINT8 PcieRpSlotImplemented[29]; + +/** Offset 0x0563 - PCIE RP Access Control Services Extended Capability + Enable/Disable PCIE RP Access Control Services Extended Capability +**/ + UINT8 PcieRpAcsEnabled[29]; + +/** Offset 0x0580 - PCIE RP Clock Power Management + Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal + can still be controlled by L1 PM substates mechanism +**/ + UINT8 PcieRpEnableCpm[29]; + +/** Offset 0x059D - Reserved +**/ + UINT8 Reserved24[3]; + +/** Offset 0x05A0 - PCIE RP Detect Timeout Ms + The number of milliseconds within 0~65535 in reference code will wait for link to + exit Detect state for enabled ports before assuming there is no device and potentially + disabling the port. +**/ + UINT16 PcieRpDetectTimeoutMs[29]; + +/** Offset 0x05DA - ModPHY SUS Power Domain Dynamic Gating + Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on + PCH-H. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcModPhySusPgEnable; + +/** Offset 0x05DB - V1p05-PHY supply external FET control + Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY + supply. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcV1p05PhyExtFetControlEn; + +/** Offset 0x05DC - V1p05-IS supply external FET control + Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS + supply. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcV1p05IsExtFetControlEn; + +/** Offset 0x05DD - Enable/Disable PavpEnable + Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable + $EN_DIS +**/ + UINT8 PavpEnable; + +/** Offset 0x05DE - Enable/Disable PeiGraphicsPeimInit + Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. + Disable: FSP will NOT initialize the framebuffer. + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x05DF - Enable D3 Hot in TCSS + This policy will enable/disable D3 hot support in IOM + $EN_DIS +**/ + UINT8 D3HotEnable; + +/** Offset 0x05E0 - Enable or disable GNA device + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 GnaEnable; + +/** Offset 0x05E1 - Reserved +**/ + UINT8 Reserved25[3]; + +/** Offset 0x05E4 - TypeC port GPIO setting + GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined + in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Mtl + = MeteorLake) +**/ + UINT32 IomTypeCPortPadCfg[12]; + +/** Offset 0x0614 - CPU USB3 Port Over Current Pin + Describe the specific over current pin number of USBC Port N. +**/ + UINT8 CpuUsb3OverCurrentPin[8]; + +/** Offset 0x061C - Enable D3 Cold in TCSS + This policy will enable/disable D3 cold support in IOM + $EN_DIS +**/ + UINT8 D3ColdEnable; + +/** Offset 0x061D - Enable/Disable PCIe tunneling for USB4 + Enable/Disable PCIe tunneling for USB4, default is enable + $EN_DIS +**/ + UINT8 ITbtPcieTunnelingForUsb4; + +/** Offset 0x061E - Enable/Disable SkipFspGop + Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver + $EN_DIS +**/ + UINT8 SkipFspGop; + +/** Offset 0x061F - Enable/Disable VPU Device + Enable(Default): Enable VPU Device, Disable: Disable VPU Device + $EN_DIS +**/ + UINT8 VpuEnable; + +/** Offset 0x0620 - TC State in TCSS + This TC C-State Limit in IOM +**/ + UINT8 TcCstateLimit; + +/** Offset 0x0621 - Reserved +**/ + UINT8 Reserved26[3]; + +/** Offset 0x0624 - Intel Graphics VBT (Video BIOS Table) Size + Size of Internal Graphics VBT Image +**/ + UINT32 VbtSize; + +/** Offset 0x0628 - Platform LID Status for LFP Displays. + LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. + 0: LidClosed, 1: LidOpen +**/ + UINT8 LidStatus; + +/** Offset 0x0629 - Reserved +**/ + UINT8 Reserved27[8]; + +/** Offset 0x0631 - Enable VMD controller + Enable/disable to VMD controller.0: Disable; 1: Enable(Default) + $EN_DIS +**/ + UINT8 VmdEnable; + +/** Offset 0x0632 - Enable VMD Global Mapping + Enable/disable to VMD controller.0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 VmdGlobalMapping; + +/** Offset 0x0633 - Map port under VMD + Map/UnMap port under VMD + $EN_DIS +**/ + UINT8 VmdPort[31]; + +/** Offset 0x0652 - Reserved +**/ + UINT8 Reserved28[31]; + +/** Offset 0x0671 - VMD Port Device + VMD Root port device number. +**/ + UINT8 VmdPortDev[31]; + +/** Offset 0x0690 - VMD Port Func + VMD Root port function number. +**/ + UINT8 VmdPortFunc[31]; + +/** Offset 0x06AF - Reserved +**/ + UINT8 Reserved29; + +/** Offset 0x06B0 - VMD Variable + VMD Variable Pointer. +**/ + UINT64 VmdVariablePtr; + +/** Offset 0x06B8 - Temporary CfgBar address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdCfgBarBase; + +/** Offset 0x06BC - Temporary MemBar1 address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdMemBar1Base; + +/** Offset 0x06C0 - Temporary MemBar2 address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdMemBar2Base; + +/** Offset 0x06C4 - Reserved +**/ + UINT8 Reserved30; + +/** Offset 0x06C5 - Enable/Disable PMC-PD Solution + This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution + $EN_DIS +**/ + UINT8 PmcPdEnable; + +/** Offset 0x06C6 - TCSS Aux Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssAuxOri; + +/** Offset 0x06C8 - TCSS HSL Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssHslOri; + +/** Offset 0x06CA - USB override in IOM + This policy will enable/disable USB Connect override in IOM + $EN_DIS +**/ + UINT8 UsbOverride; + +/** Offset 0x06CB - ITBT Root Port Enable + ITBT Root Port Enable, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 ITbtPcieRootPortEn[4]; + +/** Offset 0x06CF - TCSS USB Port Enable + Bits 0, 1, ... max Type C port control enables +**/ + UINT8 UsbTcPortEn; + +/** Offset 0x06D0 - ITBTForcePowerOn Timeout value + ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. + 100 = 100 ms. +**/ + UINT16 ITbtForcePowerOnTimeoutInMs; + +/** Offset 0x06D2 - ITbtConnectTopology Timeout value + ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range + is 0-10000. 100 = 100 ms. +**/ + UINT16 ITbtConnectTopologyTimeoutInMs; + +/** Offset 0x06D4 - VCCST request for IOM + This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5 + $EN_DIS +**/ + UINT8 VccSt; + +/** Offset 0x06D5 - Reserved +**/ + UINT8 Reserved31; + +/** Offset 0x06D6 - ITBT DMA LTR + TCSS DMA1, DMA2 LTR value +**/ + UINT16 ITbtDmaLtr[2]; + +/** Offset 0x06DA - Reserved +**/ + UINT8 Reserved32; + +/** Offset 0x06DB - Enable/Disable PTM + This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports + $EN_DIS +**/ + UINT8 PtmEnabled[4]; + +/** Offset 0x06DF - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 SaPcieItbtRpLtrEnable[4]; + +/** Offset 0x06E3 - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4]; + +/** Offset 0x06E7 - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x06EB - Reserved +**/ + UINT8 Reserved33; + +/** Offset 0x06EC - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4]; + +/** Offset 0x06F4 - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4]; + +/** Offset 0x06F8 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x06FC - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4]; + +/** Offset 0x0704 - Force LTR Override + Force LTR Override. +**/ + UINT8 SaPcieItbtRpForceLtrOverride[4]; + +/** Offset 0x0708 - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 SaPcieItbtRpLtrConfigLock[4]; + +/** Offset 0x070C - Enable or Disable TXT + Enables utilization of additional hardware capabilities provided by Intel (R) Trusted + Execution Technology. Changes require a full power cycle to take effect. 0: + Disable, 1: Enable. + $EN_DIS +**/ + UINT8 TxtEnable; + +/** Offset 0x070D - Reserved +**/ + UINT8 Reserved34[3]; + +/** Offset 0x0710 - CpuBistData + Pointer CPU BIST Data +**/ + UINT64 CpuBistData; + +/** Offset 0x0718 - CpuMpPpi + Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. + If not NULL, FSP will use the boot loader's implementation of multiprocessing. + See section 5.1.4 of the FSP Integration Guide for more details. +**/ + UINT64 CpuMpPpi; + +/** Offset 0x0720 - Reserved +**/ + UINT8 Reserved35[4]; + +/** Offset 0x0724 - PpinSupport to view Protected Processor Inventory Number + PPIN Feature Support to view Protected Processor Inventory Number. Disable to turn + off this feature. When 'PPIN Enable Mode' is selected, this shows second option + where feature can be enabled based on EOM (End of Manufacturing) flag or it is + always enabled + 0: Disable, 1: Enable, 2: Auto +**/ + UINT8 PpinSupport; + +/** Offset 0x0725 - Reserved +**/ + UINT8 Reserved36; + +/** Offset 0x0726 - Smbios Type4 Max Speed Override + Provide the option for platform to override the MaxSpeed field of Smbios Type 4. + If this value is not zero, it dominates the field. +**/ + UINT16 SmbiosType4MaxSpeedOverride; + +/** Offset 0x0728 - Advanced Encryption Standard (AES) feature + Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 AesEnable; + +/** Offset 0x0729 - AvxDisable + Enable/Disable the AVX and AVX2 Instructions + 0: Enable, 1: Disable +**/ + UINT8 AvxDisable; + +/** Offset 0x072A - Reserved +**/ + UINT8 Reserved37[58]; + +/** Offset 0x0764 - Enable Power Optimizer + Enable DMI Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 PchPwrOptEnable; + +/** Offset 0x0765 - PCH Flash Protection Ranges Write Enble + Write or erase is blocked by hardware. +**/ + UINT8 PchWriteProtectionEnable[5]; + +/** Offset 0x076A - PCH Flash Protection Ranges Read Enble + Read is blocked by hardware. +**/ + UINT8 PchReadProtectionEnable[5]; + +/** Offset 0x076F - Reserved +**/ + UINT8 Reserved38; + +/** Offset 0x0770 - PCH Protect Range Limit + Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for + limit comparison. +**/ + UINT16 PchProtectedRangeLimit[5]; + +/** Offset 0x077A - PCH Protect Range Base + Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. +**/ + UINT16 PchProtectedRangeBase[5]; + +/** Offset 0x0784 - Enable Pme + Enable Azalia wake-on-ring. + $EN_DIS +**/ + UINT8 PchHdaPme; + +/** Offset 0x0785 - HD Audio Link Frequency + HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. + 0: 6MHz, 1: 12MHz, 2: 24MHz +**/ + UINT8 PchHdaLinkFrequency; + +/** Offset 0x0786 - Enable PCH ISH SPI Cs0 pins assigned + Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiCs0Enable[1]; + +/** Offset 0x0787 - Enable PCH Io Apic Entry 24-119 + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIoApicEntry24_119; + +/** Offset 0x0788 - PCH Io Apic ID + This member determines IOAPIC ID. Default is 0x02. +**/ + UINT8 PchIoApicId; + +/** Offset 0x0789 - Enable PCH ISH SPI pins assigned + Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiEnable[1]; + +/** Offset 0x078A - Enable PCH ISH UART pins assigned + Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshUartEnable[2]; + +/** Offset 0x078C - Enable PCH ISH I2C pins assigned + Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI2cEnable[3]; + +/** Offset 0x078F - Enable PCH ISH I3C pins assigned + Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI3cEnable; + +/** Offset 0x0790 - Enable PCH ISH GP pins assigned + Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshGpEnable[12]; + +/** Offset 0x079C - PCH ISH PDT Unlock Msg + 0: False; 1: True. + $EN_DIS +**/ + UINT8 PchIshPdtUnlock; + +/** Offset 0x079D - Reserved +**/ + UINT8 Reserved39; + +/** Offset 0x079E - Enable PCH Lan LTR capabilty of PCH internal LAN + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchLanLtrEnable; + +/** Offset 0x079F - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + UINT8 PchLockDownBiosLock; + +/** Offset 0x07A0 - PCH Compatibility Revision ID + This member describes whether or not the CRID feature of PCH should be enabled. + $EN_DIS +**/ + UINT8 PchCrid; + +/** Offset 0x07A1 - RTC BIOS Interface Lock + Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed. + $EN_DIS +**/ + UINT8 RtcBiosInterfaceLock; + +/** Offset 0x07A2 - RTC Cmos Memory Lock + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcMemoryLock; + +/** Offset 0x07A3 - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 PcieRpHotPlug[29]; + +/** Offset 0x07C0 - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. + $EN_DIS +**/ + UINT8 PcieRpPmSci[29]; + +/** Offset 0x07DD - Enable PCIE RP Transmitter Half Swing + Indicate whether the Transmitter Half Swing is enabled. +**/ + UINT8 PcieRpTransmitterHalfSwing[29]; + +/** Offset 0x07FA - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + UINT8 PcieRpClkReqDetect[29]; + +/** Offset 0x0817 - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 PcieRpAdvancedErrorReporting[29]; + +/** Offset 0x0834 - PCIE RP Unsupported Request Report + Indicate whether the Unsupported Request Report is enabled. +**/ + UINT8 PcieRpUnsupportedRequestReport[29]; + +/** Offset 0x0851 - PCIE RP Fatal Error Report + Indicate whether the Fatal Error Report is enabled. +**/ + UINT8 PcieRpFatalErrorReport[29]; + +/** Offset 0x086E - PCIE RP No Fatal Error Report + Indicate whether the No Fatal Error Report is enabled. +**/ + UINT8 PcieRpNoFatalErrorReport[29]; + +/** Offset 0x088B - PCIE RP Correctable Error Report + Indicate whether the Correctable Error Report is enabled. +**/ + UINT8 PcieRpCorrectableErrorReport[29]; + +/** Offset 0x08A8 - PCIE RP System Error On Fatal Error + Indicate whether the System Error on Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnFatalError[29]; + +/** Offset 0x08C5 - PCIE RP System Error On Non Fatal Error + Indicate whether the System Error on Non Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnNonFatalError[29]; + +/** Offset 0x08E2 - PCIE RP System Error On Correctable Error + Indicate whether the System Error on Correctable Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnCorrectableError[29]; + +/** Offset 0x08FF - PCIE RP Max Payload + Max Payload Size supported, Default 256B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + UINT8 PcieRpMaxPayload[29]; + +/** Offset 0x091C - Touch Host Controller Assignment + Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1 +**/ + UINT8 ThcAssignment[2]; + +/** Offset 0x091E - Reserved +**/ + UINT8 Reserved40[122]; + +/** Offset 0x0998 - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: + PCIE_SPEED). +**/ + UINT8 PcieRpPcieSpeed[29]; + +/** Offset 0x09B5 - PCIE RP Physical Slot Number + Indicates the slot number for the root port. Default is the value as root port index. +**/ + UINT8 PcieRpPhysicalSlotNumber[29]; + +/** Offset 0x09D2 - PCIE RP Completion Timeout + The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. +**/ + UINT8 PcieRpCompletionTimeout[29]; + +/** Offset 0x09EF - PCIE RP Aspm + The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + PchPcieAspmAutoConfig. +**/ + UINT8 PcieRpAspm[29]; + +/** Offset 0x0A0C - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). + Default is PchPcieL1SubstatesL1_1_2. +**/ + UINT8 PcieRpL1Substates[29]; + +/** Offset 0x0A29 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 PcieRpLtrEnable[29]; + +/** Offset 0x0A46 - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 PcieRpLtrConfigLock[29]; + +/** Offset 0x0A63 - PCIE RP override default settings for EQ + Choose PCIe EQ method + $EN_DIS +**/ + UINT8 PcieEqOverrideDefault[29]; + +/** Offset 0x0A80 - Reserved +**/ + UINT8 Reserved41[3767]; + +/** Offset 0x1937 - PCIE RP Enable Peer Memory Write + This member describes whether Peer Memory Writes are enabled on the platform. + $EN_DIS +**/ + UINT8 PcieEnablePeerMemoryWrite[12]; + +/** Offset 0x1943 - PCIE Compliance Test Mode + Compliance Test Mode shall be enabled when using Compliance Load Board. + $EN_DIS +**/ + UINT8 PcieComplianceTestMode; + +/** Offset 0x1944 - PCIE Rp Function Swap + Allows BIOS to use root port function number swapping when root port of function + 0 is disabled. + $EN_DIS +**/ + UINT8 PcieRpFunctionSwap; + +/** Offset 0x1945 - Reserved +**/ + UINT8 Reserved42; + +/** Offset 0x1946 - PCH Pm PME_B0_S5_DIS + When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. + $EN_DIS +**/ + UINT8 PchPmPmeB0S5Dis; + +/** Offset 0x1947 - PCIE IMR + Enables Isolated Memory Region for PCIe. + $EN_DIS +**/ + UINT8 PcieRpImrEnabled; + +/** Offset 0x1948 - PCIE IMR port number + Selects PCIE root port number for IMR feature. +**/ + UINT8 PcieRpImrSelection; + +/** Offset 0x1949 - PCH Pm Wol Enable Override + Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. + $EN_DIS +**/ + UINT8 PchPmWolEnableOverride; + +/** Offset 0x194A - PCH Pm WoW lan Enable + Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanEnable; + +/** Offset 0x194B - Reserved +**/ + UINT8 Reserved43[4]; + +/** Offset 0x194F - PCH Pm Slp S3 Min Assert + SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. +**/ + UINT8 PchPmSlpS3MinAssert; + +/** Offset 0x1950 - PCH Pm Slp S4 Min Assert + SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. +**/ + UINT8 PchPmSlpS4MinAssert; + +/** Offset 0x1951 - PCH Pm Slp Sus Min Assert + SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. +**/ + UINT8 PchPmSlpSusMinAssert; + +/** Offset 0x1952 - PCH Pm Slp A Min Assert + SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. +**/ + UINT8 PchPmSlpAMinAssert; + +/** Offset 0x1953 - USB Overcurrent Override for VISA + This option overrides USB Over Current enablement state that USB OC will be disabled + after enabling this option. Enable when VISA pin is muxed with USB OC + $EN_DIS +**/ + UINT8 PchEnableDbcObs; + +/** Offset 0x1954 - PCH Pm Slp Strch Sus Up + Enable SLP_X Stretching After SUS Well Power Up. + $EN_DIS +**/ + UINT8 PchPmSlpStrchSusUp; + +/** Offset 0x1955 - PCH Pm Slp Lan Low Dc + Enable/Disable SLP_LAN# Low on DC Power. + $EN_DIS +**/ + UINT8 PchPmSlpLanLowDc; + +/** Offset 0x1956 - PCH Pm Pwr Btn Override Period + PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. +**/ + UINT8 PchPmPwrBtnOverridePeriod; + +/** Offset 0x1957 - PCH Pm Disable Native Power Button + Power button native mode disable. + $EN_DIS +**/ + UINT8 PchPmDisableNativePowerButton; + +/** Offset 0x1958 - PCH Pm ME_WAKE_STS + Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmMeWakeSts; + +/** Offset 0x1959 - PCH Pm WOL_OVR_WK_STS + Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmWolOvrWkSts; + +/** Offset 0x195A - PCH Pm Reset Power Cycle Duration + Could be customized in the unit of second. Please refer to EDS for all support settings. + 0 is default, 1 is 1 second, 2 is 2 seconds, ... +**/ + UINT8 PchPmPwrCycDur; + +/** Offset 0x195B - PCH Pm Pcie Pll Ssc + Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No + BIOS override. +**/ + UINT8 PchPmPciePllSsc; + +/** Offset 0x195C - PCH Legacy IO Low Latency Enable + Set to enable low latency of legacy IO. 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchLegacyIoLowLatency; + +/** Offset 0x195D - PCH Sata Pwr Opt Enable + SATA Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 SataPwrOptEnable; + +/** Offset 0x195E - PCH Sata eSATA Speed Limit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. + $EN_DIS +**/ + UINT8 EsataSpeedLimit; + +/** Offset 0x195F - PCH Sata Speed Limit + Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. +**/ + UINT8 SataSpeedLimit; + +/** Offset 0x1960 - Enable SATA Port HotPlug + Enable SATA Port HotPlug. +**/ + UINT8 SataPortsHotPlug[8]; + +/** Offset 0x1968 - Enable SATA Port Interlock Sw + Enable SATA Port Interlock Sw. +**/ + UINT8 SataPortsInterlockSw[8]; + +/** Offset 0x1970 - Enable SATA Port External + Enable SATA Port External. +**/ + UINT8 SataPortsExternal[8]; + +/** Offset 0x1978 - Enable SATA Port SpinUp + Enable the COMRESET initialization Sequence to the device. +**/ + UINT8 SataPortsSpinUp[8]; + +/** Offset 0x1980 - Enable SATA Port Solid State Drive + 0: HDD; 1: SSD. +**/ + UINT8 SataPortsSolidStateDrive[8]; + +/** Offset 0x1988 - Enable SATA Port Enable Dito Config + Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). +**/ + UINT8 SataPortsEnableDitoConfig[8]; + +/** Offset 0x1990 - Enable SATA Port DmVal + DITO multiplier. Default is 15. +**/ + UINT8 SataPortsDmVal[8]; + +/** Offset 0x1998 - Reserved +**/ + UINT8 Reserved44[2]; + +/** Offset 0x199A - Enable SATA Port DmVal + DEVSLP Idle Timeout (DITO), Default is 625. +**/ + UINT16 SataPortsDitoVal[8]; + +/** Offset 0x19AA - Enable SATA Port ZpOdd + Support zero power ODD. +**/ + UINT8 SataPortsZpOdd[8]; + +/** Offset 0x19B2 - PCH Sata Rst Raid Alternate Id + Enable RAID Alternate ID. + $EN_DIS +**/ + UINT8 SataRstRaidDeviceId; + +/** Offset 0x19B3 - PCH Sata Rst Pcie Storage Remap enable + Enable Intel RST for PCIe Storage remapping. +**/ + UINT8 SataRstPcieEnable[3]; + +/** Offset 0x19B6 - PCH Sata Rst Pcie Storage Port + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). +**/ + UINT8 SataRstPcieStoragePort[3]; + +/** Offset 0x19B9 - PCH Sata Rst Pcie Device Reset Delay + PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms +**/ + UINT8 SataRstPcieDeviceResetDelay[3]; + +/** Offset 0x19BC - UFS enable/disable + Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller + 0 and (0,1) to enable controller 1 + $EN_DIS +**/ + UINT8 UfsEnable[2]; + +/** Offset 0x19BE - Reserved +**/ + UINT8 Reserved45[2]; + +/** Offset 0x19C0 - IEH Mode + Integrated Error Handler Mode, 0: Bypass, 1: Enable + 0: Bypass, 1:Enable +**/ + UINT8 IehMode; + +/** Offset 0x19C1 - Reserved +**/ + UINT8 Reserved46[11]; + +/** Offset 0x19CC - PCH Thermal Throttling Custimized T0Level Value + Custimized T0Level value. +**/ + UINT16 PchT0Level; + +/** Offset 0x19CE - PCH Thermal Throttling Custimized T1Level Value + Custimized T1Level value. +**/ + UINT16 PchT1Level; + +/** Offset 0x19D0 - PCH Thermal Throttling Custimized T2Level Value + Custimized T2Level value. +**/ + UINT16 PchT2Level; + +/** Offset 0x19D2 - Enable PCH Thermal Throttle + Enable thermal throttle function. + $EN_DIS +**/ + UINT8 PchTTEnable; + +/** Offset 0x19D3 - PCH PMSync State 13 + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force + at least T2 state. + $EN_DIS +**/ + UINT8 PchTTState13Enable; + +/** Offset 0x19D4 - PCH Thermal Throttle Lock + Thermal Throttle Lock. + $EN_DIS +**/ + UINT8 PchTTLock; + +/** Offset 0x19D5 - Reserved +**/ + UINT8 Reserved47[9]; + +/** Offset 0x19DE - DMI Thermal Sensor Autonomous Width Enable + DMI Thermal Sensor Autonomous Width Enable. + $EN_DIS +**/ + UINT8 PchDmiTsawEn; + +/** Offset 0x19DF - DMI Thermal Sensor Suggested Setting + DMT thermal sensor suggested representative values. + $EN_DIS +**/ + UINT8 DmiSuggestedSetting; + +/** Offset 0x19E0 - Thermal Sensor 0 Target Width + Thermal Sensor 0 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS0TW; + +/** Offset 0x19E1 - Thermal Sensor 1 Target Width + Thermal Sensor 1 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS1TW; + +/** Offset 0x19E2 - Thermal Sensor 2 Target Width + Thermal Sensor 2 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS2TW; + +/** Offset 0x19E3 - Thermal Sensor 3 Target Width + Thermal Sensor 3 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS3TW; + +/** Offset 0x19E4 - Port 0 T1 Multipler + Port 0 T1 Multipler. +**/ + UINT8 SataP0T1M; + +/** Offset 0x19E5 - Port 0 T2 Multipler + Port 0 T2 Multipler. +**/ + UINT8 SataP0T2M; + +/** Offset 0x19E6 - Port 0 T3 Multipler + Port 0 T3 Multipler. +**/ + UINT8 SataP0T3M; + +/** Offset 0x19E7 - Port 0 Tdispatch + Port 0 Tdispatch. +**/ + UINT8 SataP0TDisp; + +/** Offset 0x19E8 - Port 1 T1 Multipler + Port 1 T1 Multipler. +**/ + UINT8 SataP1T1M; + +/** Offset 0x19E9 - Port 1 T2 Multipler + Port 1 T2 Multipler. +**/ + UINT8 SataP1T2M; + +/** Offset 0x19EA - Port 1 T3 Multipler + Port 1 T3 Multipler. +**/ + UINT8 SataP1T3M; + +/** Offset 0x19EB - Port 1 Tdispatch + Port 1 Tdispatch. +**/ + UINT8 SataP1TDisp; + +/** Offset 0x19EC - Port 0 Tinactive + Port 0 Tinactive. +**/ + UINT8 SataP0Tinact; + +/** Offset 0x19ED - Port 0 Alternate Fast Init Tdispatch + Port 0 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + UINT8 SataP0TDispFinit; + +/** Offset 0x19EE - Port 1 Tinactive + Port 1 Tinactive. +**/ + UINT8 SataP1Tinact; + +/** Offset 0x19EF - Port 1 Alternate Fast Init Tdispatch + Port 1 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + UINT8 SataP1TDispFinit; + +/** Offset 0x19F0 - Sata Thermal Throttling Suggested Setting + Sata Thermal Throttling Suggested Setting. + $EN_DIS +**/ + UINT8 SataThermalSuggestedSetting; + +/** Offset 0x19F1 - Reserved +**/ + UINT8 Reserved48; + +/** Offset 0x19F2 - Thermal Device Temperature + Decides the temperature. +**/ + UINT16 PchTemperatureHotLevel; + +/** Offset 0x19F4 - USB2 Port Over Current Pin + Describe the specific over current pin number of USB 2.0 Port N. +**/ + UINT8 Usb2OverCurrentPin[16]; + +/** Offset 0x1A04 - USB3 Port Over Current Pin + Describe the specific over current pin number of USB 3.0 Port N. +**/ + UINT8 Usb3OverCurrentPin[10]; + +/** Offset 0x1A0E - Enable xHCI LTR override + Enables override of recommended LTR values for xHCI + $EN_DIS +**/ + UINT8 PchUsbLtrOverrideEnable; + +/** Offset 0x1A0F - Reserved +**/ + UINT8 Reserved49; + +/** Offset 0x1A10 - xHCI High Idle Time LTR override + Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting +**/ + UINT32 PchUsbLtrHighIdleTimeOverride; + +/** Offset 0x1A14 - xHCI Medium Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting +**/ + UINT32 PchUsbLtrMediumIdleTimeOverride; + +/** Offset 0x1A18 - xHCI Low Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting +**/ + UINT32 PchUsbLtrLowIdleTimeOverride; + +/** Offset 0x1A1C - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + legacy OS using 8254 timer. Also enable this while S0ix is enabled. + $EN_DIS +**/ + UINT8 Enable8254ClockGating; + +/** Offset 0x1A1D - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS +**/ + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x1A1E - Enable TCO timer. + When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have + huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer + emulation must be enabled, and WDAT table must not be exposed to the OS. + $EN_DIS +**/ + UINT8 EnableTcoTimer; + +/** Offset 0x1A1F - Reserved +**/ + UINT8 Reserved50[9]; + +/** Offset 0x1A28 - BgpdtHash[4] + BgpdtHash values +**/ + UINT64 BgpdtHash[4]; + +/** Offset 0x1A48 - BiosGuardAttr + BiosGuardAttr default values +**/ + UINT32 BiosGuardAttr; + +/** Offset 0x1A4C - Reserved +**/ + UINT8 Reserved51[4]; + +/** Offset 0x1A50 - BiosGuardModulePtr + BiosGuardModulePtr default values +**/ + UINT64 BiosGuardModulePtr; + +/** Offset 0x1A58 - SendEcCmd + SendEcCmd function pointer. \n + @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE + EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode +**/ + UINT64 SendEcCmd; + +/** Offset 0x1A60 - EcCmdProvisionEav + Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC +**/ + UINT8 EcCmdProvisionEav; + +/** Offset 0x1A61 - EcCmdLock + EcCmdLock default values. Locks Ephemeral Authorization Value sent previously +**/ + UINT8 EcCmdLock; + +/** Offset 0x1A62 - Reserved +**/ + UINT8 Reserved52[22]; + +/** Offset 0x1A78 - Skip Ssid Programming. + When set to TRUE, silicon code will not do any SSID programming and platform code + needs to handle that by itself properly. + $EN_DIS +**/ + UINT8 SiSkipSsidProgramming; + +/** Offset 0x1A79 - Reserved +**/ + UINT8 Reserved53; + +/** Offset 0x1A7A - Change Default SVID + Change the default SVID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSvid; + +/** Offset 0x1A7C - Change Default SSID + Change the default SSID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSsid; + +/** Offset 0x1A7E - Reserved +**/ + UINT8 Reserved54[2]; + +/** Offset 0x1A80 - SVID SDID table Poniter. + The address of the table of SVID SDID to customize each SVID SDID entry. This is + only valid when SkipSsidProgramming is FALSE. +**/ + UINT64 SiSsidTablePtr; + +/** Offset 0x1A88 - Number of ssid table. + SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. + This is only valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiNumberOfSsidTableEntry; + +/** Offset 0x1A8A - USB2 Port Reset Message Enable + 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must + be enable for USB2 Port those are paired with CPU XHCI Port +**/ + UINT8 PortResetMessageEnable[16]; + +/** Offset 0x1A9A - SATA RST Interrupt Mode + Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. + 0:Msix, 1:Msi, 2:Legacy +**/ + UINT8 SataRstInterrupt; + +/** Offset 0x1A9B - Enable PS_ON. + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power + target that will be required by the California Energy Commission (CEC). When FALSE, + PS_ON is to be disabled. + $EN_DIS +**/ + UINT8 PsOnEnable; + +/** Offset 0x1A9C - Pmc Cpu C10 Gate Pin Enable + Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO + and VccSTG rails instead of SLP_S0# pin. + $EN_DIS +**/ + UINT8 PmcCpuC10GatePinEnable; + +/** Offset 0x1A9D - Pch Dmi Aspm Ctrl + ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig + 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto +**/ + UINT8 PchDmiAspmCtrl; + +/** Offset 0x1A9E - PchDmiCwbEnable + Central Write Buffer feature configurable and enabled by default + $EN_DIS +**/ + UINT8 PchDmiCwbEnable; + +/** Offset 0x1A9F - OS IDLE Mode Enable + Enable/Disable OS Idle Mode + $EN_DIS +**/ + UINT8 PmcOsIdleEnable; + +/** Offset 0x1AA0 - S0ix Auto-Demotion + Enable/Disable the Low Power Mode Auto-Demotion Host Control feature. + $EN_DIS +**/ + UINT8 PchS0ixAutoDemotion; + +/** Offset 0x1AA1 - Latch Events C10 Exit + When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are + captured on C10 exit (instead of C10 entry which is default) + $EN_DIS +**/ + UINT8 PchPmLatchEventsC10Exit; + +/** Offset 0x1AA2 - Reserved +**/ + UINT8 Reserved55[127]; + +/** Offset 0x1B21 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTranEnable[10]; + +/** Offset 0x1B2B - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 + USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default + = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTran[10]; + +/** Offset 0x1B35 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTranEnable[10]; + +/** Offset 0x1B3F - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 + USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTran[10]; + +/** Offset 0x1B49 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTranEnable[10]; + +/** Offset 0x1B53 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 + USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTran[10]; + +/** Offset 0x1B5D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTranEnable[10]; + +/** Offset 0x1B67 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 + USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTran[10]; + +/** Offset 0x1B71 - Skip PAM regsiter lock + Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): + PAM registers will be locked by RC + $EN_DIS +**/ + UINT8 SkipPamLock; + +/** Offset 0x1B72 - Enable/Disable IGFX RenderStandby + Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby + $EN_DIS +**/ + UINT8 RenderStandby; + +/** Offset 0x1B73 - Reserved +**/ + UINT8 Reserved56; + +/** Offset 0x1B74 - GT Frequency Limit + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz +**/ + UINT8 GtFreqMax; + +/** Offset 0x1B75 - Disable Turbo GT + 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency + $EN_DIS +**/ + UINT8 DisableTurboGt; + +/** Offset 0x1B76 - Reserved +**/ + UINT8 Reserved57[2]; + +/** Offset 0x1B78 - Enable TSN Multi-VC + Enable/disable Multi Virtual Channels(VC) in TSN. + $EN_DIS +**/ + UINT8 PchTsnMultiVcEnable; + +/** Offset 0x1B79 - Reserved +**/ + UINT8 Reserved58[11]; + +/** Offset 0x1B84 - LogoPixelHeight Address + Address of LogoPixelHeight +**/ + UINT32 LogoPixelHeight; + +/** Offset 0x1B88 - LogoPixelWidth Address + Address of LogoPixelWidth +**/ + UINT32 LogoPixelWidth; + +/** Offset 0x1B8C - Reserved +**/ + UINT8 Reserved59; + +/** Offset 0x1B8D - ITbt Usb4CmMode value + ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM +**/ + UINT8 Usb4CmMode; + +/** Offset 0x1B8E - Reserved +**/ + UINT8 Reserved60[75]; + +/** Offset 0x1BD9 - RSR feature + Enable or Disable RSR feature; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableRsr; + +/** Offset 0x1BDA - Reserved +**/ + UINT8 Reserved61[4]; + +/** Offset 0x1BDE - Enable or Disable HWP + Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the + CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; 1: + Enable; + $EN_DIS +**/ + UINT8 Hwp; + +/** Offset 0x1BDF - Package Long duration turbo mode time + Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 + = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window + which Processor Base Power (TDP) value should be maintained. Valid values(Unit + in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , + 80 , 96 , 112 , 128 +**/ + UINT8 PowerLimit1Time; + +/** Offset 0x1BE0 - Short Duration Turbo Mode + Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program + the default values for Power Limit 2. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PowerLimit2; + +/** Offset 0x1BE1 - Turbo settings Lock + Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT + MSR will be locked and a reset will be required to unlock the register. 0: Disable; + 1: Enable + $EN_DIS +**/ + UINT8 TurboPowerLimitLock; + +/** Offset 0x1BE2 - Package PL3 time window + Power Limit 3 Time Window value in Milli seconds. Indicates the time window over + which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves + the hardware default value. Valid value: 0, 3-8, 10, 12, 14, 16, 20, 24, + 28, 32, 40, 48, 56, 64. +**/ + UINT8 PowerLimit3Time; + +/** Offset 0x1BE3 - Package PL3 Duty Cycle + Specify the duty cycle in percentage that the CPU is required to maintain over the + configured time window. Range is 0-100. +**/ + UINT8 PowerLimit3DutyCycle; + +/** Offset 0x1BE4 - Package PL3 Lock + Power Limit 3 Lock. When enabled PL3 configurations are locked during OS. When disabled + PL3 configuration can be changed during OS. 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT8 PowerLimit3Lock; + +/** Offset 0x1BE5 - Package PL4 Lock + Power Limit 4 Lock. When enabled PL4 configurations are locked during OS. When disabled + PL4 configuration can be changed during OS. 0: Disable ; 1:Enable + $EN_DIS +**/ + UINT8 PowerLimit4Lock; + +/** Offset 0x1BE6 - TCC Activation Offset + TCC Activation Offset. Offset from factory set TCC activation temperature at which + the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation + Temperature, in volts. Default = 0h. +**/ + UINT8 TccActivationOffset; + +/** Offset 0x1BE7 - Tcc Offset Clamp Enable/Disable + Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle + below P1. 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 TccOffsetClamp; + +/** Offset 0x1BE8 - Tcc Offset Lock + Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature + target; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 TccOffsetLock; + +/** Offset 0x1BE9 - Custom Ratio State Entries + The number of custom ratio state entries, ranges from 0 to 40 for a valid custom + ratio table. Sets the number of custom P-states. At least 2 states must be present +**/ + UINT8 NumberOfEntries; + +/** Offset 0x1BEA - Custom Short term Power Limit time window + Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 + = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window + which Processor Base Power (TDP) value should be maintained. +**/ + UINT8 Custom1PowerLimit1Time; + +/** Offset 0x1BEB - Custom Turbo Activation Ratio + Custom value for Turbo Activation Ratio. Needs to be configured with valid values + from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255 +**/ + UINT8 Custom1TurboActivationRatio; + +/** Offset 0x1BEC - Custom Config Tdp Control + Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level + 1. Valid Range is 0 to 2 +**/ + UINT8 Custom1ConfigTdpControl; + +/** Offset 0x1BED - Custom Short term Power Limit time window + Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 + = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window + which Processor Base Power (TDP) value should be maintained. +**/ + UINT8 Custom2PowerLimit1Time; + +/** Offset 0x1BEE - Custom Turbo Activation Ratio + Custom value for Turbo Activation Ratio. Needs to be configured with valid values + from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255 +**/ + UINT8 Custom2TurboActivationRatio; + +/** Offset 0x1BEF - Custom Config Tdp Control + Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level + 1. Valid Range is 0 to 2 +**/ + UINT8 Custom2ConfigTdpControl; + +/** Offset 0x1BF0 - Custom Short term Power Limit time window + Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 + = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window + which Processor Base Power (TDP) value should be maintained. +**/ + UINT8 Custom3PowerLimit1Time; + +/** Offset 0x1BF1 - Custom Turbo Activation Ratio + Custom value for Turbo Activation Ratio. Needs to be configured with valid values + from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255 +**/ + UINT8 Custom3TurboActivationRatio; + +/** Offset 0x1BF2 - Custom Config Tdp Control + Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level + 1. Valid Range is 0 to 2 +**/ + UINT8 Custom3ConfigTdpControl; + +/** Offset 0x1BF3 - ConfigTdp mode settings Lock + cTDP(Assured Power) Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL. + Note: When CTDP(Assured Power) Lock is enabled Custom ConfigTDP Count will be forced + to 1 and Custom ConfigTDP Boot Index will be forced to 0. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ConfigTdpLock; + +/** Offset 0x1BF4 - Load Configurable TDP SSDT + Enables cTDP(Assured Power) control via runtime ACPI BIOS methods. This 'BIOS only' + feature does not require EC or driver support. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ConfigTdpBios; + +/** Offset 0x1BF5 - PL1 Enable value + Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it + activates the PL1 value to be used by the processor to limit the average power + of given time window. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit1; + +/** Offset 0x1BF6 - PL1 timewindow + Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to + 128. 0 = default values. Indicates the time window over which Platform Processor + Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to + 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 +**/ + UINT8 PsysPowerLimit1Time; + +/** Offset 0x1BF7 - PL2 Enable Value + Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS + will program the default values for Platform Power Limit 2. 0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit2; + +/** Offset 0x1BF8 - Enable or Disable MLC Streamer Prefetcher + Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MlcStreamerPrefetcher; + +/** Offset 0x1BF9 - Enable or Disable MLC Spatial Prefetcher + Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 MlcSpatialPrefetcher; + +/** Offset 0x1BFA - Enable or Disable Monitor /MWAIT instructions + Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner + should not set in MWAIT Loop. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MonitorMwaitEnable; + +/** Offset 0x1BFB - Enable or Disable initialization of machine check registers + Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MachineCheckEnable; + +/** Offset 0x1BFC - AP Idle Manner of waiting for SIPI + AP threads Idle Manner for waiting signal to run. 1: HALT loop; 2: MWAIT loop; + 3: RUN loop. + 1: HALT loop, 2: MWAIT loop, 3: RUN loop +**/ + UINT8 ApIdleManner; + +/** Offset 0x1BFD - Control on Processor Trace output scheme + Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. + 0: Single Range Output, 1: ToPA Output +**/ + UINT8 ProcessorTraceOutputScheme; + +/** Offset 0x1BFE - Enable or Disable Processor Trace feature + Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ProcessorTraceEnable; + +/** Offset 0x1BFF - Enable or Disable Intel SpeedStep Technology + Allows more than two frequency ranges to be supported. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Eist; + +/** Offset 0x1C00 - Enable or Disable Energy Efficient P-state + Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access + to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support + for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS + MSR and CPUID Function will read 1 indicating Energy Efficient policy setting is + supported. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientPState; + +/** Offset 0x1C01 - Enable or Disable Energy Efficient Turbo + Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically + lower the turbo frequency to increase efficiency. Recommended only to disable in + overclocking situations where turbo frequency must remain constant. Otherwise, + leave enabled. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientTurbo; + +/** Offset 0x1C02 - Enable or Disable T states + Enable or Disable T states; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TStates; + +/** Offset 0x1C03 - Enable or Disable Bi-Directional PROCHOT# + Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 BiProcHot; + +/** Offset 0x1C04 - Enable or Disable PROCHOT# signal being driven externally + Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DisableProcHotOut; + +/** Offset 0x1C05 - Enable or Disable PROCHOT# Response + Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ProcHotResponse; + +/** Offset 0x1C06 - Enable or Disable VR Thermal Alert + Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DisableVrThermalAlert; + +/** Offset 0x1C07 - Enable or Disable Thermal Reporting + Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 EnableAllThermalFunctions; + +/** Offset 0x1C08 - Enable or Disable Thermal Monitor + Enable or Disable Thermal Monitor; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ThermalMonitor; + +/** Offset 0x1C09 - Enable or Disable CPU power states (C-states) + Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not + 100% utilized. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Cx; + +/** Offset 0x1C0A - Configure C-State Configuration Lock + Configure MSR to CFG Lock bit. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PmgCstCfgCtrlLock; + +/** Offset 0x1C0B - Enable or Disable Enhanced C-states + Enable/Disable C1E. When enabled, CPU will switch to minimum speed when all cores + enter C-State. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1e; + +/** Offset 0x1C0C - Enable or Disable Package Cstate Demotion + Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PkgCStateDemotion; + +/** Offset 0x1C0D - Enable or Disable Package Cstate UnDemotion + Enable or Disable Package C-State Un-Demotion. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PkgCStateUnDemotion; + +/** Offset 0x1C0E - Enable or Disable CState-Pre wake + Disable - to disable the Cstate Pre-Wake. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 CStatePreWake; + +/** Offset 0x1C0F - Enable or Disable TimedMwait Support. + Enable or Disable TimedMwait Support. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 TimedMwait; + +/** Offset 0x1C10 - Enable or Disable IO to MWAIT redirection + When set, will map IO_read instructions sent to IO registers PMG_IO_BASE_ADDRBASE+offset + to MWAIT(offset). 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CstCfgCtrIoMwaitRedirection; + +/** Offset 0x1C11 - Set the Max Pkg Cstate + Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value. + Auto: Initializes to deepest available Package C State Limit. Valid values 0 - + C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 - + CPU Default, 255 - Auto +**/ + UINT8 PkgCStateLimit; + +/** Offset 0x1C12 - Interrupt Redirection Mode Select + Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1: + Round robin; 2: Hash vector; 7: No change. +**/ + UINT8 PpmIrmSetting; + +/** Offset 0x1C13 - Lock prochot configuration + Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ProcHotLock; + +/** Offset 0x1C14 - Configuration for boot TDP selection + cTDP(Assured Power) Mode as Nominal/Level1/Level2/Deactivate TDP(Base Power) selection. + Deactivate option will set MSR to Nominal and MMIO to Zero. 0: TDP(Base Power) + Nominal; 1: TDP(Base Power) Down; 2: TDP(Base Power) Up;0xFF : Deactivate +**/ + UINT8 ConfigTdpLevel; + +/** Offset 0x1C15 - Max P-State Ratio + Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F +**/ + UINT8 MaxRatio; + +/** Offset 0x1C16 - P-state ratios for custom P-state table + P-state ratios for custom P-state table. NumberOfEntries has valid range between + 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] + are configurable. Valid Range of each entry is 0 to 0x7F +**/ + UINT8 StateRatio[40]; + +/** Offset 0x1C3E - P-state ratios for max 16 version of custom P-state table + P-state ratios for max 16 version of custom P-state table. This table is used for + OS versions limited to a max of 16 P-States. If the first entry of this table is + 0, or if Number of Entries is 16 or less, then this table will be ignored, and + up to the top 16 values of the StateRatio table will be used instead. Valid Range + of each entry is 0 to 0x7F +**/ + UINT8 StateRatioMax16[16]; + +/** Offset 0x1C4E - Reserved +**/ + UINT8 Reserved62[2]; + +/** Offset 0x1C50 - Package Long duration turbo mode power limit + Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between + Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit + and Processor Base Power (TDP) Limit. If value is 0, BIOS will program Processor + Base Power (TDP) value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid + Range 0 to 32767. +**/ + UINT32 PowerLimit1; + +/** Offset 0x1C54 - Package Short duration turbo mode power limit + Power Limit 2 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. If the value is 0, BIOS will program this value as 1.25*Processor + Base Power (TDP). Processor applies control policies such that the package power + does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 PowerLimit2Power; + +/** Offset 0x1C58 - Package PL3 power limit + Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. XE SKU: Any value can be programmed. Overclocking SKU: Value + must be between Max and Min Power Limits. Other SKUs: This value must be between + Min Power Limit and Processor Base Power (TDP) Limit. If the value is 0, BIOS leaves + the hardware default value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 PowerLimit3; + +/** Offset 0x1C5C - Package PL4 power limit + Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. If the value is 0, BIOS leaves default value. Units are based + on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767. +**/ + UINT32 PowerLimit4; + +/** Offset 0x1C60 - Reserved +**/ + UINT8 Reserved63[4]; + +/** Offset 0x1C64 - Tcc Offset Time Window for RATL +**/ + UINT32 TccOffsetTimeWindowForRatl; + +/** Offset 0x1C68 - Short term Power Limit value for custom cTDP level 1 + Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between + Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit + and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom1PowerLimit1; + +/** Offset 0x1C6C - Long term Power Limit value for custom cTDP level 1 + Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Processor applies control policies + such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom1PowerLimit2; + +/** Offset 0x1C70 - Short term Power Limit value for custom cTDP level 2 + Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between + Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit + and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom2PowerLimit1; + +/** Offset 0x1C74 - Long term Power Limit value for custom cTDP level 2 + Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Processor applies control policies + such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom2PowerLimit2; + +/** Offset 0x1C78 - Short term Power Limit value for custom cTDP level 3 + Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between + Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit + and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom3PowerLimit1; + +/** Offset 0x1C7C - Long term Power Limit value for custom cTDP level 3 + Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. + Value set 120 = 15W. 0 = no custom override. Processor applies control policies + such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 Custom3PowerLimit2; + +/** Offset 0x1C80 - Platform PL1 power + Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W + when programming. Value set 120 = 15W. Any value can be programmed between Max + and Min Power Limits. This setting will act as the new PL1 value for the Package + RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range + 0 to 32767. +**/ + UINT32 PsysPowerLimit1Power; + +/** Offset 0x1C84 - Platform PL2 power + Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W + when programming. Value set 120 = 15W. Any value can be programmed between Max + and Min Power Limits. This setting will act as the new Max Turbo Power (PL2) value + for the Package RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 32767. +**/ + UINT32 PsysPowerLimit2Power; + +/** Offset 0x1C88 - Reserved +**/ + UINT8 Reserved64; + +/** Offset 0x1C89 - Race To Halt + Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency + in order to enter pkg C-State faster to reduce overall power. 0: Disable; 1: + Enable + $EN_DIS +**/ + UINT8 RaceToHalt; + +/** Offset 0x1C8A - Reserved +**/ + UINT8 Reserved65; + +/** Offset 0x1C8B - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT + Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 HwpInterruptControl; + +/** Offset 0x1C8C - Reserved +**/ + UINT8 Reserved66[4]; + +/** Offset 0x1C90 - Enable or Disable C1 Cstate Demotion + Enable or Disable C1 Cstate Auto Demotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1StateAutoDemotion; + +/** Offset 0x1C91 - Enable or Disable C1 Cstate UnDemotion + Enable or Disable C1 Cstate Un-Demotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1StateUnDemotion; + +/** Offset 0x1C92 - Minimum Ring ratio limit override + Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo + ratio limit +**/ + UINT8 MinRingRatioLimit; + +/** Offset 0x1C93 - Maximum Ring ratio limit override + Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo + ratio limit +**/ + UINT8 MaxRingRatioLimit; + +/** Offset 0x1C94 - Enable or Disable Per Core P State OS control + Enable/Disable Per Core P state OS control mode. When set, the highest core request + is used for all other core requests. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnablePerCorePState; + +/** Offset 0x1C95 - Enable or Disable HwP Autonomous Per Core P State OS control + Disable Autonomous PCPS Autonomous will request the same value for all cores all + the time. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableHwpAutoPerCorePstate; + +/** Offset 0x1C96 - Enable or Disable HwP Autonomous EPP Grouping + Enable EPP grouping Autonomous will request the same values for all cores with same + EPP. Disable EPP grouping autonomous will not necessarily request same values for + all cores with same EPP. 0: Disable ; 1: Enable + $EN_DIS +**/ + UINT8 EnableHwpAutoEppGrouping; + +/** Offset 0x1C97 - Enable Configurable TDP + Applies cTDP(Assured Power) initialization settings based on non-cTDP(Assured Power) + or cTDP(Assured Power). Default is 1: Applies to cTDP(Assured Power); if 0 then + applies non-cTDP(Assured Power) and BIOS will bypass cTDP(Assured Power) initialzation flow + $EN_DIS +**/ + UINT8 ApplyConfigTdp; + +/** Offset 0x1C98 - Reserved +**/ + UINT8 Reserved67; + +/** Offset 0x1C99 - Dual Tau Boost + Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W + sku. When DPTF is enabled this feature is ignored. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 DualTauBoost; + +/** Offset 0x1C9A - Reserved +**/ + UINT8 Reserved68[34]; + +/** Offset 0x1CBC - End of Post message + Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): + EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE + 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved +**/ + UINT8 EndOfPostMessage; + +/** Offset 0x1CBD - D0I3 Setting for HECI Disable + Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all + HECI devices + $EN_DIS +**/ + UINT8 DisableD0I3SettingForHeci; + +/** Offset 0x1CBE - Mctp Broadcast Cycle + Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MctpBroadcastCycle; + +/** Offset 0x1CBF - ME Unconfig on RTC clear + 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. + 2: Cmos is clear, status unkonwn. 3: Reserved + 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos + is clear, 3: Reserved +**/ + UINT8 MeUnconfigOnRtcClear; + +/** Offset 0x1CC0 - Enforce Enhanced Debug Mode + Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 EnforceEDebugMode; + +/** Offset 0x1CC1 - Reserved +**/ + UINT8 Reserved69[17]; + +/** Offset 0x1CD2 - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + UINT8 PchLockDownGlobalSmi; + +/** Offset 0x1CD3 - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + UINT8 PchLockDownBiosInterface; + +/** Offset 0x1CD4 - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. + $EN_DIS +**/ + UINT8 PchUnlockGpioPads; + +/** Offset 0x1CD5 - PCH Unlock SideBand access + The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before + 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. + $EN_DIS +**/ + UINT8 PchSbAccessUnlock; + +/** Offset 0x1CD6 - Reserved +**/ + UINT8 Reserved70[2]; + +/** Offset 0x1CD8 - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 PcieRpLtrMaxSnoopLatency[29]; + +/** Offset 0x1D12 - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 PcieRpLtrMaxNoSnoopLatency[29]; + +/** Offset 0x1D4C - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 PcieRpSnoopLatencyOverrideMode[29]; + +/** Offset 0x1D69 - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpSnoopLatencyOverrideMultiplier[29]; + +/** Offset 0x1D86 - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 PcieRpSnoopLatencyOverrideValue[29]; + +/** Offset 0x1DC0 - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMode[29]; + +/** Offset 0x1DDD - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[29]; + +/** Offset 0x1DFA - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 PcieRpNonSnoopLatencyOverrideValue[29]; + +/** Offset 0x1E34 - PCIE RP Slot Power Limit Scale + Specifies scale used for slot power limit value. Leave as 0 to set to default. +**/ + UINT8 PcieRpSlotPowerLimitScale[29]; + +/** Offset 0x1E51 - Reserved +**/ + UINT8 Reserved71; + +/** Offset 0x1E52 - PCIE RP Slot Power Limit Value + Specifies upper limit on power supplie by slot. Leave as 0 to set to default. +**/ + UINT16 PcieRpSlotPowerLimitValue[29]; + +/** Offset 0x1E8C - PCIE RP Enable Port8xh Decode + This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 PcieEnablePort8xhDecode; + +/** Offset 0x1E8D - PCIE Port8xh Decode Port Index + The Index of PCIe Port that is selected for Port8xh Decode (0 Based). +**/ + UINT8 PchPciePort8xhDecodePortIndex; + +/** Offset 0x1E8E - PCH Energy Reporting + Disable/Enable PCH to CPU energy report feature. + $EN_DIS +**/ + UINT8 PchPmDisableEnergyReport; + +/** Offset 0x1E8F - PCH Sata Test Mode + Allow entrance to the PCH SATA test modes. + $EN_DIS +**/ + UINT8 SataTestMode; + +/** Offset 0x1E90 - PCH USB OverCurrent mapping lock enable + If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning + that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. + $EN_DIS +**/ + UINT8 PchXhciOcLock; + +/** Offset 0x1E91 - Low Power Mode Enable/Disable config mask + Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds + to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. +**/ + UINT8 PmcLpmS0ixSubStateEnableMask; + +/** Offset 0x1E92 - Reserved +**/ + UINT8 Reserved72[105]; + +/** Offset 0x1EFB - PMC C10 dynamic threshold dajustment enable + Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs + $EN_DIS +**/ + UINT8 PmcC10DynamicThresholdAdjustment; + +/** Offset 0x1EFC - Reserved +**/ + UINT8 Reserved73[68]; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_ARCH2_UPD FspsArchUpd; + +/** Offset 0x0040 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x1F40 +**/ + UINT8 Rsvd600[6]; + +/** Offset 0x1F46 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/MemInfoHob.h new file mode 100644 index 0000000..56af141 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/MemInfoHob.h @@ -0,0 +1,344 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + +@copyright + INTEL CONFIDENTIAL + Copyright 1999 - 2022 Intel Corporation. + + The source code contained or described herein and all documents related to the + source code ("Material") are owned by Intel Corporation or its suppliers or + licensors. Title to the Material remains with Intel Corporation or its suppliers + and licensors. The Material may contain trade secrets and proprietary and + confidential information of Intel Corporation and its suppliers and licensors, + and is protected by worldwide copyright and trade secret laws and treaty + provisions. No part of the Material may be used, copied, reproduced, modified, + published, uploaded, posted, transmitted, distributed, or disclosed in any way + without Intel's prior express written permission. + + No license under any patent, copyright, trade secret or other intellectual + property right is granted to or conferred upon you by disclosure or delivery + of the Materials, either expressly, by implication, inducement, estoppel or + otherwise. Any license under such intellectual property rights must be + express and approved by Intel in writing. + + Unless otherwise agreed by Intel in writing, you may not remove or alter + this notice or any other notice embedded in Materials by Intel or + Intel's suppliers or licensors in any way. + + This file contains an 'Intel Peripheral Driver' and is uniquely identified as + "Intel Reference Module" and is licensed for Intel CPUs and chipsets under + the terms of your license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the license agreement. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryS3Data2Guid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 2 +#define MAX_CH 4 +#define MAX_DDR5_CH 2 +#define MAX_DIMM 2 +// Must match definitions in +// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h +#define HOB_MAX_SAGV_POINTS 4 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef __MRC_BOOT_MODE__ +#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h + #ifndef INT32_MAX + #define INT32_MAX (0x7FFFFFFF) + #endif //INT32_MAX +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. + MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. +} MRC_BOOT_MODE; +#endif //__MRC_BOOT_MODE__ + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR5 +#define MRC_DDR_TYPE_DDR5 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR5 +#define MRC_DDR_TYPE_LPDDR5 2 +#endif +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 4 +#endif + +#define MAX_PROFILE_NUM 7 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported + +#ifndef MAX_RCOMP_TARGETS +#define MAX_RCOMP_TARGETS 5 +#endif + +#ifndef MAX_ODT_ENTRIES +#define MAX_ODT_ENTRIES 11 +#endif + +#define MAX_TRACE_REGION 5 +#define MAX_TRACE_CACHE_TYPE 2 + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. + UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group. +} MRC_CH_TIMING; + +typedef struct { + UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay +} MRC_IP_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz + UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. +} CONTROLLER_INFO; + +typedef struct { + UINT64 BaseAddress; ///< Trace Base Address + UINT64 TotalSize; ///< Total Trace Region of Same Cache type + UINT8 CacheType; ///< Trace Cache Type + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code + UINT8 Rsvd[2]; +} PSMI_MEM_INFO; + +/// This data structure contains per-SaGv timing values that are considered output by the MRC. +typedef struct { + UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s + MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec + MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific +} HOB_SAGV_TIMING_OUT; + +/// This data structure contains SAGV config values that are considered output by the MRC. +typedef struct { + UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. + UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. + HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; +} HOB_SAGV_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of this memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed + BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. + UINT16 Ratio; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + UINT32 VddqVoltage[MAX_PROFILE_NUM]; + UINT32 VppVoltage[MAX_PROFILE_NUM]; + UINT16 RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS]; + UINT16 DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES]; + CONTROLLER_INFO Controller[MAX_NODE]; + UINT32 NumPopulatedChannels; ///< Total number of memory channels populated + HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. + BOOLEAN IsIbeccEnabled; + UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels + UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows + UINT16 PprRepairFails; ///< PPR: Counts of repair failure + UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT64 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; + PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; + BOOLEAN MrcBasicMemoryTestPass; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ -- To view, visit https://review.coreboot.org/c/coreboot/+/82473?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib41b57e794311db729ac65a968f562aa127e86c3 Gerrit-Change-Number: 82473 Gerrit-PatchSet: 11 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: vc/intel/fsp/mtl: Organize FSP headers into x86_32 directory
by Subrata Banik (Code Review) 30 May '24

30 May '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82424?usp=email ) Change subject: vc/intel/fsp/mtl: Organize FSP headers into x86_32 directory ...................................................................... vc/intel/fsp/mtl: Organize FSP headers into x86_32 directory This commit moves FSP V3471.91 header files for Meteor Lake into a new x86_32 directory to better organize the files based on the architecture. The Kconfig file has been modified accordingly to reflect the new paths of the relocated headers. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Id30186a8b1b5a9082f498e18a3378f5e9907b668 Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82424 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/meteorlake/Kconfig R src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FirmwareVersionInfo.h R src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspProducerDataHeader.h R src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspUpd.h R src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspmUpd.h R src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspsUpd.h R src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/MemInfoHob.h 7 files changed, 1 insertion(+), 1 deletion(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Dinesh Gehlot: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index a4ebad4..43f6545 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -347,7 +347,7 @@ config FSP_HEADER_PATH string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/" + default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/" config FSP_FD_PATH string diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FirmwareVersionInfo.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FirmwareVersionInfo.h similarity index 100% rename from src/vendorcode/intel/fsp/fsp2_0/meteorlake/FirmwareVersionInfo.h rename to src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FirmwareVersionInfo.h diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspProducerDataHeader.h similarity index 100% rename from src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h rename to src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspProducerDataHeader.h diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspUpd.h similarity index 100% rename from src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspUpd.h rename to src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspUpd.h diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspmUpd.h similarity index 100% rename from src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h rename to src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspmUpd.h diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspsUpd.h similarity index 100% rename from src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h rename to src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspsUpd.h diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/MemInfoHob.h similarity index 100% rename from src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h rename to src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/MemInfoHob.h -- To view, visit https://review.coreboot.org/c/coreboot/+/82424?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id30186a8b1b5a9082f498e18a3378f5e9907b668 Gerrit-Change-Number: 82424 Gerrit-PatchSet: 15 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility
by Subrata Banik (Code Review) 30 May '24

30 May '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82177?usp=email ) Change subject: soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility ...................................................................... soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility This commit updates the type definitions for FSP parameters in the Meteor Lake platform to ensure compatibility with the FSP2.4 specification, that supports 64-bit builds for the first time and this also ensures that parameter types works for both 32-bit and 64-bit builds. - In fsp_params.c, FSPS_ARCH_UPD macro is changed to FSPS_ARCHx_UPD which supports FSP2.4 and older specifications. Special handling is added for FspEventHandler assignment to handle as the variable type is different in both cases. - In meminit.c, the type for SPD pointers is changed from uint32_t to efi_uintn_t to support both 32-bit and 64-bit builds. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82177 Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/meteorlake/meminit.c M src/soc/intel/meteorlake/romstage/fsp_params.c 3 files changed, 15 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index a02d4b9..0ac3b48 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -703,7 +703,7 @@ printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); } -static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) +static void arch_silicon_init_params(FSPS_ARCHx_UPD *s_arch_cfg) { /* * EnableMultiPhaseSiliconInit for running MultiPhaseSiInit @@ -713,8 +713,14 @@ /* Assign FspEventHandler arch Upd to use coreboot debug event handler */ if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) + +#if CONFIG(PLATFORM_USES_FSP2_X86_32) s_arch_cfg->FspEventHandler = (FSP_EVENT_HANDLER) fsp_debug_event_handler; +#else + s_arch_cfg->FspEventHandler = (EFI_PHYSICAL_ADDRESS) + fsp_debug_event_handler; +#endif } static void evaluate_ssid(const struct device *dev, uint16_t *svid, uint16_t *ssid) @@ -822,7 +828,7 @@ { struct soc_intel_meteorlake_config *config; FSP_S_CONFIG *s_cfg = &supd->FspsConfig; - FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; + FSPS_ARCHx_UPD *s_arch_cfg = &supd->FspsArchUpd; config = config_of_soc(); arch_silicon_init_params(s_arch_cfg); diff --git a/src/soc/intel/meteorlake/meminit.c b/src/soc/intel/meteorlake/meminit.c index fa7e1fd..32ab358 100644 --- a/src/soc/intel/meteorlake/meminit.c +++ b/src/soc/intel/meteorlake/meminit.c @@ -77,7 +77,7 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) { - uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { + efi_uintn_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, [1] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, }, [2] = { &mem_cfg->MemorySpdPtr020, &mem_cfg->MemorySpdPtr021, }, @@ -106,7 +106,7 @@ bool enable_channel = 0; for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { - uint32_t *spd_ptr = spd_upds[ch][dimm]; + efi_uintn_t *spd_ptr = spd_upds[ch][dimm]; *spd_ptr = data->spd[ch][dimm]; if (*spd_ptr) diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index caf57a3..0f44d65 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -446,7 +446,7 @@ #define VGA_INIT_CONTROL_TEAR_DOWN BIT(1) static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg, - FSPM_ARCH_UPD *arch_upd) + FSPM_ARCHx_UPD *arch_upd) { void *vbt; size_t vbt_size; @@ -485,22 +485,22 @@ elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, sol_type); m_cfg->VgaInitControl = vga_init_control; - m_cfg->VbtPtr = (UINT32)vbt; + m_cfg->VbtPtr = (efi_uintn_t)vbt; m_cfg->VbtSize = vbt_size; m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); - m_cfg->VgaMessage = (UINT32)text; + m_cfg->VgaMessage = (efi_uintn_t)text; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct soc_intel_meteorlake_config *config; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd; if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) { if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) { enum fsp_log_level log_level = fsp_map_console_log_level(); - arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) + arch_upd->FspEventHandler = (efi_uintn_t)((FSP_EVENT_HANDLER *) fsp_debug_event_handler); /* Set Serial debug message level */ m_cfg->PcdSerialDebugLevel = log_level; -- To view, visit https://review.coreboot.org/c/coreboot/+/82177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a Gerrit-Change-Number: 82177 Gerrit-PatchSet: 20 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: vc/edk2-stable202302: Add config guards to support FSP 2.4
by Subrata Banik (Code Review) 30 May '24

30 May '24

Attention is currently required from: Appukuttan V K, Ronak Kanabar. Subrata Banik has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82425?usp=email ) Change subject: vc/edk2-stable202302: Add config guards to support FSP 2.4 ...................................................................... Patch Set 23: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82425/comment/4d6f2815_d4ed69e7?us… : PS23, Line 21: b:343428206 please specify the child bugs if you have created any to fix the EDK2 cherrypicks as well here. -- To view, visit https://review.coreboot.org/c/coreboot/+/82425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Gerrit-Change-Number: 82425 Gerrit-PatchSet: 23 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 30 May 2024 13:21:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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