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Change subject: mb/siemens/mc_ehl5: Remove DDI settings from devicetree
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Patch Set 2: Code-Review+2
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Change subject: soc/intel/xeon-sp: Hook up public FSP bin and headers
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> I don't follow, is this on purpose that FSP-S returns with paging enabled? […]
Very interesting, this seems related to my findings while porting coreboot 64-bit to ASRock SPC741d8, see CB:82206. Maybe a bug in FSP? It seems very counter-intuitive that FSP wouldn't revert any such changes done during its execution.
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Change subject: util/cbfstool: Disable paging for linux payload
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Hi Nico! It is for enabling https://review.coreboot. […]
This would affect coreboot's ramstage and other payloads, too. Everything
expects paging to be disabled.
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Change subject: soc/intel/xeon-sp: Hook up public FSP bin and headers
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> Thanks all for the patience. We confirmed the path to move forward on this together with you. […]
I don't follow, is this on purpose that FSP-S returns with paging enabled?
Is FSP even allowed to do that?
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Change subject: util/cbfstool: Disable paging for linux payload
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> I might just miss it. […]
Hi Nico! It is for enabling https://review.coreboot.org/c/coreboot/+/80360 to use public FSP headers and binary, where the public FSP binary is built with PcdMigrateTemporaryRamFirmwareVolumes = TRUE, where FSP-S will enable paging and breaks the Linux payloads's 32bit kernel handover.
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Change subject: util/cbfstool: Disable paging for linux payload
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
I might just miss it. When/why do we expect paging to be enabled?
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Change subject: util/cbfstool: Fix linux_trampoline.c generation
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Patch Set 1: Code-Review+2
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Change subject: util/cbfstool: Disable paging for linux payload
......................................................................
util/cbfstool: Disable paging for linux payload
cbfs linux payload follows 32 bit kernel boot protocol.
Per kernel spec requires, paging should be disabled.
Enforce 32 bit paging disabling in the trampoline codes.
Reference:
https://www.kernel.org/doc/Documentation/x86/boot.rst
TEST=Build and boot on intel/archercity CRB
Change-Id: I50a4ab2664910e5772b90b3dade8866f28361d87
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Co-authored-by: Gang Chen <gang.c.chen(a)intel.com>
---
M util/cbfstool/linux_trampoline.S
M util/cbfstool/linux_trampoline.c
2 files changed, 10 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/82705/2
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Change subject: soc/intel/xeon-sp: Hook up public FSP bin and headers
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> Thanks for working on this. […]
Thanks all for the patience. We confirmed the path to move forward on this together with you.
Public FSP is built with PcdMigrateTemporaryRamFirmwareVolumes = TRUE, where FSP-S will enable paging and breaks the Linux payloads's 32bit kernel handover. Below improvements could help to mitigate.
https://review.coreboot.org/c/coreboot/+/82705https://review.coreboot.org/c/coreboot/+/82704
Now, CL80360 could boot UEFI and Linux payload (with CL82704/82705) both.
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Change subject: soc/intel/xeon-sp: Hook up public FSP bin and headers
......................................................................
Patch Set 4: Code-Review+2
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