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Change subject: mb/google/brya/var/nova: Update USB ports setting
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82703/comment/39670e1b_ba031c46?us… :
PS1, Line 9: Enable USB ports for nova.
> describe the issue here?
Done
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Change subject: mb/google/nissa/var/pujjoga: Add wifi sar table
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/pujjoga/variant.c:
https://review.coreboot.org/c/coreboot/+/82702/comment/5b9d23c3_4a9af2cd?us… :
PS3, Line 4: #include <baseboard/variants.h>
> do you need this?
Don't need, remove it.
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I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/nissa/var/pujjoga: Add wifi sar table
......................................................................
mb/google/nissa/var/pujjoga: Add wifi sar table
Add wifi sar table for pujjoga intel wifi config.
Use fw_config to separate different wifi card settings.
WIFI_SAR_TABLE_AX211: 0
WIFI_SAR_TABLE_AX203: 1
BUG=b:336167281
Test=emerge-nissa coreboot
Change-Id: If0f542cb13e93e99960bf65d616b26cee7617a43
Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/pujjoga/Makefile.mk
M src/mainboard/google/brya/variants/pujjoga/overridetree.cb
A src/mainboard/google/brya/variants/pujjoga/variant.c
4 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/82702/4
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Change subject: soc/intel/skylake: Drop redundant PcieRpEnable
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/razer/blade_stealth_kbl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/79917/comment/87cea7d1_455f2410?us… :
PS2, Line 190: device ref pcie_rp1 on end
> > The PCI specification says that multi-function devices must always implement function 0. […]
Ah, if `PcieRpEnable` is not set for RP1, then `pcie_rp1` can indeed be dropped then.
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Change subject: mb/google/brya/var/nova: Enable USB ports
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82703/comment/fba1ab71_ead72b83?us… :
PS1, Line 9: Enable USB ports for nova.
describe the issue here?
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Change subject: mb/google/nissa/var/pujjoga: Add wifi sar table
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/pujjoga/variant.c:
https://review.coreboot.org/c/coreboot/+/82702/comment/ea4728ba_433dcb8f?us… :
PS3, Line 4: #include <baseboard/variants.h>
do you need this?
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/google/nissa/var/pujjoga: Add wifi sar table
......................................................................
mb/google/nissa/var/pujjoga: Add wifi sar table
Add wifi sar table for pujjoga intel wifi config.
Use fw_config to separate different wifi card settings.
Intel Wifi card AX211: 0
Intel Wifi card AX203: 1
BUG=b:336167281
Test=emerge-nissa coreboot
Change-Id: If0f542cb13e93e99960bf65d616b26cee7617a43
Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/pujjoga/Makefile.mk
M src/mainboard/google/brya/variants/pujjoga/overridetree.cb
A src/mainboard/google/brya/variants/pujjoga/variant.c
4 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/82702/3
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