coreboot-gerrit May 2024

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[S] Change in coreboot[main]: util/cbfstool: Disable paging for linux payload
by Shuo Liu (Code Review) 30 May '24

30 May '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82705?usp=email ) Change subject: util/cbfstool: Disable paging for linux payload ...................................................................... util/cbfstool: Disable paging for linux payload cbfs linux payload follows 32 bit kenrel boot protocol. Per kernel spec requires, paging should be disabled. Enforce 32 bit paging disabling in the trampoline codes. Reference: https://www.kernel.org/doc/Documentation/x86/boot.rst TEST=Build and boot on intel/archercity CRB Change-Id: I50a4ab2664910e5772b90b3dade8866f28361d87 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Co-authored-by: Gang Chen <gang.c.chen(a)intel.com> --- M util/cbfstool/linux_trampoline.S M util/cbfstool/linux_trampoline.c 2 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/82705/1 diff --git a/util/cbfstool/linux_trampoline.S b/util/cbfstool/linux_trampoline.S index 4f61209..0161984 100644 --- a/util/cbfstool/linux_trampoline.S +++ b/util/cbfstool/linux_trampoline.S @@ -21,6 +21,8 @@ #define LINUX_ENTRY_OFFSET 0x214 #define E820_OFFSET 0x2d0 +#define CR0_PG (1 << 31) + .trampoline_start: cld xor %edx, %edx @@ -185,6 +187,10 @@ movl %eax, 2(%eax) // Set pointer to new GDT lgdt (%eax) // Load it +movl %cr0, %eax +andl $(~(CR0_PG)), %eax // Disable paging +movl %eax, %cr0 + /* finally: jump to kernel */ mov $LINUX_PARAM_LOC, %esi jmp *(LINUX_PARAM_LOC + LINUX_ENTRY_OFFSET) diff --git a/util/cbfstool/linux_trampoline.c b/util/cbfstool/linux_trampoline.c index 13c0edb..6ec90bf 100644 --- a/util/cbfstool/linux_trampoline.c +++ b/util/cbfstool/linux_trampoline.c @@ -3,7 +3,7 @@ unsigned char trampoline[] = { 0xfc, 0x31, 0xd2, 0xb9, 0x00, 0x00, 0x00, 0x00, 0xbb, 0x00, 0x00, 0x01, 0x00, 0x01, 0xcb, 0x8b, 0x01, 0x3d, 0x4c, 0x42, 0x49, 0x4f, 0x74, 0x07, 0x83, 0xc1, 0x10, 0x39, 0xcb, 0x75, 0xe9, 0x39, - 0xcb, 0x0f, 0x84, 0x47, 0x01, 0x00, 0x00, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, + 0xcb, 0x0f, 0x84, 0x52, 0x01, 0x00, 0x00, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, 0x3b, 0x11, 0x75, 0x05, 0x8b, 0x4b, 0x08, 0xeb, 0xcf, 0x83, 0x3b, 0x01, 0x75, 0x70, 0x8b, 0x43, 0x04, 0x83, 0xe8, 0x08, 0xc1, 0xe8, 0x02, 0x66, 0x81, 0x3d, 0x06, 0x02, 0x09, 0x00, 0x04, 0x02, 0x7d, 0x0e, 0x3d, 0xa0, 0x00, 0x00, 0x00, 0x7e, 0x13, 0xb8, 0xa0, 0x00, 0x00, 0x00, 0xeb, 0x0c, @@ -23,7 +23,7 @@ 0x5b, 0x04, 0x49, 0x0f, 0x85, 0xf6, 0xfe, 0xff, 0xff, 0xb8, 0x00, 0x00, 0x04, 0x00, 0xc7, 0x40, 0x10, 0xff, 0xff, 0x00, 0x00, 0xc7, 0x40, 0x14, 0x00, 0x9b, 0xcf, 0x00, 0xc7, 0x40, 0x18, 0xff, 0xff, 0x00, 0x00, 0xc7, 0x40, 0x1c, 0x00, 0x93, 0xcf, 0x00, 0xc6, 0x00, 0x2b, 0x89, 0x40, 0x02, - 0x0f, 0x01, 0x10, 0xbe, 0x00, 0x00, 0x09, 0x00, 0xff, 0x25, 0x14, 0x02, 0x09, 0x00, 0xf4, 0xeb, - 0xfd + 0x0f, 0x01, 0x10, 0x0f, 0x20, 0xc0, 0x25, 0xff, 0xff, 0xff, 0x7f, 0x0f, 0x22, 0xc0, 0xbe, 0x00, + 0x00, 0x09, 0x00, 0xff, 0x25, 0x14, 0x02, 0x09, 0x00, 0xf4, 0xeb, 0xfd }; -unsigned int trampoline_len = 369; +unsigned int trampoline_len = 380; -- To view, visit https://review.coreboot.org/c/coreboot/+/82705?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50a4ab2664910e5772b90b3dade8866f28361d87 Gerrit-Change-Number: 82705 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com>

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[XS] Change in coreboot[main]: util/cbfstool: Fix linux_trampoline.c generation
by Shuo Liu (Code Review) 30 May '24

30 May '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82704?usp=email ) Change subject: util/cbfstool: Fix linux_trampoline.c generation ...................................................................... util/cbfstool: Fix linux_trampoline.c generation linux_trampoline.c generation is broken with latest crossgcc-i386 toolchain. Fix the issue to enable the building. ../cbfstool/linux_trampoline.S: Assembler messages: ../cbfstool/linux_trampoline.S:100: Error: no instruction mnemonic suffix given and no register operands; can't size instruction <builtin>: recipe for target '../cbfstool/linux_trampoline.o' failed TEST=Build and boot on intel/archercity CRB Change-Id: I7faca296f946bb4e9fd510661357925e5dcf9a6b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M util/cbfstool/linux_trampoline.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/82704/1 diff --git a/util/cbfstool/linux_trampoline.S b/util/cbfstool/linux_trampoline.S index 6a62ff0..4f61209 100644 --- a/util/cbfstool/linux_trampoline.S +++ b/util/cbfstool/linux_trampoline.S @@ -97,7 +97,7 @@ cmp $12, 16(%edi) /* type */ jng .next_e820_entry /* Fixup the type to 2, reserved memory */ -mov $2, 16(%edi) +movl $2, 16(%edi) .next_e820_entry: dec %eax add $20, %edi -- To view, visit https://review.coreboot.org/c/coreboot/+/82704?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7faca296f946bb4e9fd510661357925e5dcf9a6b Gerrit-Change-Number: 82704 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com>

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[XL] Change in coreboot[main]: soc/intel/xeon-sp: Hook up public FSP bin and headers
by Shuo Liu (Code Review) 30 May '24

30 May '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Singer, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Srinidhi N Kaushik, Tim Chu. Shuo Liu has uploaded a new patch set (#4) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/80360?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Code-Review+1 by Johnny Lin Change subject: soc/intel/xeon-sp: Hook up public FSP bin and headers ...................................................................... soc/intel/xeon-sp: Hook up public FSP bin and headers TEST=Build and boot on intel/archercity CRB Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I778d3535c273dff653330518653bdefcb45e66f4 --- M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/intel/xeon_sp/spr/Makefile.mk M src/soc/intel/xeon_sp/spr/romstage.c D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FsptUpd.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h 8 files changed, 8 insertions(+), 1,798 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/80360/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/80360?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I778d3535c273dff653330518653bdefcb45e66f4 Gerrit-Change-Number: 80360 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <kaushiksrinidhin(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Fabian Meyer <fabian(a)meyfa.net> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Srinidhi N Kaushik <kaushiksrinidhin(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: vc/edk2-stable202302: Add config guards to support FSP 2.4
by Appukuttan V K (Code Review) 30 May '24

30 May '24

Attention is currently required from: Ronak Kanabar, Subrata Banik. Appukuttan V K has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82425?usp=email ) Change subject: vc/edk2-stable202302: Add config guards to support FSP 2.4 ...................................................................... Patch Set 23: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82425/comment/2d4cfaf6_626a989c?us… : PS23, Line 16: - Guard x86_32 architecture specific structures under : PLATFORM_USES_FSP2_X86_32 config. : - Guard FSP 2.4 specific structures under PLATFORM_USES_FSP2_4 : config. > how do EDK2 manages to support 32-bit and/or 64-bit boot loader so far w/o the specific guard ? I guess the problem coming since we are using 2.3 for x32 and 2.4 for x64 build. We might need to relook how x32 and FSP2.4 guards used within coreboot. Let me get few more information. https://review.coreboot.org/c/coreboot/+/82425/comment/7313d4bc_413cf053?us… : PS23, Line 16: - Guard x86_32 architecture specific structures under : PLATFORM_USES_FSP2_X86_32 config. : - Guard FSP 2.4 specific structures under PLATFORM_USES_FSP2_4 : config. > how do EDK2 manages to support 32-bit and/or 64-bit boot loader so far w/o the specific guard ? I guess the problem that we are using FSP2.3 for x32 and FSP2.4 for x64. If both are using 2.4 version this issue should not come. File src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h: https://review.coreboot.org/c/coreboot/+/82425/comment/cfab6696_05779228?us… : PS23, Line 382: } FSPT_UPD_COMMON_FSP24; > this also should be guarded with `PLATFORM_USES_FSP2_4` FSPT is not used anywhere so it is not causing any issue. Do you want to guard this anyway. https://review.coreboot.org/c/coreboot/+/82425/comment/b1b1b196_32eef6e8?us… : PS23, Line 382: } FSPT_UPD_COMMON_FSP24; > this also should be guarded with `PLATFORM_USES_FSP2_4` FSPT is not used anywhere so it is not causing any build issue. Do you want to guard this anyway? -- To view, visit https://review.coreboot.org/c/coreboot/+/82425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Gerrit-Change-Number: 82425 Gerrit-PatchSet: 23 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 30 May 2024 10:23:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: mb/razer/blade_stealth_kbl: Add H3Q variant
by Reagan (Code Review) 30 May '24

30 May '24

Attention is currently required from: Felix Singer, Nico Huber, Paul Menzel. Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82506?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/razer/blade_stealth_kbl: Add H3Q variant ...................................................................... mb/razer/blade_stealth_kbl: Add H3Q variant The Razer Blade Stealth Kaby Lake has 2 variants. One is the H2U variant, as originally committed, with the SKU number RZ09-01962, also known as the 2016 model, and the H3Q model with SKU numbers RZ09-01963 and RZ09-01964, known as the Mid 2017 model. This commit adds support for the H3Q model. With respect to coreboot, there are few known differences: 1. Only the H2U has TPM. 2. The USB ports are different. 3. The screen size (and therefore VBIOS Table) is different. 4. The hda_verb is very slightly different. 5. The gpio is different. Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4 Signed-off-by: Reagan Bohan <xbjfk.github(a)gmail.com> --- M src/mainboard/razer/blade_stealth_kbl/Kconfig M src/mainboard/razer/blade_stealth_kbl/Kconfig.name M src/mainboard/razer/blade_stealth_kbl/Makefile.mk M src/mainboard/razer/blade_stealth_kbl/board_info.txt M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/ramstage.c M src/mainboard/razer/blade_stealth_kbl/spd/spd.h A src/mainboard/razer/blade_stealth_kbl/variants/h2u/board_info.txt R src/mainboard/razer/blade_stealth_kbl/variants/h2u/hda_verb.c R src/mainboard/razer/blade_stealth_kbl/variants/h2u/include/variant/gpio.h A src/mainboard/razer/blade_stealth_kbl/variants/h2u/overridetree.cb A src/mainboard/razer/blade_stealth_kbl/variants/h3q/board_info.txt C src/mainboard/razer/blade_stealth_kbl/variants/h3q/hda_verb.c A src/mainboard/razer/blade_stealth_kbl/variants/h3q/include/variant/gpio.h A src/mainboard/razer/blade_stealth_kbl/variants/h3q/overridetree.cb 15 files changed, 317 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/82506/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/82506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4 Gerrit-Change-Number: 82506 Gerrit-PatchSet: 10 Gerrit-Owner: Reagan <xbjfk.github(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 builds
by Appukuttan V K (Code Review) 30 May '24

30 May '24

Attention is currently required from: Subrata Banik. Appukuttan V K has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82699?usp=email ) Change subject: soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 builds ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82699/comment/ef46c1c1_90885887?us… : PS3, Line 9: EnableMultiPhaseSiliconInit upd is deprecated and has been : removed starting with v2.4 of FSP specification. > are you saying `EnableMultiPhaseSiliconInit` UPD has deprecated because it has been set to 1? (w/ FS […] It is removed from header and FSP is not depending on this UPD to enable it with 2.4. #736809 sec 6.1.3 This value is deprecated and has been removed starting with v2.4 of this specification. Multi-phase silicon initialization is mandatory for all FSP implementations compliant to v2.4 of this specification, see Section 9.11 for further details. For FSP implementations compliant to v2.2 through v2.3 of this specification, an FSP binary may optionally implement multi-phase silicon initialization, see Section 9.11 for further details. This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER is non-zero, see Section 5.1.1 for further details File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/82699/comment/53b9ecb6_0da0ca70?us… : PS3, Line 80: #if (CONFIG(FSPS_HAS_ARCH_UPD) && !CONFIG(PLATFORM_USES_FSP2_4)) > why are we disabling `EnableMultiPhaseSiliconInit` for FSP 2.4 specification? […] UPD is removed and it is not configurable in Fsp2.4. It is mandatory to support. Guarded to avoid build issues with FSP2.3 x32 builds. -- To view, visit https://review.coreboot.org/c/coreboot/+/82699?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icdbf3bacc0a05975fc941b264fd400d74f506fce Gerrit-Change-Number: 82699 Gerrit-PatchSet: 3 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 30 May 2024 09:35:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: vc/edk2-stable202302: Add config guards to support FSP 2.4
by Subrata Banik (Code Review) 30 May '24

30 May '24

Attention is currently required from: Appukuttan V K, Ronak Kanabar. Subrata Banik has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82425?usp=email ) Change subject: vc/edk2-stable202302: Add config guards to support FSP 2.4 ...................................................................... Patch Set 23: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82425/comment/b6097ab9_2dacff5e?us… : PS23, Line 16: - Guard x86_32 architecture specific structures under : PLATFORM_USES_FSP2_X86_32 config. : - Guard FSP 2.4 specific structures under PLATFORM_USES_FSP2_4 : config. how do EDK2 manages to support 32-bit and/or 64-bit boot loader so far w/o the specific guard ? File src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h: https://review.coreboot.org/c/coreboot/+/82425/comment/a2110544_fac9687f?us… : PS23, Line 382: } FSPT_UPD_COMMON_FSP24; this also should be guarded with `PLATFORM_USES_FSP2_4` -- To view, visit https://review.coreboot.org/c/coreboot/+/82425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Gerrit-Change-Number: 82425 Gerrit-PatchSet: 23 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 30 May 2024 09:05:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brya/var/nova: Update USB ports setting
by David Wu (Code Review) 30 May '24

30 May '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Kenneth Chan, Nick Vaccaro, Subrata Banik. David Wu has posted comments on this change by Kenneth Chan. ( https://review.coreboot.org/c/coreboot/+/82703?usp=email ) Change subject: mb/google/brya/var/nova: Update USB ports setting ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82703?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63cf97b23627feac05743f2a6e514a33fcaf7dff Gerrit-Change-Number: 82703 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 30 May 2024 09:02:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 builds
by Subrata Banik (Code Review) 30 May '24

30 May '24

Attention is currently required from: Andrey Petrov, Appukuttan V K, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Ronak Kanabar, Tarun. Subrata Banik has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82699?usp=email ) Change subject: soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 builds ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82699/comment/415fedd1_4b88ce1a?us… : PS3, Line 9: EnableMultiPhaseSiliconInit upd is deprecated and has been : removed starting with v2.4 of FSP specification. are you saying `EnableMultiPhaseSiliconInit` UPD has deprecated because it has been set to 1? (w/ FSP 2.4 spec) have you captured that in FSP spec File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/82699/comment/19f31283_767f7969?us… : PS3, Line 80: #if (CONFIG(FSPS_HAS_ARCH_UPD) && !CONFIG(PLATFORM_USES_FSP2_4)) why are we disabling `EnableMultiPhaseSiliconInit` for FSP 2.4 specification? ideally EnableMultiPhaseSiliconInit is viable since sometime FSP 2.1 spec onwards ? -- To view, visit https://review.coreboot.org/c/coreboot/+/82699?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icdbf3bacc0a05975fc941b264fd400d74f506fce Gerrit-Change-Number: 82699 Gerrit-PatchSet: 3 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 30 May 2024 09:02:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: vc/intel/fsp/mtl: Add x86_64 FSP V3471.91 headers
by Subrata Banik (Code Review) 30 May '24

30 May '24

Attention is currently required from: Appukuttan V K. Subrata Banik has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82473?usp=email ) Change subject: vc/intel/fsp/mtl: Add x86_64 FSP V3471.91 headers ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82473?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib41b57e794311db729ac65a968f562aa127e86c3 Gerrit-Change-Number: 82473 Gerrit-PatchSet: 10 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Comment-Date: Thu, 30 May 2024 08:49:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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