coreboot-gerrit May 2024

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[XS] Change in coreboot[main]: mb/siemens/mc_ehl5: Remove DDI settings from devicetree
by Mario Scheithauer (Code Review) 30 May '24

30 May '24

Attention is currently required from: Paul Menzel. Mario Scheithauer has posted comments on this change by Mario Scheithauer. ( https://review.coreboot.org/c/coreboot/+/82663?usp=email ) Change subject: mb/siemens/mc_ehl5: Remove DDI settings from devicetree ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82663/comment/99298c40_e2c168df?us… : PS1, Line 9: Since this mainboard no longer uses the FSP GOP driver > The GOP driver was used in the initial phase of development where we used tianocore as payload for s […] Is that enough of an explanation for you Paul? -- To view, visit https://review.coreboot.org/c/coreboot/+/82663?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9e135fbc2627546d6ef95d7d5ff3e9a9222b5d2 Gerrit-Change-Number: 82663 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 30 May 2024 05:14:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/pujjoga: Tune SX9324 register
by Leo Chou (Code Review) 30 May '24

30 May '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Leo Chou has posted comments on this change by Leo Chou. ( https://review.coreboot.org/c/coreboot/+/82689?usp=email ) Change subject: mb/google/nissa/var/pujjoga: Tune SX9324 register ...................................................................... Patch Set 3: (1 comment) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/82689/comment/a3aa5faf_f689d739?us… : PS2, Line 7: for pujjoga > no need Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82689?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I205c1f5228d792afc763a06f74a8744918e2da75 Gerrit-Change-Number: 82689 Gerrit-PatchSet: 3 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 30 May 2024 00:48:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com>

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[L] Change in coreboot[main]: soc/intel/skylake: Drop redundant PcieRpEnable
by Reagan (Code Review) 30 May '24

30 May '24

Attention is currently required from: Angel Pons, Erik van den Bogaert, Frans Hendriks, Jan Samek, Jeremy Soller, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król, Sean Rhodes, Tim Crawford. Reagan has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/79917?usp=email ) Change subject: soc/intel/skylake: Drop redundant PcieRpEnable ...................................................................... Patch Set 2: (1 comment) File src/mainboard/razer/blade_stealth_kbl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79917/comment/eefaa8af_8ff6976f?us… : PS2, Line 190: device ref pcie_rp1 on end > The PCI specification says that multi-function devices must always implement function 0. To provide flexibility, Intel allows remapping PCH PCIe root port functions so that root port 1 doesn't have to be enabled when it's not in use. > IIRC, it's because a PCI device has to have a function 0 so it can be enumerated. If the root port corresponding to function 0 isn't enabled, the PCH promotes the first enabled function to function 0. Thank you both, that makes sense. Changing `pcie_rp1` to `pcie_rp3` works fine on my variant. As for the other board, I assume that's the case too, considering `PcieRpEnable` is enabled for 3, but not 1; I believe `pcie_rp1` could be removed entirely, but I am not an expert here by any definition. Booting with the stock firmware also does not create a root port 1. -- To view, visit https://review.coreboot.org/c/coreboot/+/79917?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4 Gerrit-Change-Number: 79917 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jan Samek <samekh(a)email.cz> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Reagan <xbjfk.github(a)gmail.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Jan Samek <samekh(a)email.cz> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Wed, 29 May 2024 23:47:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Jonathon Hall <jonathon.hall(a)puri.sm> Comment-In-Reply-To: Reagan <xbjfk.github(a)gmail.com>

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[XS] Change in coreboot[main]: libpayload/libc: Include region device APIs
by Julius Werner (Code Review) 30 May '24

30 May '24

Attention is currently required from: Eran Mitrani, Kapil Porwal, Subrata Banik. Julius Werner has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/82659?usp=email ) Change subject: libpayload/libc: Include region device APIs ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > > What's the overall plan on how we want to do this CSE sync from payload thing? It looks like CL:55 […] Yes, we agree on the process. I was not talking about actually passing pointers to binaries loaded by coreboot into libpayload (we generally never do that). I was just talking about sharing code. If code is to be shared between coreboot and depthcharge, that should be through commonlib (which is linked by default into libpayload nowadays). Like I said, I'm not sure if that's a good idea in practice for this or not so you may need to explore that. But either way, like I mentioned, whether we share code or make it a completely independent implementation, I don't think depthcharge should be using the region API (because it's existing interfaces don't). -- To view, visit https://review.coreboot.org/c/coreboot/+/82659?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92a2504fcbf9035bdf3435c83eb6d5512c07a692 Gerrit-Change-Number: 82659 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 29 May 2024 22:53:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[M] Change in coreboot[main]: mb/system76: Add SPDX ID to devicetree files
by Tim Crawford (Code Review) 30 May '24

30 May '24

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82700?usp=email ) Change subject: mb/system76: Add SPDX ID to devicetree files ...................................................................... mb/system76: Add SPDX ID to devicetree files Change-Id: I55f2730f7277a3c699b86ded5864e9690d92d518 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/addw1/variants/addw1/overridetree.cb M src/mainboard/system76/addw1/variants/addw2/overridetree.cb M src/mainboard/system76/adl/devicetree.cb M src/mainboard/system76/adl/variants/darp8/overridetree.cb M src/mainboard/system76/adl/variants/galp6/overridetree.cb M src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb M src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb M src/mainboard/system76/adl/variants/lemp11/overridetree.cb M src/mainboard/system76/adl/variants/oryp10/overridetree.cb M src/mainboard/system76/adl/variants/oryp9/overridetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/cml-u/variants/darp6/overridetree.cb M src/mainboard/system76/cml-u/variants/galp4/overridetree.cb M src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb M src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb M src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb M src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb M src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb M src/mainboard/system76/rpl/devicetree.cb M src/mainboard/system76/rpl/variants/addw3/overridetree.cb M src/mainboard/system76/rpl/variants/bonw15/overridetree.cb M src/mainboard/system76/rpl/variants/darp9/overridetree.cb M src/mainboard/system76/rpl/variants/galp7/overridetree.cb M src/mainboard/system76/rpl/variants/gaze18/overridetree.cb M src/mainboard/system76/rpl/variants/lemp12/overridetree.cb M src/mainboard/system76/rpl/variants/oryp11/overridetree.cb M src/mainboard/system76/rpl/variants/serw13/overridetree.cb M src/mainboard/system76/tgl-h/devicetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb M src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb M src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb M src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/mainboard/system76/whl-u/variants/darp5/overridetree.cb M src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb 47 files changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/82700/1 diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 529767c..16827ddb 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/addw1/variants/addw1/overridetree.cb b/src/mainboard/system76/addw1/variants/addw1/overridetree.cb index fa327fd..b1fab29 100644 --- a/src/mainboard/system76/addw1/variants/addw1/overridetree.cb +++ b/src/mainboard/system76/addw1/variants/addw1/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/addw1/variants/addw2/overridetree.cb b/src/mainboard/system76/addw1/variants/addw2/overridetree.cb index 40e2128..3b9c562 100644 --- a/src/mainboard/system76/addw1/variants/addw2/overridetree.cb +++ b/src/mainboard/system76/addw1/variants/addw2/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb index 9a78415..9a7a149 100644 --- a/src/mainboard/system76/adl/devicetree.cb +++ b/src/mainboard/system76/adl/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/adl/variants/darp8/overridetree.cb b/src/mainboard/system76/adl/variants/darp8/overridetree.cb index 73d016f..7a7e14e 100644 --- a/src/mainboard/system76/adl/variants/darp8/overridetree.cb +++ b/src/mainboard/system76/adl/variants/darp8/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 20, diff --git a/src/mainboard/system76/adl/variants/galp6/overridetree.cb b/src/mainboard/system76/adl/variants/galp6/overridetree.cb index a0a0ad2..79c614e 100644 --- a/src/mainboard/system76/adl/variants/galp6/overridetree.cb +++ b/src/mainboard/system76/adl/variants/galp6/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 28, diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb index 960ead6..603879b 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb +++ b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # FIVR configuration # Read EXT_RAIL_CONFIG to determine bitmaps diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb index 74b87ee..a9c614e4 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # FIVR configuration # Read EXT_RAIL_CONFIG to determine bitmaps diff --git a/src/mainboard/system76/adl/variants/lemp11/overridetree.cb b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb index 1e65248..10c6bfcf 100644 --- a/src/mainboard/system76/adl/variants/lemp11/overridetree.cb +++ b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ .tdp_pl1_override = 15, diff --git a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb index efebe7a..09f07b6 100644 --- a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb +++ b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ .tdp_pl1_override = 45, diff --git a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb index 2f79c9e..4ca81ab 100644 --- a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb +++ b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ .tdp_pl1_override = 45, diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index d79aa76..aa7d1ab 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index 90c5b71..07c56b4 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ /* Touchpad */ diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb index b349762..17b1ba1 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1404 inherit diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb index bbfc2ea..9c747cf 100644 --- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1403 inherit diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb index 164774a..2279cb3 100644 --- a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1401 inherit diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 4ae412d..f80c45c 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb b/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb index 0cfd040..e94d703 100644 --- a/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb +++ b/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb b/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb index 9f64b5f..02275df 100644 --- a/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb +++ b/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 3b84d7f..da3327a 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb b/src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb index 9e042a3..8fb495b 100644 --- a/src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb +++ b/src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/skylake device domain 0 on subsystemid 0x1558 0x1303 inherit diff --git a/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb b/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb index 134fbec..5cc90b26 100644 --- a/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb +++ b/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/skylake device domain 0 on subsystemid 0x1558 0x1413 inherit diff --git a/src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb b/src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb index 8a61f28..d18dfa4 100644 --- a/src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb +++ b/src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/skylake device domain 0 on subsystemid 0x1558 0x1313 inherit diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index f17862f..ae52165 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index c0c1b4a..abf68b9 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb b/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb index 3d6355e..3b2748f 100644 --- a/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb +++ b/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x50d3 inherit diff --git a/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb b/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb index 3be1b15..b9bb816 100644 --- a/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb +++ b/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x65e5 inherit diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index 4fd50fd..749ce53 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/rpl/variants/addw3/overridetree.cb b/src/mainboard/system76/rpl/variants/addw3/overridetree.cb index 9b8d453..24c272c 100644 --- a/src/mainboard/system76/rpl/variants/addw3/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/addw3/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # Support 5600 MT/s memory register "max_dram_speed_mts" = "5600" diff --git a/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb b/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb index fde40f6..a1191a5 100644 --- a/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # Support 5600 MT/s memory register "max_dram_speed_mts" = "5600" diff --git a/src/mainboard/system76/rpl/variants/darp9/overridetree.cb b/src/mainboard/system76/rpl/variants/darp9/overridetree.cb index fc9b49a..3dc2786 100644 --- a/src/mainboard/system76/rpl/variants/darp9/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/darp9/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{ .tdp_pl1_override = 20, diff --git a/src/mainboard/system76/rpl/variants/galp7/overridetree.cb b/src/mainboard/system76/rpl/variants/galp7/overridetree.cb index 0c0aec3..cc060e4 100644 --- a/src/mainboard/system76/rpl/variants/galp7/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/galp7/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[RPL_P_682_642_482_45W_CORE]" = "{ .tdp_pl1_override = 45, diff --git a/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb b/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb index 4c11595..636d57c 100644 --- a/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake device domain 0 on subsystemid 0x1558 0x5630 inherit diff --git a/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb index 34950cc..c84628b 100644 --- a/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ .tdp_pl1_override = 15, diff --git a/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb index d337a57..57bc594 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake device domain 0 on subsystemid 0x1558 0x66a2 inherit diff --git a/src/mainboard/system76/rpl/variants/serw13/overridetree.cb b/src/mainboard/system76/rpl/variants/serw13/overridetree.cb index b261d59..cc89764 100644 --- a/src/mainboard/system76/rpl/variants/serw13/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/serw13/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # Support 5600 MT/s memory register "max_dram_speed_mts" = "5600" diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb index 353a96d..11b85ce 100644 --- a/src/mainboard/system76/tgl-h/devicetree.cb +++ b/src/mainboard/system76/tgl-h/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb index ad90eab..6ac474d 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake device domain 0 on subsystemid 0x1558 0x5015 inherit diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb index bfbc5c5..b4b62fa 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake device domain 0 on subsystemid 0x1558 0x50e1 inherit diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb index a09cf30..0967154 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{ diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index f056da7..ae80a32 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb index a35dc52..b263c5a 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb index 075a2e4..7cfc62b 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb index ce45079..a4e3052 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 0899f62..6607f45 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Lock Down register "common_soc_config" = "{ diff --git a/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb b/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb index b9c9de7..c72111a 100644 --- a/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb +++ b/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1325 inherit diff --git a/src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb b/src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb index 022be95..4556940 100644 --- a/src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb +++ b/src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1323 inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/82700?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I55f2730f7277a3c699b86ded5864e9690d92d518 Gerrit-Change-Number: 82700 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com>

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[L] Change in coreboot[main]: mb/system76/mtl: Add Darter Pro 10
by Tim Crawford (Code Review) 30 May '24

30 May '24

Attention is currently required from: Felix Singer, Jeremy Soller. Tim Crawford has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/82609?usp=email ) Change subject: mb/system76/mtl: Add Darter Pro 10 ...................................................................... Patch Set 3: (2 comments) File src/mainboard/system76/mtl/devicetree.cb: PS2: > Add missing SPDX license ideentifier. Done File src/mainboard/system76/mtl/variants/darp10/overridetree.cb: PS2: > Add missing SPDX license identifier. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaef03a47cf108591ef823bfa779777c7c05c6337 Gerrit-Change-Number: 82609 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Wed, 29 May 2024 22:27:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

1 0

[L] Change in coreboot[main]: mb/system76/mtl: Add Darter Pro 10
by Tim Crawford (Code Review) 30 May '24

30 May '24

Attention is currently required from: Jeremy Soller, Tim Crawford. Hello Felix Singer, Jeremy Soller, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82609?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/system76/mtl: Add Darter Pro 10 ...................................................................... mb/system76/mtl: Add Darter Pro 10 The Darter Pro 10 (darp10) is an Intel Meteor Lake-H based board. There are 2 variants in order to differentiate the 14" and 16" models, as they have different keyboards and so have different EC firmware. Change-Id: Iaef03a47cf108591ef823bfa779777c7c05c6337 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- A src/mainboard/system76/mtl/Kconfig A src/mainboard/system76/mtl/Kconfig.name A src/mainboard/system76/mtl/Makefile.mk A src/mainboard/system76/mtl/acpi/backlight.asl A src/mainboard/system76/mtl/acpi/mainboard.asl A src/mainboard/system76/mtl/acpi/sleep.asl A src/mainboard/system76/mtl/board_info.txt A src/mainboard/system76/mtl/bootblock.c A src/mainboard/system76/mtl/cmos.default A src/mainboard/system76/mtl/cmos.layout A src/mainboard/system76/mtl/devicetree.cb A src/mainboard/system76/mtl/dsdt.asl A src/mainboard/system76/mtl/include/mainboard/gpio.h A src/mainboard/system76/mtl/ramstage.c A src/mainboard/system76/mtl/variants/darp10/board.fmd A src/mainboard/system76/mtl/variants/darp10/board_info.txt A src/mainboard/system76/mtl/variants/darp10/data.vbt A src/mainboard/system76/mtl/variants/darp10/gpio.c A src/mainboard/system76/mtl/variants/darp10/gpio_early.c A src/mainboard/system76/mtl/variants/darp10/hda_verb.c A src/mainboard/system76/mtl/variants/darp10/overridetree.cb A src/mainboard/system76/mtl/variants/darp10/ramstage.c A src/mainboard/system76/mtl/variants/darp10/romstage.c 23 files changed, 791 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/82609/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/82609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaef03a47cf108591ef823bfa779777c7c05c6337 Gerrit-Change-Number: 82609 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com>

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[L] Change in coreboot[main]: mb/system76/mtl: Add Darter Pro 10
by Felix Singer (Code Review) 30 May '24

30 May '24

Attention is currently required from: Jeremy Soller, Tim Crawford. Felix Singer has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/82609?usp=email ) Change subject: mb/system76/mtl: Add Darter Pro 10 ...................................................................... Patch Set 2: (2 comments) File src/mainboard/system76/mtl/devicetree.cb: PS2: Add missing SPDX license ideentifier. File src/mainboard/system76/mtl/variants/darp10/overridetree.cb: PS2: Add missing SPDX license identifier. -- To view, visit https://review.coreboot.org/c/coreboot/+/82609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaef03a47cf108591ef823bfa779777c7c05c6337 Gerrit-Change-Number: 82609 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Wed, 29 May 2024 22:11:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[L] Change in coreboot[main]: mb/system76/rpl: Add Adder WS 4 as a variant
by Felix Singer (Code Review) 29 May '24

29 May '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82595?usp=email ) Change subject: mb/system76/rpl: Add Adder WS 4 as a variant ...................................................................... mb/system76/rpl: Add Adder WS 4 as a variant The Adder WS 4 (addw4) is a Raptor Lake-HX board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots (with Crucial CT8G48C40S5) - M.2 NVMe SSDs - All USB ports - MicroSD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Linux 6.8 - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.8.0 - TPM 2.0 device Not working: - Discrete/Hybrid graphics - Detection of devices in TBT slot on boot Change-Id: I4a6819cbcf64f68237008adebdd7eb196336514c Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82595 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/system76/rpl/Kconfig M src/mainboard/system76/rpl/Kconfig.name M src/mainboard/system76/rpl/devicetree.cb A src/mainboard/system76/rpl/variants/addw4/board.fmd A src/mainboard/system76/rpl/variants/addw4/board_info.txt A src/mainboard/system76/rpl/variants/addw4/data.vbt A src/mainboard/system76/rpl/variants/addw4/gpio.c A src/mainboard/system76/rpl/variants/addw4/gpio_early.c A src/mainboard/system76/rpl/variants/addw4/hda_verb.c A src/mainboard/system76/rpl/variants/addw4/overridetree.cb A src/mainboard/system76/rpl/variants/addw4/romstage.c 11 files changed, 525 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig index 1d32b49..20a09b6 100644 --- a/src/mainboard/system76/rpl/Kconfig +++ b/src/mainboard/system76/rpl/Kconfig @@ -32,6 +32,12 @@ select PCIEXP_HOTPLUG select SOC_INTEL_ALDERLAKE_PCH_S +config BOARD_SYSTEM76_ADDW4 + select BOARD_SYSTEM76_RPL_COMMON + select EC_SYSTEM76_EC_DGPU + select PCIEXP_HOTPLUG + select SOC_INTEL_ALDERLAKE_PCH_S + config BOARD_SYSTEM76_BONW15 select BOARD_SYSTEM76_RPL_COMMON select EC_SYSTEM76_EC_DGPU @@ -85,6 +91,7 @@ config VARIANT_DIR default "addw3" if BOARD_SYSTEM76_ADDW3 + default "addw4" if BOARD_SYSTEM76_ADDW4 default "bonw15" if BOARD_SYSTEM76_BONW15 default "darp9" if BOARD_SYSTEM76_DARP9 default "galp7" if BOARD_SYSTEM76_GALP7 @@ -99,6 +106,7 @@ config MAINBOARD_PART_NUMBER default "addw3" if BOARD_SYSTEM76_ADDW3 + default "addw4" if BOARD_SYSTEM76_ADDW4 default "bonw15" if BOARD_SYSTEM76_BONW15 default "darp9" if BOARD_SYSTEM76_DARP9 default "galp7" if BOARD_SYSTEM76_GALP7 @@ -109,7 +117,7 @@ default "serw13" if BOARD_SYSTEM76_SERW13 config MAINBOARD_SMBIOS_PRODUCT_NAME - default "Adder WS" if BOARD_SYSTEM76_ADDW3 + default "Adder WS" if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 default "Bonobo WS" if BOARD_SYSTEM76_BONW15 default "Darter Pro" if BOARD_SYSTEM76_DARP9 default "Galago Pro" if BOARD_SYSTEM76_GALP7 @@ -120,6 +128,7 @@ config MAINBOARD_VERSION default "addw3" if BOARD_SYSTEM76_ADDW3 + default "addw4" if BOARD_SYSTEM76_ADDW4 default "bonw15" if BOARD_SYSTEM76_BONW15 default "darp9" if BOARD_SYSTEM76_DARP9 default "galp7" if BOARD_SYSTEM76_GALP7 diff --git a/src/mainboard/system76/rpl/Kconfig.name b/src/mainboard/system76/rpl/Kconfig.name index a33e57c..57c3de7 100644 --- a/src/mainboard/system76/rpl/Kconfig.name +++ b/src/mainboard/system76/rpl/Kconfig.name @@ -3,6 +3,9 @@ config BOARD_SYSTEM76_ADDW3 bool "addw3" +config BOARD_SYSTEM76_ADDW4 + bool "addw3" + config BOARD_SYSTEM76_BONW15 bool "bonw15" diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index d389d21..4fd50fd 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -53,7 +53,7 @@ register "sata_salp_support" = "1" register "sata_ports_enable[1]" = "1" # SSD1 # FIXME: DevSlp breaks S0ix - #register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1) + #register "sata_ports_dev_slp[1]" = "1" end device ref pch_espi on register "gen1_dec" = "0x00040069" # EC PM channel diff --git a/src/mainboard/system76/rpl/variants/addw4/board.fmd b/src/mainboard/system76/rpl/variants/addw4/board.fmd new file mode 100644 index 0000000..b2615d1 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/board.fmd @@ -0,0 +1,12 @@ +FLASH 32M { + SI_DESC 4K + SI_ME 3944K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/rpl/variants/addw4/board_info.txt b/src/mainboard/system76/rpl/variants/addw4/board_info.txt new file mode 100644 index 0000000..01f9c50 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/board_info.txt @@ -0,0 +1,2 @@ +Board name: addw4 +Release year: 2024 diff --git a/src/mainboard/system76/rpl/variants/addw4/data.vbt b/src/mainboard/system76/rpl/variants/addw4/data.vbt new file mode 100644 index 0000000..40fdfb2 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/data.vbt Binary files differ diff --git a/src/mainboard/system76/rpl/variants/addw4/gpio.c b/src/mainboard/system76/rpl/variants/addw4/gpio.c new file mode 100644 index 0000000..471212b --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/gpio.c @@ -0,0 +1,294 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_NC(GPD2, NONE), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_NC(GPD6, NONE), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + PAD_NC(GPD12, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_NC(GPP_A9, NONE), + PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // ESPI_ALRT0# + PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // GPIO4_GC6_NVVDD_EN_R + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), + PAD_NC(GPP_A14, NONE), + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_NC(GPP_B1, NONE), + PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CNVI_WAKE# + PAD_CFG_GPO(GPP_B3, 1, PLTRST), // BT_EN + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B11, NONE), + PAD_NC(GPP_B12, NONE), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1), // GPP_B18_PMCALERT# + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO(GPP_B20, 0, DEEP), // GPIO_LANRTD3 + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_GPI(GPP_B23, NONE, DEEP), // Crystal freq strap + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPI(GPP_C2, NONE, DEEP), // TLS confidentiality strap + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // I2C2_SDA (Pantone) + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // I2C2_SCL (Pantone) + PAD_NC(GPP_C5, NONE), // eSPI disable strap + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2), // SMD_7411 + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2), // SMC_7411 + PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET + PAD_NC(GPP_C9, NONE), + PAD_CFG_GPO(GPP_C10, 0, DEEP), // TEST_R (ANX7411) + PAD_CFG_GPO(GPP_C11, 0, DEEP), // PCH_TEST_R_2 (ANX7411) + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // SMD_7411_2 + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // SMC_7411_2 + // GPP_C20 (UART2_RXD) configured in bootblock + // GPP_C21 (UART2_TXD) configured in bootblock + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_CFG_GPO(GPP_D3, 0, DEEP), // GFX_DETECT_STRAP + PAD_NC(GPP_D4, NONE), + PAD_CFG_GPO(GPP_D5, 1, DEEP), // M.2_BT_PCMFRM_CRF_RST_N + // GPP_D6 (M.2_BT_PCMOUT_CLKREQ0) configured by FSP + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + // GPP_D12 (SSD2_CLKREQ#) configured by FSP + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SWI# + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED# + PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0# + PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1# + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2# + PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3# + PAD_NC(GPP_E13, NONE), + PAD_NC(GPP_E14, NONE), + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // SB_KBCRST# + PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON + PAD_NC(GPP_E19, NONE), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // M.2_SSD_SATA_DET_N + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // SSD_SATA_DEVSLP + PAD_NC(GPP_F6, NONE), + _PAD_CFG_STRUCT(GPP_F7, 0x80100100, 0x0000), // 7411_INTP_OUT + PAD_NC(GPP_F8, NONE), + // GPP_F9 (DGPU_PWR_EN) configured in bootblock + PAD_CFG_GPI(GPP_F10, NONE, DEEP), // Recovery strap + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N + _PAD_CFG_STRUCT(GPP_F16, 0x80100100, 0x0000), // INTP_OUT + PAD_NC(GPP_F17, NONE), + PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP# + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPO(GPP_G0, 0, DEEP), // Board ID 2 + PAD_CFG_GPO(GPP_G1, 0, DEEP), // Board ID 3 + PAD_NC(GPP_G2, NONE), + PAD_CFG_GPI(GPP_G3, NONE, DEEP), // MB detect GN20/GN21 + PAD_CFG_GPI(GPP_G4, NONE, DEEP), // Board ID 1 + PAD_NC(GPP_G5, NONE), + PAD_CFG_GPI(GPP_G6, NONE, DEEP), // MB detect G-SYNC + PAD_CFG_GPI(GPP_G7, NONE, DEEP), // MB detect 230W/180W adapter + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPI(GPP_H0, NONE, DEEP), // VAL_SV_ADVANCE_STRAP + PAD_CFG_GPO(GPP_H1, 0, DEEP), // Pantone detect + PAD_CFG_GPI(GPP_H2, NONE, DEEP), // WLAN_GPIO_WAKE_N + // GPP_H3 (NC) configured by FSP + // GPP_H4 (SSD1_SATA_CLKREQ#) configured by FSP + // GPP_H5 (WLAN_CLKREQ#) configured by FSP + // GPP_H6 (NC) configured by FSP + // GPP_H7 (LAN_CLKREQ#) configured by FSP + // GPP_H8 (PEG_CLKREQ#) configured by FSP + // GPP_H9 (SSD3_CLKREQ#) configured by FSP + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_CFG_GPO(GPP_H15, 0, DEEP), // JTAG ODT strap + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_CFG_GPO(GPP_H18, 0, DEEP), // 1.8V VCCPSPI strap + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // DP_HPD + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // HDMI_HPD + PAD_NC(GPP_I3, NONE), + PAD_NC(GPP_I4, NONE), + PAD_NC(GPP_I5, NONE), + PAD_NC(GPP_I6, NONE), + PAD_NC(GPP_I7, NONE), + PAD_NC(GPP_I8, NONE), + PAD_NC(GPP_I9, NONE), + PAD_NC(GPP_I10, NONE), + PAD_CFG_GPI(GPP_I11, NONE, DEEP), // USB_OC4# + PAD_CFG_GPI(GPP_I12, NONE, DEEP), // USB_OC5# + PAD_CFG_GPI(GPP_I13, NONE, DEEP), // USB_OC6# + PAD_CFG_GPI(GPP_I14, NONE, DEEP), // USB_OC7# + PAD_NC(GPP_I15, NONE), + PAD_NC(GPP_I16, NONE), + PAD_NC(GPP_I17, NONE), + PAD_CFG_GPO(GPP_I18, 0, DEEP), // No reboot strap + PAD_NC(GPP_I19, NONE), + PAD_NC(GPP_I20, NONE), + PAD_NC(GPP_I21, NONE), + PAD_CFG_GPO(GPP_I22, 0, DEEP), // Boot BIOS strap + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT_R / Xtal freq strap + PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT_R / M.2 CNV modes strap + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD + PAD_CFG_GPI(GPP_J8, NONE, DEEP), // VAL_TEST_SETUP_MENU + PAD_NC(GPP_J9, NONE), + PAD_NC(GPP_J10, NONE), + PAD_NC(GPP_J11, NONE), + + /* ------- GPIO Group GPP_K ------- */ + PAD_NC(GPP_K0, NONE), + PAD_NC(GPP_K1, NONE), + PAD_NC(GPP_K2, NONE), + PAD_NC(GPP_K3, NONE), + PAD_NC(GPP_K4, NONE), + PAD_NC(GPP_K5, NONE), + // GPP_K6 not in schematics + // GPP_K7 not in schematics + PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + // GPP_K10 not in schematics + PAD_NC(GPP_K11, NONE), + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#_R + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), + PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD + PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_R10, NONE), + PAD_NC(GPP_R11, NONE), + PAD_NC(GPP_R12, NONE), + PAD_NC(GPP_R13, NONE), + PAD_NC(GPP_R14, NONE), + PAD_NC(GPP_R15, NONE), + // GPP_R16 (DGPU_RST#_PCH) configured in bootblock + PAD_NC(GPP_R17, NONE), + PAD_NC(GPP_R18, NONE), + PAD_CFG_GPI(GPP_R19, NONE, DEEP), // SCI# + PAD_NC(GPP_R20, NONE), + PAD_NC(GPP_R21, NONE), + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/addw4/gpio_early.c b/src/mainboard/system76/rpl/variants/addw4/gpio_early.c new file mode 100644 index 0000000..b6914ad --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/addw4/hda_verb.c b/src/mainboard/system76/rpl/variants/addw4/hda_verb.c new file mode 100644 index 0000000..3850d34 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/hda_verb.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x15580353, /* Subsystem ID */ + 35, /* Number of entries */ + + 0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb, + + AZALIA_SUBVENDOR(0, 0x15580353), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40689b2d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + + 0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b, + 0x0205004a, 0x02042010, 0x02050038, 0x02047909, + 0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82, + 0x05350000, 0x0534201a, 0x05350000, 0x0534201a, + 0x0535001d, 0x05340800, 0x0535001e, 0x05340800, + 0x05350003, 0x05341ec4, 0x05350004, 0x05340000, + 0x05450000, 0x05442000, 0x0545001d, 0x05440800, + 0x0545001e, 0x05440800, 0x05450003, 0x05441ec4, + 0x05450004, 0x05440000, 0x05350000, 0x0534a01a, + 0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135, + 0x02050040, 0x02048800, 0x05a50001, 0x05a4001f, + 0x02050010, 0x02040020, 0x02050010, 0x02040020, + 0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390, + 0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00, + 0x00170500, 0x00170500, 0x05a50004, 0x05a40113, + 0x02050008, 0x02046a8c, 0x02050076, 0x0204f000, + 0x0205000e, 0x020465c0, 0x02050033, 0x02048580, + 0x02050069, 0x0204fda8, 0x02050068, 0x02040000, + 0x02050003, 0x02040002, 0x02050069, 0x02040000, + 0x02050068, 0x02040001, 0x0205002e, 0x0204290e, + 0x02050010, 0x02040020, 0x02050010, 0x02040020, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/addw4/overridetree.cb b/src/mainboard/system76/rpl/variants/addw4/overridetree.cb new file mode 100644 index 0000000..c29aea9 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/overridetree.cb @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/alderlake + # Support 5600 MT/s memory + register "max_dram_speed_mts" = "5600" + + device domain 0 on + subsystemid 0x1558 0x0353 inherit + + device ref xhci on + register "usb2_ports" = "{ + /* Port reset messaging cannot be used, + * so do not use USB2_PORT_TYPE_C for these */ + [0] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC1 */ + [1] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC2 */ + [2] = USB2_PORT_MID(OC_SKIP), /* J_USB2 */ + [3] = USB2_PORT_MID(OC_SKIP), /* J_USB1 (Audio board) */ + [6] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */ + [7] = USB2_PORT_MID(OC_SKIP), /* Camera */ + [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB2 */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB1 (Audio board) */ + }" + end + + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + + device ref pcie5_0 on + # DGPU + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 14, + .clk_req = 14, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + + device ref pcie_rp3 on + # GLAN + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .clk_src = 13, + .clk_req = 13, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + device pci 00.0 on end # Realtek RTL8111H + end + device ref pcie_rp8 on + # WLAN + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 11, + .clk_req = 11, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp13 on + # J_SSD1 + register "pch_pcie_rp[PCH_RP(13)]" = "{ + .clk_src = 10, + .clk_req = 10, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp21 on + # J_SSD2 + register "pch_pcie_rp[PCH_RP(21)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp25 on + # J_SSD3 + register "pch_pcie_rp[PCH_RP(25)]" = "{ + .clk_src = 15, + .clk_req = 15, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + end +end diff --git a/src/mainboard/system76/rpl/variants/addw4/romstage.c b/src/mainboard/system76/rpl/variants/addw4/romstage.c new file mode 100644 index 0000000..fe91032 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/romstage.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + .LpDdrDqDqsReTraining = 1, + .ddr_config = { + .dq_pins_interleaved = true, + }, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + // Set primary display to hybrid graphics + mupd->FspmConfig.PrimaryDisplay = 4; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/82595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a6819cbcf64f68237008adebdd7eb196336514c Gerrit-Change-Number: 82595 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/dell: Add Latitude E6530 (Ivy Bridge)
by Nicholas Chin (Code Review) 29 May '24

29 May '24

Attention is currently required from: Felix Singer, Paul Menzel. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/79012?usp=email ) Change subject: mb/dell: Add Latitude E6530 (Ivy Bridge) ...................................................................... Patch Set 6: (1 comment) File src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c: https://review.coreboot.org/c/coreboot/+/79012/comment/43806ecf_f6b5bbf3?us… : PS3, Line 28: > nit: remove blank line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71 Gerrit-Change-Number: 79012 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 29 May 2024 21:10:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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