coreboot-gerrit May 2024

coreboot-gerrit@coreboot.org

1 participants
3266 discussions

[XS] Change in coreboot[main]: src/mainboard/google/rex: Enable Rex64 build configuration
by Paul Menzel (Code Review) 30 May '24

30 May '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Subrata Banik, Tarun. Paul Menzel has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/82625?usp=email ) Change subject: src/mainboard/google/rex: Enable Rex64 build configuration ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82625/comment/728a0bc9_ec716432?us… : PS2, Line 7: src/ Please remove. -- To view, visit https://review.coreboot.org/c/coreboot/+/82625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Gerrit-Change-Number: 82625 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 30 May 2024 21:19:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 builds
by Subrata Banik (Code Review) 30 May '24

30 May '24

Attention is currently required from: Appukuttan V K. Subrata Banik has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82699?usp=email ) Change subject: soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 builds ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82699?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icdbf3bacc0a05975fc941b264fd400d74f506fce Gerrit-Change-Number: 82699 Gerrit-PatchSet: 3 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Comment-Date: Thu, 30 May 2024 20:08:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard
by Subrata Banik (Code Review) 30 May '24

30 May '24

Attention is currently required from: Appukuttan V K, Ronak Kanabar. Subrata Banik has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82425?usp=email ) Change subject: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard ...................................................................... Patch Set 26: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Gerrit-Change-Number: 82425 Gerrit-PatchSet: 26 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 30 May 2024 20:08:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: mb/google/brox: Fix CPU crashlog device MMIO memory access
by Subrata Banik (Code Review) 30 May '24

30 May '24

Attention is currently required from: Angel Pons, Benjamin Doron, Dinesh Gehlot, Kane Chen, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel, Sowmya Aralguppe. Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/82136?usp=email ) Change subject: mb/google/brox: Fix CPU crashlog device MMIO memory access ...................................................................... Patch Set 10: (4 comments) File src/soc/intel/alderlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/82136/comment/1b98d7da_01dfb0a7?us… : PS10, Line 205: & > Good point. The code says "if `dw1` and `dw0` don't have any one-bits in common", which is rather odd. > > As per the surrounding code, looks like this is a 64-bit register (a memory address?), and a zero address would be invalid. If this is correct, then the check should be: > > ```suggestion > if (!dw1 && !dw0) { > ``` > > This would be equivalent, but I feel it's harder to understand so I prefer the former: > ``` > if (!(dw1 | dw0)) { > ``` If the idea is to check the zero based value, then please be explicit and don't use bit wise operator. ``` if (!dw1 && !dw0) { ``` https://review.coreboot.org/c/coreboot/+/82136/comment/825b6d82_01ccc0c1?us… : PS10, Line 245: CPU_TRACE_HUB_BASE_ADDRESS wondering why we are using temp base address here ? and how do we know if this temp access is not being assigned to any other resource ? https://review.coreboot.org/c/coreboot/+/82136/comment/a0ee3559_90c416b6?us… : PS10, Line 246: printk(BIOS_DEBUG, "cpu_bar_addr for Crashlog device : 0x%X\n", cpu_bar_addr); this is hardcoded value so why should we print the additional debug msg here ? https://review.coreboot.org/c/coreboot/+/82136/comment/3f554cee_7f447cd5?us… : PS10, Line 248: if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) { : pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, cpu_bar_addr); : } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) { : pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, cpu_bar_addr); : } else { : printk(BIOS_DEBUG, "invalid discovery data t_bir_q: 0x%x\n", : cpu_cl_devsc_cap.discovery_data.fields.t_bir_q); : return false; : } WDYT ? ``` uint8_t t_bir_q = cpu_cl_devsc_cap.discovery_data.fields.t_bir_q; const uint8_t BAR_OFFSET = PCI_BASE_ADDRESS_0; if (t_bir_q >= TEL_DVSEC_TBIR_BAR0 && t_bir_q <= TEL_DVSEC_TBIR_BAR1) { uint8_t bar_index = t_bir_q - TEL_DVSEC_TBIR_BAR0; pci_write_config32(SA_DEV_TMT, BAR_OFFSET + bar_index, cpu_bar_addr); } else { printk(BIOS_DEBUG, "Invalid TEL_DVSEC_TBIR_BARx: %d\n", t_bir_q); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/82136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I262254ee8d0eb91efcb3e748d121e13c31e66251 Gerrit-Change-Number: 82136 Gerrit-PatchSet: 10 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 30 May 2024 19:59:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

1 0

[XS] Change in coreboot[main]: drivers/soundwire/alc711: Update ALC711 codec address fields
by Angel Pons (Code Review) 30 May '24

30 May '24

Attention is currently required from: Anil Kumar K, Hannah Williams, Kapil Porwal, Paul Menzel, Sathyanarayana Nujella, Subrata Banik, Wonkyu Kim. Angel Pons has posted comments on this change by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/81952?usp=email ) Change subject: drivers/soundwire/alc711: Update ALC711 codec address fields ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Patchset: PS5: > @th3fanbus@gmail.com @paulepanter@mailbox. […] I don't have the codec's datasheet, someone else should approve this -- To view, visit https://review.coreboot.org/c/coreboot/+/81952?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ece9976ab174659ebd0ae95330ca3deb0481f2a Gerrit-Change-Number: 81952 Gerrit-PatchSet: 5 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 30 May 2024 19:58:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com>

1 0

[XS] Change in coreboot[main]: soc/intel/meteorlake: Enable eSOL without 64-bit support
by Subrata Banik (Code Review) 30 May '24

30 May '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82716?usp=email ) Change subject: soc/intel/meteorlake: Enable eSOL without 64-bit support ...................................................................... soc/intel/meteorlake: Enable eSOL without 64-bit support This change allows eSOL to be enabled on production Meteor Lake silicon even when 64-bit support is not present. eSOL support is still TBD for 64-bit FSP hence, skip adding this support for 64-bit build. TEST=Able to build and boot google/rex64 w/o eSOL. Change-Id: I16762e5b74ae0aaa3c28730479a1fd9defc4d93c Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/82716/1 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 2721e0b..566e88c 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -458,7 +458,7 @@ config SOC_INTEL_METEORLAKE_SIGN_OF_LIFE bool - default y if !SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON + default y if !SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON || !HAVE_X86_64_SUPPORT depends on MAINBOARD_HAS_CHROMEOS select VBT_CBFS_COMPRESSION_DEFAULT_LZ4 help -- To view, visit https://review.coreboot.org/c/coreboot/+/82716?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I16762e5b74ae0aaa3c28730479a1fd9defc4d93c Gerrit-Change-Number: 82716 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

1 0

[M] Change in coreboot[main]: acpi/acpi.c: fix XSDT handling on QEMU
by Tim Wawrzynczak (Code Review) 30 May '24

30 May '24

Attention is currently required from: Arthur Heymans, Cliff Huang, Krystian Hebel, Lance Zhao. Tim Wawrzynczak has posted comments on this change by Krystian Hebel. ( https://review.coreboot.org/c/coreboot/+/82698?usp=email ) Change subject: acpi/acpi.c: fix XSDT handling on QEMU ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82698?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7f38467b7de3f35fc3ec3854a840de8345cd0fe5 Gerrit-Change-Number: 82698 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Thu, 30 May 2024 19:36:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: mb/google/brox: Fix CPU crashlog device MMIO memory access
by Angel Pons (Code Review) 30 May '24

30 May '24

Attention is currently required from: Benjamin Doron, Dinesh Gehlot, Kane Chen, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel, Sowmya Aralguppe, Subrata Banik. Angel Pons has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/82136?usp=email ) Change subject: mb/google/brox: Fix CPU crashlog device MMIO memory access ...................................................................... Patch Set 10: -Code-Review (1 comment) File src/soc/intel/alderlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/82136/comment/2d11a895_2d4f6b5d?us… : PS10, Line 205: & > Why bitwise `&`? Did you mean to use logical `&&` operator? Good point. The code says "if `dw1` and `dw0` don't have any one-bits in common", which is rather odd. As per the surrounding code, looks like this is a 64-bit register (a memory address?), and a zero address would be invalid. If this is correct, then the check should be: ```suggestion if (!dw1 && !dw0) { ``` This would be equivalent, but I feel it's harder to understand so I prefer the former: ``` if (!(dw1 | dw0)) { ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/82136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I262254ee8d0eb91efcb3e748d121e13c31e66251 Gerrit-Change-Number: 82136 Gerrit-PatchSet: 10 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 30 May 2024 18:46:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

1 0

[S] Change in coreboot[main]: util/cbfstool: Disable paging for linux payload
by Angel Pons (Code Review) 30 May '24

30 May '24

Attention is currently required from: Arthur Heymans, Lean Sheng Tan, Patrick Rudolph, Shuo Liu. Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82705?usp=email ) Change subject: util/cbfstool: Disable paging for linux payload ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Since coreboot doesn't set up paging, it must not disable paging. […] So, as I understand it, is the issue that FSP doesn't properly restore the execution environment? If so, it sounds like a bug in FSP, so having to work around it in coreboot feels utterly wrong. -- To view, visit https://review.coreboot.org/c/coreboot/+/82705?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50a4ab2664910e5772b90b3dade8866f28361d87 Gerrit-Change-Number: 82705 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 30 May 2024 18:40:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

[XS] Change in coreboot[main]: util/cbfstool: Fix linux_trampoline.c generation
by Angel Pons (Code Review) 30 May '24

30 May '24

Attention is currently required from: Arthur Heymans, Lean Sheng Tan, Patrick Rudolph, Shuo Liu. Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82704?usp=email ) Change subject: util/cbfstool: Fix linux_trampoline.c generation ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Would be nice to have this build-tested -- To view, visit https://review.coreboot.org/c/coreboot/+/82704?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7faca296f946bb4e9fd510661357925e5dcf9a6b Gerrit-Change-Number: 82704 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 30 May 2024 18:37:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2024