coreboot-gerrit May 2024

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[L] Change in coreboot[main]: mb/google/trulo/var/orisa: Add overridetree
by Amanda Hwang (Code Review) 30 May '24

30 May '24

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82714?usp=email ) Change subject: mb/google/trulo/var/orisa: Add overridetree ...................................................................... mb/google/trulo/var/orisa: Add overridetree Add override devicetree based on schematics BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id3ceff41fdb8e4a57bd6dab6247b622a5d13587d Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/orisa/overridetree.cb 2 files changed, 522 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/82714/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 366d2dd..9f6a026 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -687,7 +687,8 @@ config TPM_TIS_ACPI_INTERRUPT int - default 13 if !BOARD_GOOGLE_BASEBOARD_HADES # GPE0_DW0_13 (GPP_A13_IRQ) + default 13 if !BOARD_GOOGLE_BASEBOARD_HADES && !BOARD_GOOGLE_ORISA # GPE0_DW0_13 (GPP_A13_IRQ) + default 17 if BOARD_GOOGLE_ORISA # GPE0_DW0_17 (GPP_A17_IRQ) default 20 if BOARD_GOOGLE_BASEBOARD_HADES # GPE0_DW0_20 (GPP_A20_IRQ) config OVERRIDE_DEVICETREE diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index 4f2c04a..0d20a3a 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -1,6 +1,524 @@ +fw_config + field THERMAL_SOLUTION 0 0 + option THERMAL_SOLUTION_6W 0 + option THERMAL_SOLUTION_15W 1 + end +end + chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" - device domain 0 on - end + # GPE configuration + register "pmc_gpe0_dw1" = "GPP_B" + # S0ix enable + register "s0ix_enable" = "1" + + # DPTF enable + register "dptf_enable" = "1" + + register "tcc_offset" = "10" # TCC of 90 + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + # eMMC HS400 + register "emmc_enable_hs400_mode" = "1" + + #eMMC DLL tuning parameters + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7 + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC. + # Bit 2 - C1 has a redriver which does SBU muxing. + # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. + register "tcss_aux_ori" = "0" + + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # FIXME: To be enabled in future based on PNP impact data. + # Disable Package C-state demotion for nissa baseboard. + register "disable_package_c_state_demotion" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Trackpad | + #| I2C5 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + register "power_limits_config[ADL_N_041_6W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + + register "power_limits_config[ADL_N_081_15W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 35, + .tdp_pl4 = 83, + }" + + device domain 0 on + device ref igpu on end + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR"" + register "options.tsr[1].desc" = ""charger"" + register "options.tsr[2].desc" = ""ambient"" + + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(70, 100), + TEMP_PCT(60, 65), + TEMP_PCT(42, 60), + TEMP_PCT(39, 55), + TEMP_PCT(38, 50), + TEMP_PCT(35, 43), + TEMP_PCT(31, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(60, 100), + TEMP_PCT(55, 65), + TEMP_PCT(52, 60), + TEMP_PCT(50, 55), + TEMP_PCT(48, 50), + TEMP_PCT(45, 43), + TEMP_PCT(41, 30), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 6000, + .max_power = 20000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 500 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 32 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 500 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on + probe THERMAL_SOLUTION THERMAL_SOLUTION_6W + end + end + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR"" + register "options.tsr[1].desc" = ""charger"" + register "options.tsr[2].desc" = ""ambient"" + + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(70, 100), + TEMP_PCT(60, 65), + TEMP_PCT(42, 58), + TEMP_PCT(39, 53), + TEMP_PCT(38, 47), + TEMP_PCT(35, 43), + TEMP_PCT(31, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(60, 100), + TEMP_PCT(55, 65), + TEMP_PCT(52, 58), + TEMP_PCT(50, 53), + TEMP_PCT(48, 47), + TEMP_PCT(45, 43), + TEMP_PCT(41, 30), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 20000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 500 + }, + .pl2 = { + .min_power = 35000, + .max_power = 35000, + .time_window_min = 32 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 500 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 1 on + probe THERMAL_SOLUTION THERMAL_SOLUTION_15W + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + end + end + end + device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A17_IRQ)" + device i2c 50 on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW1_03" + register "detect" = "1" + device i2c 15 on end + end + end #I2C1 + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)" + register "generic.enable_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)" + register "generic.stop_delay_ms" = "150" + register "generic.stop_off_delay_ms" = "2" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end #I2C5 + device ref heci1 on end + device ref pcie_rp7 off end + device ref emmc on end + device ref uart0 on end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/82714?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id3ceff41fdb8e4a57bd6dab6247b622a5d13587d Gerrit-Change-Number: 82714 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com>

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[XS] Change in coreboot[main]: drivers/soundwire/alc711: Update ALC711 codec address fields
by Anil Kumar K (Code Review) 30 May '24

30 May '24

Attention is currently required from: Hannah Williams, Kapil Porwal, Paul Menzel, Sathyanarayana Nujella, Subrata Banik, Wonkyu Kim. Anil Kumar K has posted comments on this change by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/81952?usp=email ) Change subject: drivers/soundwire/alc711: Update ALC711 codec address fields ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: @th3fanbus@gmail.com @paulepanter@mailbox.org Can we merge this patch if it looks good ? -- To view, visit https://review.coreboot.org/c/coreboot/+/81952?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ece9976ab174659ebd0ae95330ca3deb0481f2a Gerrit-Change-Number: 81952 Gerrit-PatchSet: 5 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 30 May 2024 18:18:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/qemu-{i440fx,q35}: reduce default ROM size to 8M
by Sergii Dmytruk (Code Review) 30 May '24

30 May '24

Attention is currently required from: Krystian Hebel, Maciej Pijanowski, Michał Kopeć, Michał Żygowski, Patrick Rudolph. Sergii Dmytruk has posted comments on this change by Krystian Hebel. ( https://review.coreboot.org/c/coreboot/+/82639?usp=email ) Change subject: mb/qemu-{i440fx,q35}: reduce default ROM size to 8M ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82639/comment/10d31365_ef3559aa?us… : PS1, Line 9: QEMU doesn't allow to use bigger images with '-drive if=pflash', which > No idea why, I guess this was a design decision made by QEMU. […] After facing this error recently I found a failed attempt to increase the size in https://lists.gnu.org/archive/html/qemu-devel/2020-09/msg04146.html, wanted to link to modern version of that code now and found https://gitlab.com/qemu-project/qemu/-/commit/0657c657eb37bb48bfd9fe3ae8a32…. There seems to be `max-fw-size` machine option for more than 3 years, which is present in `qemu-system-x86_64 -M q35,help` output but search at https://www.qemu.org/docs/master/index.html doesn't find it. The default is still 8 MiB though, so this change still improves usability. -- To view, visit https://review.coreboot.org/c/coreboot/+/82639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If36cb754a8e75e23bce49ff568dd88e5db279bb8 Gerrit-Change-Number: 82639 Gerrit-PatchSet: 2 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Thu, 30 May 2024 18:10:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com>

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[XS] Change in coreboot[main]: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard
by Subrata Banik (Code Review) 30 May '24

30 May '24

Attention is currently required from: Appukuttan V K, Ronak Kanabar. Subrata Banik has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82425?usp=email ) Change subject: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard ...................................................................... Patch Set 26: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82425/comment/08384011_a571bcf1?us… : PS23, Line 16: - Guard x86_32 architecture specific structures under : PLATFORM_USES_FSP2_X86_32 config. : - Guard FSP 2.4 specific structures under PLATFORM_USES_FSP2_4 : config. > I removed all the config guards including the pre existing one (Introduced in https://review.coreboot.org/c/coreboot/+/62847/2). > It builds fine in both x32 and x64. > That existing guard on FSPM_ARCH_UPD was causing the compile issue within this file itself. it sounds to me the correct move and thanks for doing so, -- To view, visit https://review.coreboot.org/c/coreboot/+/82425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Gerrit-Change-Number: 82425 Gerrit-PatchSet: 26 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 30 May 2024 17:55:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Appukuttan V K <appukuttan.vk(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard
by Appukuttan V K (Code Review) 30 May '24

30 May '24

Attention is currently required from: Ronak Kanabar, Subrata Banik. Appukuttan V K has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82425?usp=email ) Change subject: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard ...................................................................... Patch Set 26: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82425/comment/fcfa9c86_d98f8196?us… : PS23, Line 16: - Guard x86_32 architecture specific structures under : PLATFORM_USES_FSP2_X86_32 config. : - Guard FSP 2.4 specific structures under PLATFORM_USES_FSP2_4 : config. > I don't think so, we are not building both code at same time. […] I removed all the config guards including the pre existing one (Introduced in https://review.coreboot.org/c/coreboot/+/62847/2). It builds fine in both x32 and x64. That existing guard on FSPM_ARCH_UPD was causing the compile issue within this file itself. https://review.coreboot.org/c/coreboot/+/82425/comment/1a91ae2b_fd468c06?us… : PS23, Line 21: b:343428206 > please specify the child bugs if you have created any to fix the EDK2 cherrypicks as well here. No additional changes are required for this. After removing the existing x32 guard both builds fine. File src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h: https://review.coreboot.org/c/coreboot/+/82425/comment/966bc522_0cd18385?us… : PS23, Line 382: } FSPT_UPD_COMMON_FSP24; > > FSPT is not used anywhere so it is not causing any issue. Do you want to guard this anyway. […] I have removed all the guards now. -- To view, visit https://review.coreboot.org/c/coreboot/+/82425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Gerrit-Change-Number: 82425 Gerrit-PatchSet: 26 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 30 May 2024 17:51:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Appukuttan V K <appukuttan.vk(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard
by Appukuttan V K (Code Review) 30 May '24

30 May '24

Attention is currently required from: Appukuttan V K, Ronak Kanabar. Hello Ronak Kanabar, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82425?usp=email to look at the new patch set (#26). Change subject: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard ...................................................................... vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard This commit removes config guard around FSPM_ARCH_UPD from the FspApi.h header file. This change is done to ensure that this header file can be used with both x86_32 and x86_64 architectures and also with different FSP specification versions. The following modifications are made: - Removes PLATFORM_USES_FSP2_X86_32 config guard around FSPM_ARCH_UPD, this was added to isolate the structure from x64 build. This is not really required since the x64 build uses FSP2.4 structures. BUG=b:343428206 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/82425/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/82425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Gerrit-Change-Number: 82425 Gerrit-PatchSet: 26 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com>

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[XS] Change in coreboot[main]: vc/edk2-stable202302: Add config guards to support FSP 2.4
by Appukuttan V K (Code Review) 30 May '24

30 May '24

Attention is currently required from: Appukuttan V K, Ronak Kanabar. Hello Ronak Kanabar, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82425?usp=email to look at the new patch set (#25). Change subject: vc/edk2-stable202302: Add config guards to support FSP 2.4 ...................................................................... vc/edk2-stable202302: Add config guards to support FSP 2.4 This commit updates the FspApi.h header file to conditionally include different structures based on the platform architecture or FSP specification version. This changes are done to ensure that this header file can be used with both x86_32 and x86_64 architectures and also with different FSP specification versions. The following modifications are made: - Guard x86_32 architecture specific structures under PLATFORM_USES_FSP2_X86_32 config. - Guard FSP 2.4 specific structures under PLATFORM_USES_FSP2_4 config. BUG=b:343428206 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/82425/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/82425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Gerrit-Change-Number: 82425 Gerrit-PatchSet: 25 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 builds
by Subrata Banik (Code Review) 30 May '24

30 May '24

Attention is currently required from: Appukuttan V K. Subrata Banik has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82699?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 builds ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82699/comment/ea818cf9_a65472b3?us… : PS3, Line 9: EnableMultiPhaseSiliconInit upd is deprecated and has been : removed starting with v2.4 of FSP specification. > Have you confirmed the default value is 1 aka enabled now by default for FSP 2.4 build (irrespective of 32-bit or 64-bit)? -- To view, visit https://review.coreboot.org/c/coreboot/+/82699?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icdbf3bacc0a05975fc941b264fd400d74f506fce Gerrit-Change-Number: 82699 Gerrit-PatchSet: 3 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Comment-Date: Thu, 30 May 2024 17:27:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Appukuttan V K <appukuttan.vk(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: mb/razer/blade_stealth_kbl: Add H3Q variant
by Nico Huber (Code Review) 30 May '24

30 May '24

Attention is currently required from: Felix Singer, Paul Menzel, Reagan. Nico Huber has posted comments on this change by Reagan. ( https://review.coreboot.org/c/coreboot/+/82506?usp=email ) Change subject: mb/razer/blade_stealth_kbl: Add H3Q variant ...................................................................... Patch Set 10: Code-Review+2 (2 comments) File src/mainboard/razer/blade_stealth_kbl/spd/spd.h: File src/mainboard/razer/blade_stealth_kbl/variants/h3q/include/variant/gpio.h: https://review.coreboot.org/c/coreboot/+/82506/comment/fd1ce6cd_7884ea4e?us… : PS10, Line 8: /* Pad configuration was generated automatically using intelp2m utility */ There's a suspiciously huge amount of GPO's. Just wondering, did you confirm that this matches the register values? -- To view, visit https://review.coreboot.org/c/coreboot/+/82506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4 Gerrit-Change-Number: 82506 Gerrit-PatchSet: 10 Gerrit-Owner: Reagan <xbjfk.github(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reagan <xbjfk.github(a)gmail.com> Gerrit-Comment-Date: Thu, 30 May 2024 17:15:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: vc/edk2-stable202302: Add config guards to support FSP 2.4
by Appukuttan V K (Code Review) 30 May '24

30 May '24

Attention is currently required from: Appukuttan V K, Ronak Kanabar. Hello Ronak Kanabar, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82425?usp=email to look at the new patch set (#24). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: vc/edk2-stable202302: Add config guards to support FSP 2.4 ...................................................................... vc/edk2-stable202302: Add config guards to support FSP 2.4 This commit updates the FspApi.h header file to conditionally include different structures based on the platform architecture or FSP specification version. This changes are done to ensure that this header file can be used with both x86_32 and x86_64 architectures and also with different FSP specification versions. The following modifications are made: - Guard x86_32 architecture specific structures under PLATFORM_USES_FSP2_X86_32 config. - Guard FSP 2.4 specific structures under PLATFORM_USES_FSP2_4 config. BUG=b:343428206 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/82425/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/82425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Gerrit-Change-Number: 82425 Gerrit-PatchSet: 24 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com>

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