coreboot-gerrit April 2024

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 57: (1 comment) File src/soc/intel/xeon_sp/chip_gen6.c: https://review.coreboot.org/c/coreboot/+/81316/comment/cebefd40_cb74800a : PS56, Line 35: static void iio_pci_domain_read_resources(struct device *dev) > I updated legacy IO resources with constructors, however, for PCI domains we have some restrictions […] I created below ones as separate discussion. https://review.coreboot.org/c/coreboot/+/82098 https://review.coreboot.org/c/coreboot/+/82103 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 57 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 09:51:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add domain resource window creation utils
by Shuo Liu (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82103?usp=email ) Change subject: soc/intel/xeon_sp: Add domain resource window creation utils ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: This patch is from the discussion in CL81316 around resource window creation. Look forward to your review and good suggestions! -- To view, visit https://review.coreboot.org/c/coreboot/+/82103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e90512a48ab002a1c1d5031585ddadaac63673e Gerrit-Change-Number: 82103 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 09:50:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: device_util: Set resource limit in fixed_resource_range_idx
by Shuo Liu (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Lean Sheng Tan, Nico Huber, Patrick Rudolph. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82098?usp=email ) Change subject: device_util: Set resource limit in fixed_resource_range_idx ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: This patch is from the discussion in CL81316 around resource window creation. Look forward to your review and good suggestions! -- To view, visit https://review.coreboot.org/c/coreboot/+/82098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbd7cf21b4375a891f9149194445ba44af02642a Gerrit-Change-Number: 82098 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 09:50:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add domain resource window creation utils
by Shuo Liu (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82103?usp=email ) Change subject: soc/intel/xeon_sp: Add domain resource window creation utils ...................................................................... soc/intel/xeon_sp: Add domain resource window creation utils It might be benefical to have utils for domain resource window creation so that the correct IORESOURCE flags used could be guaranteed. TEST=Build on intel/avenuecity CRB Change-Id: I1e90512a48ab002a1c1d5031585ddadaac63673e Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/device/device_util.c M src/include/device/device.h M src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/chip_gen6.c M src/soc/intel/xeon_sp/spr/ioat.c 5 files changed, 73 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/82103/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index 312ef17..70fb881 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -776,7 +776,7 @@ } } -const struct resource *fixed_resource_range_idx(struct device *dev, unsigned long index, +const struct resource *resource_range_idx(struct device *dev, unsigned long index, uint64_t base, uint64_t size, unsigned long flags) { struct resource *resource; @@ -787,7 +787,7 @@ resource->base = base; resource->size = size; resource->limit = base + size - 1; - resource->flags = IORESOURCE_FIXED | IORESOURCE_ASSIGNED; + resource->flags = IORESOURCE_ASSIGNED; resource->flags |= flags; printk(BIOS_SPEW, "dev: %s, index: 0x%lx, base: 0x%llx, size: 0x%llx\n", diff --git a/src/include/device/device.h b/src/include/device/device.h index ac7e8691..506d5e7 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -262,7 +262,7 @@ /* These are temporary resource constructors to get us through the migration away from open-coding all the IORESOURCE_FLAGS. */ -const struct resource *fixed_resource_range_idx(struct device *dev, unsigned long index, +const struct resource *resource_range_idx(struct device *dev, unsigned long index, uint64_t base, uint64_t size, unsigned long flags); @@ -271,7 +271,8 @@ uint64_t base, uint64_t size, unsigned long flags) { - return fixed_resource_range_idx(dev, index, base, size, IORESOURCE_MEM | flags); + return resource_range_idx(dev, index, base, size, + IORESOURCE_FIXED | IORESOURCE_MEM | flags); } static inline @@ -284,6 +285,24 @@ } static inline +const struct resource *domain_mem_window_range(struct device *dev, unsigned long index, + uint64_t base, uint64_t size) +{ + return resource_range_idx(dev, index, base, size, + IORESOURCE_MEM); +} + +static inline +const struct resource *domain_mem_window_from_to(struct device *dev, unsigned long index, + uint64_t base, uint64_t end) +{ + if (end <= base) + return NULL; + return domain_mem_window_range(dev, index, base, end - base); +} + + +static inline const struct resource *ram_range(struct device *dev, unsigned long index, uint64_t base, uint64_t size) { @@ -343,7 +362,8 @@ const struct resource *fixed_io_range_flags(struct device *dev, unsigned long index, uint16_t base, uint16_t size, unsigned long flags) { - return fixed_resource_range_idx(dev, index, base, size, IORESOURCE_IO | flags); + return resource_range_idx(dev, index, base, size, + IORESOURCE_FIXED | IORESOURCE_IO | flags); } static inline @@ -362,6 +382,23 @@ return fixed_io_range_flags(dev, index, base, size, IORESOURCE_RESERVE); } +static inline +const struct resource *domain_io_window_range(struct device *dev, unsigned long index, + uint16_t base, uint16_t size) +{ + return resource_range_idx(dev, index, base, size, + IORESOURCE_IO); +} + +static inline +const struct resource *domain_io_window_from_to(struct device *dev, unsigned long index, + uint16_t base, uint16_t end) +{ + if (end <= base) + return NULL; + return domain_io_window_range(dev, index, base, end - base); +} + /* Compatibility code */ static inline void fixed_mem_resource_kb(struct device *dev, unsigned long index, diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index 720f236..dac5413 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -27,7 +27,6 @@ static void iio_pci_domain_read_resources(struct device *dev) { - struct resource *res; const STACK_RES *sr = domain_to_stack_res(dev); if (!sr) @@ -40,29 +39,17 @@ fixed_io_from_to_flags(dev, index++, 0x0000, 0x1000, IORESOURCE_SUBTRACTIVE); - if (sr->PciResourceIoBase < sr->PciResourceIoLimit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceIoBase; - res->limit = sr->PciResourceIoLimit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; - } + if (sr->PciResourceIoBase < sr->PciResourceIoLimit) + domain_io_window_from_to(dev, index++, + sr->PciResourceIoBase, sr->PciResourceIoLimit + 1); - if (sr->PciResourceMem32Base < sr->PciResourceMem32Limit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceMem32Base; - res->limit = sr->PciResourceMem32Limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (sr->PciResourceMem32Base < sr->PciResourceMem32Limit) + domain_mem_window_from_to(dev, index++, + sr->PciResourceMem32Base, sr->PciResourceMem32Limit + 1); - if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceMem64Base; - res->limit = sr->PciResourceMem64Limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) + domain_mem_window_from_to(dev, index++, + sr->PciResourceMem64Base, sr->PciResourceMem64Limit + 1); } /* @@ -125,7 +112,6 @@ #if CONFIG(SOC_INTEL_HAS_CXL) static void iio_cxl_domain_read_resources(struct device *dev) { - struct resource *res; const STACK_RES *sr = domain_to_stack_res(dev); if (!sr) @@ -133,29 +119,17 @@ int index = 0; - if (sr->IoBase < sr->PciResourceIoBase) { - res = new_resource(dev, index++); - res->base = sr->IoBase; - res->limit = sr->PciResourceIoBase - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; - } + if (sr->IoBase < sr->PciResourceIoBase) + domain_io_window_from_to(dev, index++, + sr->IoBase, sr->PciResourceIoBase); - if (sr->Mmio32Base < sr->PciResourceMem32Base) { - res = new_resource(dev, index++); - res->base = sr->Mmio32Base; - res->limit = sr->PciResourceMem32Base - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (sr->Mmio32Base < sr->PciResourceMem32Base) + domain_mem_window_from_to(dev, index++, + sr->Mmio32Base, sr->PciResourceMem32Base); - if (sr->Mmio64Base < sr->PciResourceMem64Base) { - res = new_resource(dev, index++); - res->base = sr->Mmio64Base; - res->limit = sr->PciResourceMem64Base - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (sr->Mmio64Base < sr->PciResourceMem64Base) + domain_mem_window_from_to(dev, index++, + sr->Mmio64Base, sr->PciResourceMem64Base); } static struct device_operations iio_cxl_domain_ops = { diff --git a/src/soc/intel/xeon_sp/chip_gen6.c b/src/soc/intel/xeon_sp/chip_gen6.c index 2e3a84f..358f26e 100644 --- a/src/soc/intel/xeon_sp/chip_gen6.c +++ b/src/soc/intel/xeon_sp/chip_gen6.c @@ -35,17 +35,12 @@ static void iio_pci_domain_read_resources(struct device *dev) { int index = 0; - struct resource *res; const UDS_PCIROOT_RES *pr = domain_to_pciroot_res(dev); /* Initialize the system-wide I/O space constraints. */ - if (pr->IoBase <= pr->IoLimit) { - res = new_resource(dev, index++); - res->base = pr->IoBase; - res->limit = pr->IoLimit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; - } + if (pr->IoBase <= pr->IoLimit) + domain_io_window_from_to(dev, index++, + pr->IoBase, pr->IoLimit + 1); /* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */ if (is_domain0(dev)) @@ -53,22 +48,14 @@ IORESOURCE_SUBTRACTIVE); /* Initialize the system-wide memory resources constraints. */ - if (pr->Mmio32Base <= pr->Mmio32Limit) { - res = new_resource(dev, index++); - res->base = pr->Mmio32Base; - res->limit = pr->Mmio32Limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (pr->Mmio32Base <= pr->Mmio32Limit) + domain_mem_window_from_to(dev, index++, + pr->Mmio32Base, pr->Mmio32Limit + 1); /* Initialize the system-wide memory resources constraints. */ - if (pr->Mmio64Base <= pr->Mmio64Limit) { - res = new_resource(dev, index++); - res->base = pr->Mmio64Base; - res->limit = pr->Mmio64Limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (pr->Mmio64Base <= pr->Mmio64Limit) + domain_mem_window_from_to(dev, index++, + pr->Mmio64Base, pr->Mmio64Limit + 1); } static struct device_operations iio_pcie_domain_ops = { diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index 9ed9576..a0babee 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -61,21 +61,11 @@ unsigned int index = 0; - if (mem32_base <= mem32_limit) { - struct resource *const res = new_resource(domain, index++); - res->base = mem32_base; - res->limit = mem32_limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (mem32_base <= mem32_limit) + domain_mem_window_from_to(domain, index++, mem32_base, mem32_limit + 1); - if (mem64_base <= mem64_limit) { - struct resource *const res = new_resource(domain, index++); - res->base = mem64_base; - res->limit = mem64_limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (mem64_base <= mem64_limit) + domain_mem_window_from_to(domain, index++, mem64_base, mem64_limit + 1); } void create_ioat_domains(const union xeon_domain_path path, -- To view, visit https://review.coreboot.org/c/coreboot/+/82103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e90512a48ab002a1c1d5031585ddadaac63673e Gerrit-Change-Number: 82103 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: device_util: Set resource limit in fixed_resource_range_idx
by Shuo Liu (Code Review) 29 Apr '24

29 Apr '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82098?usp=email to look at the new patch set (#2). Change subject: device_util: Set resource limit in fixed_resource_range_idx ...................................................................... device_util: Set resource limit in fixed_resource_range_idx TEST=Build on intel/avenuecity CRB Change-Id: Idbd7cf21b4375a891f9149194445ba44af02642a Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/device/device_util.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/82098/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbd7cf21b4375a891f9149194445ba44af02642a Gerrit-Change-Number: 82098 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Nico Huber (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 57: (1 comment) File src/soc/intel/xeon_sp/chip_gen6.c: https://review.coreboot.org/c/coreboot/+/81316/comment/255387af_f73cf8b5 : PS56, Line 56: res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; > Yes, both points are correct. […] No, fixed would be wrong and redundant here. PS 56 had it right. It makes no difference with the current LPC/eSPI code. But if somebody would change the latter, things would keep working if we advertise the correct window here (without reserving it, 'fixed' would reserve it). -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 57 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 09:48:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Makefile.mk: Align romstage to page directory pointer requirements
by Shuo Liu (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82102?usp=email ) Change subject: Makefile.mk: Align romstage to page directory pointer requirements ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Glad to have this :) -- To view, visit https://review.coreboot.org/c/coreboot/+/82102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94e4a4209b7441ecb2966a1342c3d46625771bb8 Gerrit-Change-Number: 82102 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 29 Apr 2024 09:43:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 57: (2 comments) File src/soc/intel/xeon_sp/chip_gen6.c: https://review.coreboot.org/c/coreboot/+/81316/comment/3566efb4_71a0158d : PS56, Line 56: res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; > Well, this is the domain level where we describe the windows available for […] Yes, both points are correct. For 1, should the 'fixed' flag be kept? (I suppose it should be okay to keep?). File src/soc/intel/xeon_sp/gnr/Kconfig: https://review.coreboot.org/c/coreboot/+/81316/comment/526e3a41_bafdfaaa : PS56, Line 17: select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND > That's why we do open-source, right? Because things that take a month or […] Yes, agree, the opensource discussion benefits :) -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 57 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 09:32:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
by Federico Amedeo Izzo (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Federico Amedeo Izzo. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82010?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1) ...................................................................... mb/aoostar: Add AOOSTAR R1 (WTR_R1) AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4 SODIMM slot. It also comes with 2x 2.5Gb Intel NICs, Intel AX200 WiFi + BT and USB-C Alt-DP Power Delivery. Working: - Automatic FAN control (IT8613E SuperIO) - M.2 NVME slot - 2x SATA ports (Issue on 3.5" HDD, see below) - USB 2.0 ports - USB 3.0 ports - USB-C port with Alt-DP and PD - HDMI / DisplayPort ports - 2x 2.5Gb NICs - WiFi + BT - MicroSD card reader - ASPM (Unavailable on stock) - Linux/Windows UEFI booting with EDK2 Broken: - Power button (OFF->ON broken, ON->OFF works) - 3.5" SATA HDDs (Detected only after reboot) Untested: - Internal audio - S3 My motivation for doing this port is enabling ASPM, as it makes a great difference on idle power consumption (from 8.4W to 5W measured from the wall). The last remaining annoyance of this port is the power button not working. I spent a few hours double checking the SuperIO registers but then I gave up. A workaround for this is to use the "ON after power loss" feature and reconnect the power cord to turn on the board. It's not a big problem for a NAS that will stay ON 24/7. Any hint on the power button or 3.5" HDD issue is welcome. VBT extracted from vendor BIOS. Compiled with FSP GOP video initialization, using IFD descriptor and ME blob extracted from vendor BIOS. The board can be flashed externally using a 1.8V adapter, I used a CH341a modded for 3.3V I/O. Internal flashing works, as flash is not read/write protected. Patchset 5: Re-enabled dptf, added default options to Kconfig. Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works Patchset 8: Fixed microSD card reader Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Signed-off-by: Federico Amedeo Izzo <federico(a)izzo.pro> --- A src/mainboard/aoostar/Kconfig A src/mainboard/aoostar/Kconfig.name A src/mainboard/aoostar/wtr_r1/Kconfig A src/mainboard/aoostar/wtr_r1/Kconfig.name A src/mainboard/aoostar/wtr_r1/Makefile.mk A src/mainboard/aoostar/wtr_r1/board_info.txt A src/mainboard/aoostar/wtr_r1/bootblock.c A src/mainboard/aoostar/wtr_r1/data.vbt A src/mainboard/aoostar/wtr_r1/devicetree.cb A src/mainboard/aoostar/wtr_r1/dsdt.asl A src/mainboard/aoostar/wtr_r1/gpio.h A src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c 12 files changed, 723 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/82010/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 9 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Nico Huber (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 57: (2 comments) File src/soc/intel/xeon_sp/chip_gen6.c: https://review.coreboot.org/c/coreboot/+/81316/comment/5a1b7ebc_24b08013 : PS56, Line 56: res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; > Good suggestion! Updated. Well, this is the domain level where we describe the windows available for allocation. It's probably just coincidence that it matches in position and size what we usually tag fixed. There are two things: 1. Xeon-SP hardware always forwards (or is configured by FSP to always forward) this, iow. makes it available for anything below DMI I guess (not fixed. maybe subtractive maybe not, doesn't matter to the resource allocator). 2. Developers are lazy and instead of adding all the "Fixed I/O Ranges Decoded by PCH" (table usually found it PCH datasheets) individually, we add a bulk 0..fff fixed resource, traditionally to the LPC/eSPI device as representative for all the legacy things in a PCH. Now, 2. is already done in common/block/lpc code. File src/soc/intel/xeon_sp/gnr/Kconfig: https://review.coreboot.org/c/coreboot/+/81316/comment/79f4105d_cb487072 : PS56, Line 17: select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND > GNR still needs this ... the related discussion history is at: […] That's why we do open-source, right? Because things that take a month or two in open-source take years in proprietary projects. -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 57 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 09:14:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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