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Hello Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81316?usp=email
to look at the new patch set (#58).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
soc/intel/xeon_sp: Add Granite Rapids initial codes
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.
This patch initially sets the code set up as a build target with
Granite Rapids N-1 FSP (src/vc/intel/fsp/fsp2_0/graniterapids).
1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmitsburg PCH)'s codes are reused.
2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.
Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Co-authored-by: Gang Chen <gang.c.chen(a)intel.com>
Co-authored-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/soc/intel/xeon_sp/Makefile.mk
A src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/Kconfig
A src/soc/intel/xeon_sp/gnr/Makefile.mk
A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
A src/soc/intel/xeon_sp/gnr/chip.c
A src/soc/intel/xeon_sp/gnr/chip.h
A src/soc/intel/xeon_sp/gnr/chipset.cb
A src/soc/intel/xeon_sp/gnr/cpu.c
A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h
A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h
A src/soc/intel/xeon_sp/gnr/ramstage.c
A src/soc/intel/xeon_sp/gnr/romstage.c
A src/soc/intel/xeon_sp/gnr/soc_acpi.c
A src/soc/intel/xeon_sp/gnr/soc_util.c
17 files changed, 1,075 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/58
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Change subject: payloads/iPXE: add TRUST_CMD switch
......................................................................
Patch Set 6:
(1 comment)
File payloads/external/iPXE/Kconfig:
https://review.coreboot.org/c/coreboot/+/79684/comment/8a0673e8_7482e5d9 :
PS5, Line 112: config PXE_CUSTOM_BUILD_ID
> This probably belongs to another patch?
Yess, fixed [here](https://review.coreboot.org/c/coreboot/+/79684/5..6/payloads/external…
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Filip Lewiński has uploaded a new patch set (#6) to the change originally created by Maciej Pijanowski. ( https://review.coreboot.org/c/coreboot/+/79684?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: payloads/iPXE: add TRUST_CMD switch
......................................................................
payloads/iPXE: add TRUST_CMD switch
Change-Id: Ia4f5d4140eeb8625c5ee41e38f048658db28a199
Signed-off-by: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com>
---
M payloads/external/Makefile.mk
M payloads/external/iPXE/Kconfig
M payloads/external/iPXE/Makefile
3 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/79684/6
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Change subject: soc/intel/xeon_sp: Add domain resource window creation utils
......................................................................
Patch Set 1: Code-Review+1
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Change subject: device_util: Set resource limit in fixed_resource_range_idx
......................................................................
Patch Set 2: Code-Review+1
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 57:
(1 comment)
File src/soc/intel/xeon_sp/chip_gen6.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/cebefd40_cb74800a :
PS56, Line 35: static void iio_pci_domain_read_resources(struct device *dev)
> I updated legacy IO resources with constructors, however, for PCI domains we have some restrictions […]
I created below ones as separate discussion.
https://review.coreboot.org/c/coreboot/+/82098https://review.coreboot.org/c/coreboot/+/82103
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