coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/corsola/wugtrio: Add initialization of USB port0
by Yu-Ping Wu (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Hung-Te Lin, Wentao Qin, Xuxin Xiong, Yang Wu. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email ) Change subject: mb/google/corsola/wugtrio: Add initialization of USB port0 ...................................................................... Patch Set 9: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82089/comment/04ff01d8_edb38807 : PS9, Line 7: wugtrio var/wugtrio File src/soc/mediatek/common/usb.c: https://review.coreboot.org/c/coreboot/+/82089/comment/3c833010_cc399cff : PS9, Line 162: Can we also add `update_usb_base_regs(SSUSB_IPPC_BASE, SSUSB_SIF_BASE)` here, so that the behavior is independent of the calling order of `setup_usb_secondary_host` and `setup_usb_host`. File src/soc/mediatek/mt8186/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/82089/comment/0be23ff1_5f08fff9 : PS9, Line 80: SSUSB_IPPC_BASE = IO_PHYS + 0x01283E00, : SSUSB_IPPC_BASE_P0 = IO_PHYS + 0x01203E00, Sort by addresses. -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 9 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 09:11:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/hp/280_g2: Fix comment in `gma-mainboard.ads`
by Paul Menzel (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82112?usp=email ) Change subject: mb/hp/280_g2: Fix comment in `gma-mainboard.ads` ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74c1257efb67cfdff2ae04a42c163dd320c850a4 Gerrit-Change-Number: 82112 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 09:08:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for SPI RW
by Patrick Rudolph (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Ashish Kumar Mishra, Paul Menzel, Saurabh Mishra, Subrata Banik. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email ) Change subject: block/fast_spi: Use read32p/write32p for SPI RW ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 4 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 29 Apr 2024 09:06:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for SPI RW
by Angel Pons (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Ashish Kumar Mishra, Paul Menzel, Saurabh Mishra, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email ) Change subject: block/fast_spi: Use read32p/write32p for SPI RW ...................................................................... Patch Set 4: (2 comments) File src/soc/intel/common/block/fast_spi/fast_spi_flash.c: https://review.coreboot.org/c/coreboot/+/82079/comment/5e9cf939_fa0bfed9 : PS4, Line 81: (len >> 2) This optimisation can be done by the compiler. There's absolutely no reason to write code that's harder for people to understand. Just use `len / 4`, please. The point is to use `4` everywhere (or, if you want, `sizeof(uint32_t)`. https://review.coreboot.org/c/coreboot/+/82079/comment/ee34d119_8c673147 : PS4, Line 85: (len & 3) Same here, please use `len % 4` -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 4 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 29 Apr 2024 09:05:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Makefile.mk: Align romstage to page directory pointer requirements
by Patrick Rudolph (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82102?usp=email ) Change subject: Makefile.mk: Align romstage to page directory pointer requirements ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94e4a4209b7441ecb2966a1342c3d46625771bb8 Gerrit-Change-Number: 82102 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 29 Apr 2024 09:04:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board
by Federico Amedeo Izzo (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Brandon Weeks, Joel Linn, Paul Menzel. Federico Amedeo Izzo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81595?usp=email ) Change subject: mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81595/comment/79cb6391_611589a9 : PS2, Line 18: - Fan (ITE IT8613E) > According to the IT8613E Kconfig the EC configuration is supported. […] I just submitted a port for AOOSTAR R1 with working fan control on IT8613E SuperIO: https://review.coreboot.org/c/coreboot/+/82010 Regarding the devicetree configuration: For TMPIN number and types and fan numbers I loaded this driver: https://aur.archlinux.org/packages/it87-dkms-git and looked at the output of lm_sensors while running the vendor BIOS. For io and irq registers I looked at superiotool dump LDN 0x04. Finally nothing worked unless I set the correct gen1/2/3/4_dec addresses. -- To view, visit https://review.coreboot.org/c/coreboot/+/81595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Gerrit-Change-Number: 81595 Gerrit-PatchSet: 4 Gerrit-Owner: Brandon Weeks <bweeks(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-CC: Matthew Garrett <mjgarrett59(a)googlemail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Brandon Weeks <bweeks(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Comment-Date: Mon, 29 Apr 2024 08:53:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Brandon Weeks <bweeks(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/wugtrio: Add initialization of USB port0
by Paul Menzel (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Hung-Te Lin, Wentao Qin, Xuxin Xiong, Yang Wu, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email ) Change subject: mb/google/corsola/wugtrio: Add initialization of USB port0 ...................................................................... Patch Set 9: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82089/comment/60c25952_6f873dd8 : PS9, Line 7: port0 I’d spell it with a space: port 0 (If you agree, please update all other places too.) https://review.coreboot.org/c/coreboot/+/82089/comment/344039e1_7154c259 : PS9, Line 7: Add initialization of Initialize https://review.coreboot.org/c/coreboot/+/82089/comment/73e7b445_7c4ce28f : PS9, Line 11: Please describe the implementation. You use fwconfig for this, for example? -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 9 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 08:46:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Makefile.mk: Align romstage to page directory pointer requirements
by Paul Menzel (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82102?usp=email ) Change subject: Makefile.mk: Align romstage to page directory pointer requirements ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82102/comment/754702cd_7efe7dee : PS1, Line 10: which have an larger alignment requirement. … So, increase them from 64 bytes to 4 kB. https://review.coreboot.org/c/coreboot/+/82102/comment/771a95a1_d08cef9a : PS1, Line 10: an a -- To view, visit https://review.coreboot.org/c/coreboot/+/82102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94e4a4209b7441ecb2966a1342c3d46625771bb8 Gerrit-Change-Number: 82102 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 29 Apr 2024 08:44:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86: Link page tables in stage if possible
by Arthur Heymans (Code Review) 29 Apr '24

29 Apr '24

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80337?usp=email ) Change subject: cpu/x86: Link page tables in stage if possible ...................................................................... Patch Set 22: (1 comment) Patchset: PS22: > This change breaks systems that use PLATFORM_USES_FSP2_X86_32 and HAVE_MRC due to romstage not being aligned to 4096 and thus the page tables are also not aligned. https://review.coreboot.org/c/coreboot/+/82102 -- To view, visit https://review.coreboot.org/c/coreboot/+/80337?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Gerrit-Change-Number: 80337 Gerrit-PatchSet: 22 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 08:08:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Makefile.mk: Align romstage to page directory pointer requirements
by Arthur Heymans (Code Review) 29 Apr '24

29 Apr '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82102?usp=email ) Change subject: Makefile.mk: Align romstage to page directory pointer requirements ...................................................................... Makefile.mk: Align romstage to page directory pointer requirements On x86_64 romstage can contain page tables and a page table pointer which have an larger alignment requirement. Change-Id: I94e4a4209b7441ecb2966a1342c3d46625771bb8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.mk 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/82102/1 diff --git a/Makefile.mk b/Makefile.mk index e642ac7..c476afb 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -1276,7 +1276,7 @@ $(CONFIG_CBFS_PREFIX)/romstage-options := -b 0 endif ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -# Use a 64 byte alignment to provide a minimum alignment +# Use a 4096 byte alignment to provide a minimum alignment # requirement for the overall romstage. While the first object within # romstage could have a 4 byte minimum alignment that doesn't mean the linker # won't decide the entire section should be aligned to a larger value. In the @@ -1284,7 +1284,7 @@ # requirements of the program segment. # # Make sure that segment for .car.data is ignored while adding romstage. -$(CONFIG_CBFS_PREFIX)/romstage-align := 64 +$(CONFIG_CBFS_PREFIX)/romstage-align := 4096 ifeq ($(CONFIG_NO_XIP_EARLY_STAGES),y) $(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data" else -- To view, visit https://review.coreboot.org/c/coreboot/+/82102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94e4a4209b7441ecb2966a1342c3d46625771bb8 Gerrit-Change-Number: 82102 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit April 2024