coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/corsola/var/wugtrio: Add initialize USB port 0
by Wentao Qin (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Wentao Qin, Xuxin Xiong, Yang Wu, Yu-Ping Wu. Hello Hung-Te Lin, Mingjin Ge, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82089?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/corsola/var/wugtrio: Add initialize USB port 0 ...................................................................... mb/google/corsola/var/wugtrio: Add initialize USB port 0 The default MT8186 platform is to initialize USB3 port 1. Use option 27th in fwconfig to enable initialization of USB2 port 0 to support devices mounted on it. BUG=b:335124437 TEST=boot to OS from USB-A boot to OS from SD Card BRANCH=corsola Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/devicetree.cb M src/mainboard/google/corsola/mainboard.c M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c A src/soc/mediatek/common/usb_secondary.c M src/soc/mediatek/mt8186/Makefile.mk M src/soc/mediatek/mt8186/include/soc/addressmap.h 7 files changed, 43 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/82089/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 11 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
by Federico Amedeo Izzo (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Federico Amedeo Izzo. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82010?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1) ...................................................................... mb/aoostar: Add AOOSTAR R1 (WTR_R1) AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4 SODIMM slot. It also comes with 2x 2.5Gb Intel NICs, Intel AX200 WiFi + BT and USB-C Alt-DP Power Delivery. Working: - Automatic FAN control (IT8613E SuperIO) - M.2 NVME slot - 2x SATA ports (Issue on 3.5" HDD, see below) - USB 2.0 ports - USB 3.0 ports - USB-C port with Alt-DP and PD - HDMI / DisplayPort ports - 2x 2.5Gb NICs - WiFi + BT - MicroSD card reader - ASPM (Unavailable on stock) - Linux (Arch Linux, kernel 6.8.7-arch1-1) UEFI booting with EDK2 - Windows 10 UEFI booting with EDK2 Broken: - Power button (OFF->ON broken, ON->OFF works) - 3.5" SATA HDDs (Detected only after reboot) Untested: - Internal audio - S3 My motivation for doing this port is enabling ASPM, as it makes a great difference on idle power consumption (from 8.4W to 5W measured from the wall). The last remaining annoyance of this port is the power button not working. I spent a few hours double checking the SuperIO registers but then I gave up. A workaround for this is to use the "ON after power loss" feature and reconnect the power cord to turn on the board. It's not a big problem for a NAS that will stay ON 24/7. Any hint on the power button or 3.5" HDD issue is welcome. VBT extracted from vendor UEFI firmware version 1AXFE 0.01 x64 (Build date and time 11/29/2023 10:57:44) Compiled with FSP GOP video initialization, using IFD descriptor and ME blob extracted from vendor UEFI firmware (see above). The board can be flashed externally using a 1.8V adapter, I used a CH341a modded for 3.3V I/O. Internal flashing works, as flash is not read/write protected. Patchset 5: Re-enabled dptf, added default options to Kconfig. Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works Patchset 8: Fixed microSD card reader Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Signed-off-by: Federico Amedeo Izzo <federico(a)izzo.pro> --- A src/mainboard/aoostar/Kconfig A src/mainboard/aoostar/Kconfig.name A src/mainboard/aoostar/wtr_r1/Kconfig A src/mainboard/aoostar/wtr_r1/Kconfig.name A src/mainboard/aoostar/wtr_r1/Makefile.mk A src/mainboard/aoostar/wtr_r1/board_info.txt A src/mainboard/aoostar/wtr_r1/bootblock.c A src/mainboard/aoostar/wtr_r1/data.vbt A src/mainboard/aoostar/wtr_r1/devicetree.cb A src/mainboard/aoostar/wtr_r1/dsdt.asl A src/mainboard/aoostar/wtr_r1/gpio.h A src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c 12 files changed, 716 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/82010/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 10 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/corsola/var/wugtrio: Add initialize of USB port 0
by Yidi Lin (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Wentao Qin, Xuxin Xiong, Yang Wu, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email ) Change subject: mb/google/corsola/var/wugtrio: Add initialize of USB port 0 ...................................................................... Patch Set 10: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82089/comment/b21cc945_357ba713 : PS10, Line 7: Add initialize of USB port 0 Initialize USB port 0 File src/soc/mediatek/common/usb.c: https://review.coreboot.org/c/coreboot/+/82089/comment/ecd4bdfd_e65b90f6 : PS9, Line 162: > But this will not receive the parameters of SSUSB_IPPC_BASE_P0 and SSUSB_SIF_BASE_P0 You can do something like this common/usb.c ``` void setup_usb_host_controller(void) { u3p_msg("Setting up USB HOST controller...\n"); mtk_usb_prepare(); ssusb_soft_reset(); if (u3phy_ports_enable()) { u3p_err("%s fail to enable ports\n", __func__); return; } u3phy_power_on(); mtk_usb_adjust_phy_shift(); u3p_msg("phy power-on done.\n"); } void setup_usb_host(void) { update_usb_base_regs(SSUSB_IPPC_BASE, SSUSB_SIF_BASE); setup_usb_host_controller(); } ``` common/usb_secondary.c ``` void setup_usb_secondary_host(void) { /* We always consider USB2 port as the secondary UBS host regardless of the register naming */ update_usb_base_regs(SSUSB_IPPC_BASE_P0, SSUSB_SIF_BASE_P0); setup_usb_host_controller(); } ``` Then we can call `setup_usb_host` for the primary USB host and call `setup_usb_secondary_host` for the secondary USB host. -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 10 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 12:24:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/var/wugtrio: Add initialize of USB port 0
by Wentao Qin (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu. Wentao Qin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email ) Change subject: mb/google/corsola/var/wugtrio: Add initialize of USB port 0 ...................................................................... Patch Set 10: (1 comment) File src/soc/mediatek/common/usb.c: https://review.coreboot.org/c/coreboot/+/82089/comment/33e05292_f5dcfd84 : PS9, Line 162: > Can we also add `update_usb_base_regs(SSUSB_IPPC_BASE, SSUSB_SIF_BASE)` here, so that the behavior i […] But this will not receive the parameters of SSUSB_IPPC_BASE_P0 and SSUSB_SIF_BASE_P0 -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 10 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 12:07:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/var/wugtrio: Add initialize of USB port 0
by Wentao Qin (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu. Wentao Qin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email ) Change subject: mb/google/corsola/var/wugtrio: Add initialize of USB port 0 ...................................................................... Patch Set 10: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82089/comment/aa643bdf_6f3b697e : PS9, Line 7: Add initialization of > Initialize Done https://review.coreboot.org/c/coreboot/+/82089/comment/568b32a3_fc698161 : PS9, Line 7: wugtrio > var/wugtrio Done https://review.coreboot.org/c/coreboot/+/82089/comment/7ad592ea_ea72ea92 : PS9, Line 7: port0 > I’d spell it with a space: port 0 […] Done https://review.coreboot.org/c/coreboot/+/82089/comment/06a5f6e7_06410340 : PS9, Line 11: > Please describe the implementation. […] Done File src/soc/mediatek/mt8186/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/82089/comment/ed17c696_4a6ed858 : PS9, Line 80: SSUSB_IPPC_BASE = IO_PHYS + 0x01283E00, : SSUSB_IPPC_BASE_P0 = IO_PHYS + 0x01203E00, > Sort by addresses. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 10 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 11:56:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/var/wugtrio: Add initialize of USB port 0
by Wentao Qin (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Hung-Te Lin, Wentao Qin, Xuxin Xiong, Yang Wu, Yidi Lin. Hello Hung-Te Lin, Mingjin Ge, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82089?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Yidi Lin, Verified+1 by build bot (Jenkins) Change subject: mb/google/corsola/var/wugtrio: Add initialize of USB port 0 ...................................................................... mb/google/corsola/var/wugtrio: Add initialize of USB port 0 The default MT8186 platform is to initialize USB3 port 1. Use option 27th in fwconfig to enable initialization of USB2 port 0 to support devices mounted on it. BUG=b:335124437 TEST=boot to OS from USB-A boot to OS from SD Card BRANCH=corsola Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/devicetree.cb M src/mainboard/google/corsola/mainboard.c M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c A src/soc/mediatek/common/usb_secondary.c M src/soc/mediatek/mt8186/Makefile.mk M src/soc/mediatek/mt8186/include/soc/addressmap.h 7 files changed, 35 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/82089/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 10 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board
by Paul Menzel (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Brandon Weeks, Joel Linn. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81595?usp=email ) Change subject: mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board ...................................................................... Patch Set 4: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81595/comment/07a03947_494cad70 : PS2, Line 12: - DisplayPort / HDMI > VBT was extracted from the vendor UEFI firmware. It’d be great if you documented that (also UEFI firmware version). https://review.coreboot.org/c/coreboot/+/81595/comment/a71bf606_87913ad8 : PS2, Line 21: > I believe at least S0ix is working but digging into ACPI and Linux power management is where I ran o […] Feel free to update the commit message accordingly, or just ignore, and mark as resolved. Commit Message: https://review.coreboot.org/c/coreboot/+/81595/comment/ae975e76_40a14d60 : PS4, Line 26: Linux It’s always helpful to also document the used Linux version. Patchset: PS4: As this boots GNU/Linux this should get submitted soon, and the rest be fixed in follow-ups. Great work. Feel free to ignore my nitpicks. -- To view, visit https://review.coreboot.org/c/coreboot/+/81595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Gerrit-Change-Number: 81595 Gerrit-PatchSet: 4 Gerrit-Owner: Brandon Weeks <bweeks(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-CC: Matthew Garrett <mjgarrett59(a)googlemail.com> Gerrit-Attention: Brandon Weeks <bweeks(a)google.com> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Comment-Date: Mon, 29 Apr 2024 11:48:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Brandon Weeks <bweeks(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpi: Fix return value in acpi_device_write_dsd_gpio()
by Paul Menzel (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Jianeng Ceng, Paul Menzel. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82088?usp=email ) Change subject: acpi: Fix return value in acpi_device_write_dsd_gpio() ...................................................................... Patch Set 6: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82088/comment/3b7a15c9_521bedc6 : PS6, Line 11: The error was introduced in the commit making it public: Blank line above. https://review.coreboot.org/c/coreboot/+/82088/comment/ad1f95ec_accfa204 : PS6, Line 11: The error was introduced in the commit making it public: : commit 01344bce Maybe: Commit 01344bce1a60 (acpi: Make acpi_device_write_dsd_gpio() public) introduced the error by removing the parentheses, when refactoring the assignment. https://review.coreboot.org/c/coreboot/+/82088/comment/2dae7e18_09c886d0 : PS6, Line 16: Maybe even add the tag below (although we have no policy to this effect): Fixes: 01344bce1a60 ("acpi: Make acpi_device_write_dsd_gpio() public") Patchset: PS6: Feel free to address my nitpicks or to ignore them. -- To view, visit https://review.coreboot.org/c/coreboot/+/82088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a3eb89633aaebebc8bd98ac6126c578fda23839 Gerrit-Change-Number: 82088 Gerrit-PatchSet: 6 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 11:43:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: payloads/iPXE: add TRUST_CMD switch
by Felix Singer (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Filip Lewiński, Maciej Pijanowski, Martin L Roth, Stefan Reinauer. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79684?usp=email ) Change subject: payloads/iPXE: add TRUST_CMD switch ...................................................................... Patch Set 6: (1 comment) File payloads/external/iPXE/Makefile: https://review.coreboot.org/c/coreboot/+/79684/comment/12f9a839_6313ac99 : PS6, Line 56: sed 's|.*IMAGE_TRUST_CMD|#define IMAGE_TRUST_CMD|g' "$(project_dir)/src/config/general.h" > "$(project_dir)/src/config/general.h.tmp" Please use the way the other options are configured, see e.g. line 53. -- To view, visit https://review.coreboot.org/c/coreboot/+/79684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4f5d4140eeb8625c5ee41e38f048658db28a199 Gerrit-Change-Number: 79684 Gerrit-PatchSet: 6 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Apr 2024 11:18:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 58: (1 comment) File src/soc/intel/xeon_sp/chip_gen6.c: https://review.coreboot.org/c/coreboot/+/81316/comment/b75b8359_1940c67e : PS56, Line 56: res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; > No, fixed would be wrong and redundant here. PS 56 had it right. It makes […] Thanks, updated! -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 58 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 11:17:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2024