coreboot-gerrit April 2024

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[M] Change in coreboot[main]: mb/framework: Push initial port of azalea (Framework 13 AMD 7040)
by Felix Held (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Martin L Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81978?usp=email ) Change subject: mb/framework: Push initial port of azalea (Framework 13 AMD 7040) ...................................................................... Patch Set 7: (1 comment) File src/mainboard/framework/azalea/Kconfig: https://review.coreboot.org/c/coreboot/+/81978/comment/5f864523_feb10293 : PS7, Line 4: select BOARD_ROMSIZE_KB_32768 did you verify if this works as expected? i think a flash size of more than 32 mbyte will only work as expected on genoa, but not on phoenix -- To view, visit https://review.coreboot.org/c/coreboot/+/81978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief4b5c75471a2ef5bedaaee9b4737510c2826b6e Gerrit-Change-Number: 81978 Gerrit-PatchSet: 7 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Daniel Schaefer <dhs(a)frame.work> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Kieran Levin <ktl(a)frame.work> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jean Lucas Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 15:36:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: payloads/iPXE: add TRUST_CMD switch
by Filip Lewiński (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Felix Singer, Maciej Pijanowski, Martin L Roth, Stefan Reinauer. Filip Lewiński has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79684?usp=email ) Change subject: payloads/iPXE: add TRUST_CMD switch ...................................................................... Patch Set 7: (1 comment) File payloads/external/iPXE/Makefile: https://review.coreboot.org/c/coreboot/+/79684/comment/18e6a484_71c8fde7 : PS6, Line 56: sed 's|.*IMAGE_TRUST_CMD|#define IMAGE_TRUST_CMD|g' "$(project_dir)/src/config/general.h" > "$(project_dir)/src/config/general.h.tmp" > Please use the way the other options are configured, see e.g. line 53. Fixed [here](https://review.coreboot.org/c/coreboot/+/79684/7/payloads/external/iP… -- To view, visit https://review.coreboot.org/c/coreboot/+/79684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4f5d4140eeb8625c5ee41e38f048658db28a199 Gerrit-Change-Number: 79684 Gerrit-PatchSet: 7 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Apr 2024 15:19:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE
by Felix Singer (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Christian Walter, Dinesh Gehlot, Eric Lai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Subrata Banik, Tim Crawford. Hello Angel Pons, Christian Walter, Dinesh Gehlot, Eric Lai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Subrata Banik, Tim Crawford, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82115?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE ...................................................................... soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total SPD size of 512 bytes. Set this as the default and remove the setting from mainboard Kconfigs. Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brya/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/shadowmountain/Kconfig M src/mainboard/msi/ms7d25/Kconfig M src/mainboard/msi/ms7e06/Kconfig M src/mainboard/prodrive/atlas/Kconfig M src/mainboard/system76/adl/Kconfig M src/mainboard/system76/rpl/Kconfig M src/soc/intel/alderlake/Kconfig 10 files changed, 3 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/82115/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/82115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Gerrit-Change-Number: 82115 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: payloads/iPXE: add TRUST_CMD switch
by Filip Lewiński (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Filip Lewiński, Maciej Pijanowski, Martin L Roth, Stefan Reinauer. Filip Lewiński has uploaded a new patch set (#7) to the change originally created by Maciej Pijanowski. ( https://review.coreboot.org/c/coreboot/+/79684?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: payloads/iPXE: add TRUST_CMD switch ...................................................................... payloads/iPXE: add TRUST_CMD switch Change-Id: Ia4f5d4140eeb8625c5ee41e38f048658db28a199 Signed-off-by: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> --- M payloads/external/Makefile.mk M payloads/external/iPXE/Kconfig M payloads/external/iPXE/Makefile 3 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/79684/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/79684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4f5d4140eeb8625c5ee41e38f048658db28a199 Gerrit-Change-Number: 79684 Gerrit-PatchSet: 7 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE
by Felix Singer (Code Review) 29 Apr '24

29 Apr '24

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82115?usp=email ) Change subject: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/82115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Gerrit-Change-Number: 82115 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Apr 2024 15:13:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Add Granite Rapids FSP to Xeon-SP
by Felix Held (Code Review) 29 Apr '24

29 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82082?usp=email ) Change subject: MAINTAINERS: Add Granite Rapids FSP to Xeon-SP ...................................................................... MAINTAINERS: Add Granite Rapids FSP to Xeon-SP Change-Id: I5170a69d798d0e8198b89f6932a80e6051228ac2 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82082 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M MAINTAINERS 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Angel Pons: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved build bot (Jenkins): Verified diff --git a/MAINTAINERS b/MAINTAINERS index 2963ab4..c23e3d0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -951,6 +951,7 @@ F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp/ F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/ F: src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/ +F: src/vendorcode/intel/fsp/fsp2_0/graniterapids/ MEDIATEK SOCS M: Hung-Te Lin <hungte(a)chromium.org> -- To view, visit https://review.coreboot.org/c/coreboot/+/82082?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5170a69d798d0e8198b89f6932a80e6051228ac2 Gerrit-Change-Number: 82082 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brya/xol: Add Fn key scancode
by Felix Held (Code Review) 29 Apr '24

29 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82069?usp=email ) Change subject: mb/google/brya/xol: Add Fn key scancode ...................................................................... mb/google/brya/xol: Add Fn key scancode The Fn key on Xol emits a scancode of 94 (0x5e). BUG=b:327656989 TEST=Flash xol, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: I34ed93d9666504bfd4d439e166911e49f58e5ff5 Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82069 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, but someone else must approve build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 66839d1..1565f13 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config ACPI_FNKEY_GEN_SCANCODE + default 94 if BOARD_GOOGLE_XOL + config BOARD_GOOGLE_BRYA_COMMON def_bool n select DRIVERS_GENERIC_ALC1015 -- To view, visit https://review.coreboot.org/c/coreboot/+/82069?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34ed93d9666504bfd4d439e166911e49f58e5ff5 Gerrit-Change-Number: 82069 Gerrit-PatchSet: 3 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
by Angel Pons (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Federico Amedeo Izzo, Felix Singer. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email ) Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1) ...................................................................... Patch Set 10: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82010/comment/5ab0d110_fcc5390e : PS10, Line 57: Patchset 5: Re-enabled dptf, added default options to Kconfig. : Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works : Pa > It's not needed to document the changes of each patchset. Please remove. Doesn't hurt, and it's common practice in mailing lists commits. File src/mainboard/aoostar/wtr_r1/bootblock.c: https://review.coreboot.org/c/coreboot/+/82010/comment/76d7cee0_ca20571d : PS10, Line 20: ite_set_3vsbsw(GPIO_DEV, true); Where do the Super I/O settings come from? On the IT8625E (closest chip for which I have a datasheet), GP40 is muxed with 3VSBSW#. Since you're configuring GP40 as a GPIO, this doesn't seem to have any effect. I would recommend double-checking these settings, as this can cause the board to misbehave. https://review.coreboot.org/c/coreboot/+/82010/comment/43d421f4_94d03208 : PS10, Line 21: ite_delay_pwrgd3(GPIO_DEV); There's very few boards that use this, is it actually needed? Hard to say without testing S3, though. File src/mainboard/aoostar/wtr_r1/devicetree.cb: https://review.coreboot.org/c/coreboot/+/82010/comment/59d3b05c_35771ed3 : PS10, Line 117: .clk_req = 2, How were CLKSRC and CLKREQ values determined? These could be causing troubles with power management. File src/mainboard/aoostar/wtr_r1/gpio.h: https://review.coreboot.org/c/coreboot/+/82010/comment/0dd6be0c_e003e5db : PS10, Line 207: _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PWRBTN# */ Try this instead: `PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1)` If this doesn't work, you can try different settings for pad reset (`PWROK`, `DEEP`, `PLTRST`, `RSMRST`; the current `_PAD_CFG_STRUCT` values correspond to `PWROK` for reset). -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 10 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Comment-Date: Mon, 29 Apr 2024 14:32:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/x11-lga1151-series: Add x11ssw-f
by Angel Pons (Code Review) 29 Apr '24

29 Apr '24

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77610?usp=email ) Change subject: mb/x11-lga1151-series: Add x11ssw-f ...................................................................... Patch Set 12: (1 comment) File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md: https://review.coreboot.org/c/coreboot/+/77610/comment/17aaad52_26f4ee70 : PS2, Line 22: - Right PCIe slot : - NVMe : > At least KBL FSP does not have any options for that IIRC, PEG bifurcation is controlled by some strap pins, so in theory enabling the root ports in the devicetree should suffice. -- To view, visit https://review.coreboot.org/c/coreboot/+/77610?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53a0b6012ae64cf1ba4b625f11aaf771637307f3 Gerrit-Change-Number: 77610 Gerrit-PatchSet: 12 Gerrit-Owner: Kieran Kunhya <kieran(a)kunhya.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Apr 2024 14:26:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kieran Kunhya <kieran(a)kunhya.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
by Felix Singer (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Federico Amedeo Izzo. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email ) Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1) ...................................................................... Patch Set 10: (1 comment) File src/mainboard/aoostar/wtr_r1/gpio.h: https://review.coreboot.org/c/coreboot/+/82010/comment/93ab69bd_134955b5 : PS10, Line 14: _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | : PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* CORE_VID0 */ Would be great if these could be translated to more readable macros, like ``` PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ ``` However, that can be done in a separate change. Let's keep it as it is for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 10 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Comment-Date: Mon, 29 Apr 2024 14:14:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2024