coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for SPI RW
by Angel Pons (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Ashish Kumar Mishra, Patrick Rudolph, Paul Menzel, Saurabh Mishra, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email ) Change subject: block/fast_spi: Use read32p/write32p for SPI RW ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS5: Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 5 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 29 Apr 2024 17:18:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox: Disable c1 state auto-demotion
by Ashish Kumar Mishra (Code Review) 29 Apr '24

29 Apr '24

Ashish Kumar Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82104?usp=email ) Change subject: mb/google/brox: Disable c1 state auto-demotion ...................................................................... mb/google/brox: Disable c1 state auto-demotion Disable c1 state auto-demotion support for brox BUG=None BRANCH=None TEST=Boot brox and verify in fsp debug logs Change-Id: I18d40cd721d46fce4702cf1a943583cd41c03cf4 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/82104/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index f901db9..89c714d 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -21,6 +21,9 @@ # seen on J0 and Q0 SKUs register "disable_package_c_state_demotion" = "1" + # Disable C1 state auto-demotion for all brox baseboards + register "disable_c1_state_auto_demotion" = "1" + # DPTF enable register "dptf_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/82104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18d40cd721d46fce4702cf1a943583cd41c03cf4 Gerrit-Change-Number: 82104 Gerrit-PatchSet: 1 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/mtlrvp: use different names for mtlrvp variants
by YH Lin (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Kapil Porwal, Paul Menzel, Subrata Banik. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82084?usp=email ) Change subject: soc/intel/mtlrvp: use different names for mtlrvp variants ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Verified with Intel MTLRVP. -- To view, visit https://review.coreboot.org/c/coreboot/+/82084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5292a0ffcd7524c55cd7aef37c2f59432b2af06a Gerrit-Change-Number: 82084 Gerrit-PatchSet: 5 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 17:02:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
by Federico Amedeo Izzo (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Felix Singer. Federico Amedeo Izzo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email ) Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1) ...................................................................... Patch Set 11: (31 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82010/comment/d8da15a6_31b67c93 : PS8, Line 47: VDT > VBT? Done https://review.coreboot.org/c/coreboot/+/82010/comment/2d100263_c87d5e64 : PS8, Line 49: vgabios blob (ID 8086,0406) > Shouldn't be needed if you use FSP GOP for video init. […] Done Commit Message: https://review.coreboot.org/c/coreboot/+/82010/comment/7f4fa2eb_10eb92db : PS10, Line 57: Patchset 5: Re-enabled dptf, added default options to Kconfig. : Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works : Pa > Doesn't hurt, and it's common practice in mailing lists commits. Acknowledged Patchset: PS11: Thank you for your reviews 😊 File src/mainboard/aoostar/wtr_r1/Kconfig: https://review.coreboot.org/c/coreboot/+/82010/comment/88435139_a7c555a3 : PS8, Line 28: config MAINBOARD_VENDOR : string : default "AOOSTAR" > Already set in vendor Kconfig, please drop Done File src/mainboard/aoostar/wtr_r1/bootblock.c: https://review.coreboot.org/c/coreboot/+/82010/comment/461d1085_43ba42fe : PS2, Line 1: > Remove blank line Done File src/mainboard/aoostar/wtr_r1/bootblock.c: https://review.coreboot.org/c/coreboot/+/82010/comment/1c7525dc_965fa615 : PS10, Line 20: ite_set_3vsbsw(GPIO_DEV, true); > Where do the Super I/O settings come from? […] These Super I/O settings are taken from a superiotool dump while running the vendor UEFI firmware. I tried to document them with the datasheet of a similar SIO chip, as I couldn't find the exact datasheet. The Super I/O functions are working, except for the power button from off. https://review.coreboot.org/c/coreboot/+/82010/comment/6182c868_f83a2f3e : PS10, Line 21: ite_delay_pwrgd3(GPIO_DEV); > There's very few boards that use this, is it actually needed? Hard to say without testing S3, though […] The equivalent Super I/O register was set from the vendor UEFI firmware (according to superiotool dump), so I replaced the reg_write with set_3vsbsw. File src/mainboard/aoostar/wtr_r1/devicetree.cb: https://review.coreboot.org/c/coreboot/+/82010/comment/83f3e638_6f284fe7 : PS2, Line 16: register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 : register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-C Port2 : register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # FPS connector : register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN : register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 : register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port2 : register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port3 : register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type A/ M.2 WLAN : register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth : : register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 : register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port2 : register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port3 : r > Please move into the devicetree below. Done https://review.coreboot.org/c/coreboot/+/82010/comment/7b07ddd0_5718b16c : PS2, Line 81: device ref ipu off end > Already disabled in chipset devicetree, remove. Done https://review.coreboot.org/c/coreboot/+/82010/comment/8af97df2_016de20c : PS2, Line 117: device ref heci1 on end > Enabled in chipset devicetree, remove. Done https://review.coreboot.org/c/coreboot/+/82010/comment/c7a34896_84d17b8d : PS2, Line 230: device ref p2sb on end > P2SB is hidden by the FSP, which is configured accordingly in chipset devicetree. Remove. Done https://review.coreboot.org/c/coreboot/+/82010/comment/95a4bb4c_11c08afa : PS2, Line 231: device ref emmc off end > Already disabled in chipset devicetree, remove. Done https://review.coreboot.org/c/coreboot/+/82010/comment/754624d3_eca409ee : PS2, Line 233: device ref ufs off end > Already disabled in chipset devicetree, remove. Done File src/mainboard/aoostar/wtr_r1/devicetree.cb: https://review.coreboot.org/c/coreboot/+/82010/comment/54e203a9_462c25b9 : PS8, Line 194: : [PchSerialIoIndexUART1] = PchSerialIoDisabled, : [PchSerialIoIndexUART2] = PchSerialIoDisabled, > Disabled equals zero. […] Done https://review.coreboot.org/c/coreboot/+/82010/comment/24ce101e_4bc1e9df : PS8, Line 201: : [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, : [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, : [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, > Disabled equals zero. […] Done https://review.coreboot.org/c/coreboot/+/82010/comment/a426c71a_4df4b975 : PS8, Line 205: : register "serial_io_gspi_cs_mode" = "{ : [PchSerialIoIndexGSPI0] = 0, : [PchSerialIoIndexGSPI1] = 0, : [PchSerialIoIndexGSPI2] = 0, : [PchSerialIoIndexGSPI3] = 0, : }" : register "serial_io_gspi_cs_state" = "{ : [PchSerialIoIndexGSPI0] = 0, : [PchSerialIoIndexGSPI1] = 0, : [PchSerialIoIndexGSPI2] = 0, : [PchSerialIoIndexGSPI3] = 0, : }" > Devicetree "register"s are default-initialised to zero, so this can be dropped. Done File src/mainboard/aoostar/wtr_r1/devicetree.cb: PS9: > Missing SPDX license identifier. Done https://review.coreboot.org/c/coreboot/+/82010/comment/67d279db_028e7421 : PS9, Line 11: # FSP configuration > Remove superfluous comment Done https://review.coreboot.org/c/coreboot/+/82010/comment/4934dae6_a5b55263 : PS9, Line 13: # Sagv Configuration > Same Done https://review.coreboot.org/c/coreboot/+/82010/comment/5aa183e5_83fc6ce8 : PS9, Line 16: # Enable DPTF > Same Done https://review.coreboot.org/c/coreboot/+/82010/comment/cdaef54f_d6d7c1bc : PS9, Line 21: # Intel Common SoC Config > Same Done https://review.coreboot.org/c/coreboot/+/82010/comment/f06f2534_be683027 : PS9, Line 74: register "usb2_ports[6]" = "USB2_PORT_EMPTY" > Not needed, remove. Done https://review.coreboot.org/c/coreboot/+/82010/comment/332cc47f_d91012b6 : PS9, Line 79: register "usb3_ports[2]" = "USB3_PORT_EMPTY" : register "usb3_ports[3]" = "USB3_PORT_EMPTY" : register "usb3_ports[4]" = "USB3_PORT_EMPTY" > Not needed, remove. Done https://review.coreboot.org/c/coreboot/+/82010/comment/62deb40b_df08426c : PS9, Line 85: register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)" # USB3/2 Type A upper > Move to tcss_xhci PCI device Done File src/mainboard/aoostar/wtr_r1/devicetree.cb: https://review.coreboot.org/c/coreboot/+/82010/comment/f68a1328_480fb5b8 : PS10, Line 67: register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C : register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # microSD card reader : register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # USB2 Type A upper : register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB2 Type A lower : register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A upper : register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A lower : register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN : : register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C : register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # microSD card reader : register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A lower : > Rewrite as: […] Done https://review.coreboot.org/c/coreboot/+/82010/comment/9b052812_7e451203 : PS10, Line 117: .clk_req = 2, > How were CLKSRC and CLKREQ values determined? These could be causing troubles with power management. they are educated guesses, unfortunately I don't have the schematics of this board. However if I remove these, the M.2 SSD and NICs stop working. https://review.coreboot.org/c/coreboot/+/82010/comment/fde8e9e4_44f80653 : PS10, Line 114: device ref pcie_rp3 on : register "pch_pcie_rp[PCH_RP(3)]" = "{ : .clk_src = 2, : .clk_req = 2, : .flags = PCIE_RP_CLK_REQ_DETECT, : }" : end : device ref pcie_rp7 on : register "pch_pcie_rp[PCH_RP(7)]" = "{ : .clk_src = 3, : .clk_req = 3, : .flags = PCIE_RP_CLK_REQ_DETECT, : }" : end : device ref pcie_rp9 on : register "pch_pcie_rp[PCH_RP(9)]" = "{ : .clk_src = 0, : .clk_req = 0, : .flags = PCIE_RP_CLK_REQ_DETECT, : }" : end : device ref pcie_rp10 on : register "pch_pcie_rp[PCH_RP(10)]" = "{ : .clk_src = 1, : .clk_req = 1, : .flags = PCIE_RP_CLK_REQ_DETECT, : }" : end > For accessible ports, add SMBIOS information with `smbios_slot_desc`. […] Done File src/mainboard/aoostar/wtr_r1/gpio.h: https://review.coreboot.org/c/coreboot/+/82010/comment/e8b2887c_a81b27fd : PS10, Line 207: _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PWRBTN# */ > Try this instead: `PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1)` […] Unfortunately none of these make the power button work. I left PWROK as it's equivalent to the configuration from intelp2m. I'm guessing a Super I/O issue, as in the schematics of the similar Odroid H4, the power button is handled by the Super I/O https://wiki.odroid.com/odroid-h4/start#odroid-h4_schematic_and_full_intel_… File src/mainboard/aoostar/wtr_r1/gpio.h: PS2: > Remove comments to GPIOs which are configured with PAD_NC. Done https://review.coreboot.org/c/coreboot/+/82010/comment/49b0ddd2_2b71c650 : PS2, Line 222: /* ------- GPIO Group PCIe vGPIO ------- */ > Remove the superfluous comments below. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 11 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 17:02:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/mtlrvp: use different names for mtlrvp variants
by YH Lin (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Kapil Porwal, Paul Menzel, Subrata Banik. Hello Angel Pons, Kapil Porwal, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82084?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: soc/intel/mtlrvp: use different names for mtlrvp variants ...................................................................... soc/intel/mtlrvp: use different names for mtlrvp variants This patch sets different names for different mtlrvp variants so they can be matched properly at runtime against unique frids (i.e. firmware read-only identifiers). BRANCH=firmware-rex-15709.B TEST=Verified boot functionality on intel/mtlrvp Change-Id: I5292a0ffcd7524c55cd7aef37c2f59432b2af06a Signed-off-by: YH Lin <yueherngl(a)google.com> --- M src/mainboard/intel/mtlrvp/Kconfig 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/82084/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/82084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5292a0ffcd7524c55cd7aef37c2f59432b2af06a Gerrit-Change-Number: 82084 Gerrit-PatchSet: 5 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/mtl: use different names per mtlrvp variants
by YH Lin (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Kapil Porwal, Paul Menzel, Subrata Banik. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82084?usp=email ) Change subject: soc/intel/mtl: use different names per mtlrvp variants ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82084/comment/0fb68d95_b00272fd : PS4, Line 7: soc/intel/mtl: > ``mb/intel/mtlrvp`` Done https://review.coreboot.org/c/coreboot/+/82084/comment/e20e166b_16ebadb8 : PS4, Line 7: per > nit: replace `per` with `for` Done https://review.coreboot.org/c/coreboot/+/82084/comment/7a24f513_4cb7a60b : PS4, Line 14: TEST=Verified boot functionality on google/rex. > Given that this change only affects `intel/mtlrvp`, I don't think testing on `google/rex` matters (i […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/82084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5292a0ffcd7524c55cd7aef37c2f59432b2af06a Gerrit-Change-Number: 82084 Gerrit-PatchSet: 4 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 17:02:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
by Krishna P Bhat D (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Appukuttan V K, Felix Held, Subrata Banik, Wonkyu Kim. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81661?usp=email ) Change subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Gerrit-Change-Number: 81661 Gerrit-PatchSet: 15 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Apr 2024 17:00:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
by Federico Amedeo Izzo (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Federico Amedeo Izzo, Felix Singer. Hello Angel Pons, Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82010?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Code-Review+1 by Felix Singer, Verified+1 by build bot (Jenkins) Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1) ...................................................................... mb/aoostar: Add AOOSTAR R1 (WTR_R1) AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4 SODIMM slot. It also comes with 2x 2.5Gb Intel NICs, Intel AX200 WiFi + BT and USB-C Alt-DP Power Delivery. Working: - Automatic FAN control (IT8613E SuperIO) - M.2 NVME slot - 2x SATA ports (Issue on 3.5" HDD, see below) - USB 2.0 ports - USB 3.0 ports - USB-C port with Alt-DP and PD - HDMI / DisplayPort ports - 2x 2.5Gb NICs - WiFi + BT - MicroSD card reader - ASPM (Unavailable on stock) - Linux (Arch Linux, kernel 6.8.7-arch1-1) UEFI booting with EDK2 - Windows 10 UEFI booting with EDK2 Broken: - Power button (OFF->ON broken, ON->OFF works) - 3.5" SATA HDDs (Detected only after reboot) Untested: - Internal audio - S3 My motivation for doing this port is enabling ASPM, as it makes a great difference on idle power consumption (from 8.4W to 5W measured from the wall). The last remaining annoyance of this port is the power button not working. I spent a few hours double checking the SuperIO registers but then I gave up. A workaround for this is to use the "ON after power loss" feature and reconnect the power cord to turn on the board. It's not a big problem for a NAS that will stay ON 24/7. Any hint on the power button or 3.5" HDD issue is welcome. VBT extracted from vendor UEFI firmware version 1AXFE 0.01 x64 (Build date and time 11/29/2023 10:57:44) Compiled with FSP GOP video initialization, using IFD descriptor and ME blob extracted from vendor UEFI firmware (see above). The board can be flashed externally using a 1.8V adapter, I used a CH341a modded for 3.3V I/O. Internal flashing works, as flash is not read/write protected. Patchset 5: Re-enabled dptf, added default options to Kconfig. Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works Patchset 8: Fixed microSD card reader Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Signed-off-by: Federico Amedeo Izzo <federico(a)izzo.pro> --- A src/mainboard/aoostar/Kconfig A src/mainboard/aoostar/Kconfig.name A src/mainboard/aoostar/wtr_r1/Kconfig A src/mainboard/aoostar/wtr_r1/Kconfig.name A src/mainboard/aoostar/wtr_r1/Makefile.mk A src/mainboard/aoostar/wtr_r1/board_info.txt A src/mainboard/aoostar/wtr_r1/bootblock.c A src/mainboard/aoostar/wtr_r1/data.vbt A src/mainboard/aoostar/wtr_r1/devicetree.cb A src/mainboard/aoostar/wtr_r1/dsdt.asl A src/mainboard/aoostar/wtr_r1/gpio.h A src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c 12 files changed, 724 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/82010/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 11 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for SPI RW
by Ashish Kumar Mishra (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Patrick Rudolph, Paul Menzel, Saurabh Mishra, Subrata Banik. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email ) Change subject: block/fast_spi: Use read32p/write32p for SPI RW ...................................................................... Patch Set 5: (3 comments) File src/soc/intel/common/block/fast_spi/fast_spi_flash.c: https://review.coreboot.org/c/coreboot/+/82079/comment/b9d6f896_dfbf38cb : PS2, Line 80: const uint8_t *byte_ptr = (const uint8_t *)data; : size_t bytes_to_copy; : union { : uint32_t full; : uint8_t bytes[4]; : } dword; : : for (size_t i = 0; i < len; i += 4) { : dword.full = 0; : : bytes_to_copy = (len - i < 4) ? len - i : 4; : for (size_t j = 0; j < bytes_to_copy; j++) : dword.bytes[j] = byte_ptr[i + j]; : : write32p(ctx->mmio_base + SPIBAR_FDATA(i >> 2), dword.full); : } > OK. Marking this as unresolved until the patch is actually updated. Done File src/soc/intel/common/block/fast_spi/fast_spi_flash.c: https://review.coreboot.org/c/coreboot/+/82079/comment/3373f537_8c4fd3e5 : PS4, Line 81: (len >> 2) > This optimisation can be done by the compiler. […] Done https://review.coreboot.org/c/coreboot/+/82079/comment/ac00e240_abdca429 : PS4, Line 85: (len & 3) > Same here, please use `len % 4` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 5 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 29 Apr 2024 16:59:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for SPI RW
by Ashish Kumar Mishra (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Ashish Kumar Mishra, Patrick Rudolph, Paul Menzel, Saurabh Mishra, Subrata Banik. Hello Patrick Rudolph, Saurabh Mishra, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82079?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+2 by Patrick Rudolph, Verified+1 by build bot (Jenkins) Change subject: block/fast_spi: Use read32p/write32p for SPI RW ...................................................................... block/fast_spi: Use read32p/write32p for SPI RW The current fast_spi code uses memcpy for rw. The SPI flash read/write has 4 byte limit, due to which the current 64 bit memcpy doesn't work. Hence update rw ops to use read32p/write32p. BUG=b:242829490 TEST=Build and boot mtl 64-bit and verified MRC cache working. Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/soc/intel/common/block/fast_spi/fast_spi_flash.c 1 file changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/82079/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 5 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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