coreboot-gerrit April 2024

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[L] Change in coreboot[main]: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
by Felix Singer (Code Review) 29 Apr '24

29 Apr '24

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[L] Change in coreboot[main]: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
by Felix Singer (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Angel Pons, Federico Amedeo Izzo. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email ) Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1) ...................................................................... Patch Set 10: Code-Review+1 (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82010/comment/5108ad87_162bc007 : PS10, Line 57: Patchset 5: Re-enabled dptf, added default options to Kconfig. : Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works : Pa It's not needed to document the changes of each patchset. Please remove. File src/mainboard/aoostar/wtr_r1/bootblock.c: https://review.coreboot.org/c/coreboot/+/82010/comment/505e5faf_b7d291bb : PS2, Line 1: > Remove blank line Done File src/mainboard/aoostar/wtr_r1/devicetree.cb: https://review.coreboot.org/c/coreboot/+/82010/comment/9398383e_4a118b0b : PS10, Line 67: register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C : register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # microSD card reader : register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # USB2 Type A upper : register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB2 Type A lower : register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A upper : register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A lower : register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN : : register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C : register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # microSD card reader : register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A lower : Rewrite as: ``` register "usb2_ports" = "{ [0] = USB2_PORT_TYPE_C(OC0), /* Type-C */ ... }" ``` https://review.coreboot.org/c/coreboot/+/82010/comment/a03c0a11_58f97814 : PS10, Line 114: device ref pcie_rp3 on : register "pch_pcie_rp[PCH_RP(3)]" = "{ : .clk_src = 2, : .clk_req = 2, : .flags = PCIE_RP_CLK_REQ_DETECT, : }" : end : device ref pcie_rp7 on : register "pch_pcie_rp[PCH_RP(7)]" = "{ : .clk_src = 3, : .clk_req = 3, : .flags = PCIE_RP_CLK_REQ_DETECT, : }" : end : device ref pcie_rp9 on : register "pch_pcie_rp[PCH_RP(9)]" = "{ : .clk_src = 0, : .clk_req = 0, : .flags = PCIE_RP_CLK_REQ_DETECT, : }" : end : device ref pcie_rp10 on : register "pch_pcie_rp[PCH_RP(10)]" = "{ : .clk_src = 1, : .clk_req = 1, : .flags = PCIE_RP_CLK_REQ_DETECT, : }" : end For accessible ports, add SMBIOS information with `smbios_slot_desc`. The tree provides several usage examples. For the other ports, add a short comment on how they are used. File src/mainboard/aoostar/wtr_r1/gpio.h: PS2: > Remove comments to GPIOs which are configured with PAD_NC. Done https://review.coreboot.org/c/coreboot/+/82010/comment/d4127db3_2736a9df : PS2, Line 222: /* ------- GPIO Group PCIe vGPIO ------- */ > Remove the superfluous comments below. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 10 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Comment-Date: Mon, 29 Apr 2024 14:06:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER
by Angel Pons (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu, Ziang Wang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81443?usp=email ) Change subject: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER ...................................................................... Patch Set 4: Code-Review+1 (5 comments) File src/soc/intel/xeon_sp/numa.c: https://review.coreboot.org/c/coreboot/+/81443/comment/7c758261_44b41e4f : PS4, Line 36: /* : * Rules/assumptions: : * 1. Each processor has a processor proximity domain regardless whether : * a processor has DIMM attached to it or not. : * 2. All system memory map elements are either from processor attached memory, : * or from CXL memory. Each CXL node info entry has a corresponding entry : * in system memory map elements. : * 3. Each CXL device may have multiple HDMs (Host-managed Device Memory). Each : * HDM has one and only one CXL node info entry. Each CXL node info entry : * represents a generic initiator proximity domain. : */ Would be good to expand this comment w.r.t. clusters. https://review.coreboot.org/c/coreboot/+/81443/comment/ff45fb3c_9178a713 : PS4, Line 58: continue; Add: `const uint8_t socket_id = hob->PlatformData.IIO_resource[socket].SocketID;` https://review.coreboot.org/c/coreboot/+/81443/comment/29dac3fc_22d57b46 : PS4, Line 60: pds.pds[i].socket_bitmap = 1 << hob->PlatformData.IIO_resource[socket].SocketID; Replace with: `pds.pds[i].socket_bitmap = 1 << socket_id;` https://review.coreboot.org/c/coreboot/+/81443/comment/26592dd8_350ecd44 : PS4, Line 68: pds.pds[i].socket_bitmap = 1 << hob->PlatformData.IIO_resource[socket].SocketID; Replace with: `pds.pds[i].socket_bitmap = 1 << socket_id;` https://review.coreboot.org/c/coreboot/+/81443/comment/6e1d6c43_bff7dbce : PS4, Line 70: pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds); : if (!pds.pds[i].distances) : die("%s %d out of memory.", __FILE__, __LINE__); : i++; This bit could be factored out into a helper function, but can be done in a follow-up. -- To view, visit https://review.coreboot.org/c/coreboot/+/81443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32558983780f302ff4893901540a90baebf47add Gerrit-Change-Number: 81443 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 13:41:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add fill_pd_distances
by Angel Pons (Code Review) 29 Apr '24

29 Apr '24

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add device to proximity domain map utils
by Angel Pons (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, Ziang Wang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81440?usp=email ) Change subject: soc/intel/xeon_sp: Add device to proximity domain map utils ...................................................................... Patch Set 6: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81440/comment/6de6c8eb_9323e62d : PS6, Line 18: SNC What does SNC mean? I would at least expand the acronym File src/soc/intel/xeon_sp/numa.c: https://review.coreboot.org/c/coreboot/+/81440/comment/ed054797_e85d0851 : PS6, Line 122: uint32_t Use `enum proximity_domain_type`. If it doesn't make sense (returned value is not a proximity domain **type**), then returning `PD_TYPE_MAX` in the error case is not correct. https://review.coreboot.org/c/coreboot/+/81440/comment/3b490871_62e1b984 : PS6, Line 130: return PD_TYPE_MAX; Would it be a good idea to log a warning/error when the pd couldn't be found? https://review.coreboot.org/c/coreboot/+/81440/comment/ef24c942_c288bf9a : PS6, Line 147: return PD_TYPE_MAX; Same here -- To view, visit https://review.coreboot.org/c/coreboot/+/81440?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd14a98823491ccfc38473e44a26dddfbbcaa7c0 Gerrit-Change-Number: 81440 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 13:31:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add SOC_INTEL_HAS_NUMA
by Angel Pons (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu, Ziang Wang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81439?usp=email ) Change subject: soc/intel/xeon_sp: Add SOC_INTEL_HAS_NUMA ...................................................................... Patch Set 5: Code-Review+1 (2 comments) File src/soc/intel/xeon_sp/numa.c: https://review.coreboot.org/c/coreboot/+/81439/comment/0d60223b_e8a134c7 : PS5, Line 75: #if CONFIG(SOC_INTEL_HAS_CXL) Is this preprocessor needed? Unless something causes a compilation error on the non-CXL case, I would prefer adapting the check above: ``` /* If there are no CXL nodes, we are done */ if (!CONFIG(SOC_INTEL_HAS_CXL) || num_cxlnodes == 0) return; ``` File src/soc/intel/xeon_sp/uncore_acpi.c: https://review.coreboot.org/c/coreboot/+/81439/comment/c174b6a8_4c865ec9 : PS5, Line 578: if (CONFIG(SOC_INTEL_HAS_NUMA)) { Is there any Xeon-SP platform that is not NUMA? -- To view, visit https://review.coreboot.org/c/coreboot/+/81439?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84f07c16e24e441a885144df8c805f1310acae29 Gerrit-Change-Number: 81439 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 13:26:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Move domain resources adding to their creation
by Angel Pons (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81435?usp=email ) Change subject: soc/intel/xeon_sp: Move domain resources adding to their creation ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81435/comment/f48babda_e6bea240 : PS3, Line 9: Domain > Sorry, the whole thing was my idea. Some thoughts: […] I'm not sure if I follow. Why would one report resources outside of `read_resources`? Also, if the HOB pointer doesn't change, wouldn't it be enough to cache it in a helper function? ``` template<typename fsp_hob_type> fsp_hob_type *get_cached_fsp_hob(void) { static fsp_hob_type *hob_ptr = NULL; if (hob_ptr) return hob_ptr; hob_ptr = get_fsp_hob_real(); if (hob_ptr) return hob_ptr; die("%s: hob_ptr is NULL!", __func__); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/81435?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba58dc9ac1d2e7d07004ee2bb0cc76b273d37e99 Gerrit-Change-Number: 81435 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 13:21:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
by Felix Singer (Code Review) 29 Apr '24

29 Apr '24

1 0

[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Angel Pons (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 58: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 58 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 13:13:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/var/wugtrio: Add initialize USB port 0
by Wentao Qin (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu. Wentao Qin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email ) Change subject: mb/google/corsola/var/wugtrio: Add initialize USB port 0 ...................................................................... Patch Set 11: (1 comment) File src/soc/mediatek/common/usb.c: https://review.coreboot.org/c/coreboot/+/82089/comment/5f8f6823_b91950a1 : PS9, Line 162: > That's a good idea, thank you Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 11 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 13:06:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2024