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Change subject: mb/google/brox: Add 20K pulldown to GPP_D14
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82096/comment/7b4461fe_47355436 :
PS1, Line 16: HW validates that power usage is lower
> HW team? […]
Done
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Hello Karthik Ramasubramanian, Nick Vaccaro, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82096?usp=email
to look at the new patch set (#2).
Change subject: mb/google/brox: Add 20K pulldown to GPP_D14
......................................................................
mb/google/brox: Add 20K pulldown to GPP_D14
GPP_D14 is floating when ISH is not being used and wasting power. Add
pulldown to prevent this from happening.
BUG=b:336654954
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
make sure OS boots up
HW team validated that power usage is 20 mW lower
Change-Id: I4e19e98fa31022ece66a47402a2a4461b430ef70
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/gpio.c
M src/mainboard/google/brox/variants/brox/fw_config.c
2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/82096/2
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Change subject: payloads/iPXE: add TRUST_CMD switch
......................................................................
Patch Set 7:
(1 comment)
File payloads/external/iPXE/Makefile:
https://review.coreboot.org/c/coreboot/+/79684/comment/686b6247_55807242 :
PS6, Line 56: sed 's|.*IMAGE_TRUST_CMD|#define IMAGE_TRUST_CMD|g' "$(project_dir)/src/config/general.h" > "$(project_dir)/src/config/general.h.tmp"
> Fixed [here](https://review.coreboot. […]
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Change subject: soc/intel/xeon_sp/spr: Improves CPU codes
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82097/comment/746d1227_b11d6825 :
PS1, Line 9: 1. xeonsp_acpi_create_madt_lapics is removed due to ACPI common
: code can handle this well with ACPI_COMMON_MADT_LAPIC set.
:
: 2. Improvement in log prints, comments and the file include list.
I would make two commits, one for each thing in this list.
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Change subject: soc/intel/xeon_sp: Add get_cxl_mode
......................................................................
Patch Set 8: Code-Review+2
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Change subject: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/lenovo/m920q/romstage.c:
https://review.coreboot.org/c/coreboot/+/80609/comment/a4266c21_089a62f9 :
PS6, Line 33: /* Rcomp target values for CFL-S, DDR4 and 2 DIMMs per channel */
> Hmm indeed the docs don't have the values for CFL-S SODIMM 1DPC... […]
Ah, I remember a bit more: this number is read ODT, and it gets trained by MRC anyway. So, as long as it boots, I'd say it's fine.
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Change subject: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE
......................................................................
Patch Set 3: Code-Review+2
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(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP
......................................................................
soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP
In a server platform many silicon specific register lock operations
are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option
to make sure the codes could be used out-of-box to build products.
Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081
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---
M src/soc/intel/xeon_sp/lockdown.c
1 file changed, 4 insertions(+), 0 deletions(-)
Approvals:
Patrick Rudolph: Looks good to me, approved
build bot (Jenkins): Verified
Angel Pons: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c
index 9e25920..a3d17b4 100644
--- a/src/soc/intel/xeon_sp/lockdown.c
+++ b/src/soc/intel/xeon_sp/lockdown.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <intelblocks/cfg.h>
#include <intelblocks/lpc_lib.h>
#include <intelpch/lockdown.h>
#include <soc/lockdown.h>
@@ -20,6 +21,9 @@
void soc_lockdown_config(int chipset_lockdown)
{
+ if (chipset_lockdown == CHIPSET_LOCKDOWN_FSP)
+ return;
+
lpc_lockdown_config();
pmc_lockdown_config();
sata_lockdown_config(chipset_lockdown);
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Change subject: Makefile.mk: Align romstage to page directory pointer requirements
......................................................................
Patch Set 1: Code-Review+2
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