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Change subject: mb/amd/birman: add function to update MPIO config in devicetree
......................................................................
mb/amd/birman: add function to update MPIO config in devicetree
Phoenix 2 has less PCIe lanes than Phoenix, so some of the lane end
numbers need to be adjusted to take that into account. When the Kconfig
options WLAN01 or WWAN01 are set, either the WLAN or the WWAN card uses
both PICe lanes that are available for those two devices, so the MPIO
descriptor information the devicetree needs to be updated accordingly
and the bridge to the PCIe port that doesn't have any lane left needs to
be disabled. Two other PCIe devices will be disabled when the
corresponding Kconfig options ENABLE_EVAL_CARD and DISABLE_DT_M2 have
the value that results in the device being disabled via some GPIO driven
by the EC. Since the code has paths and names specific to the MPIO stub,
include the update_devicetree_phoenix_opensil.c file depending on
whether CONFIG_SOC_AMD_OPENSIL_STUB is selected and not depending on
whether CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL is selected.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I23c14cc03980ea1e39f7e5aec551b975c237e487
---
M src/mainboard/amd/birman/Makefile.mk
M src/mainboard/amd/birman/mainboard.c
A src/mainboard/amd/birman/update_devicetree.h
A src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c
4 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/82106/2
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Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81332?usp=email )
Change subject: soc/intel/meteorlake: Update Touch Controller UPD params
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81332/comment/397551a7_ff124d18 :
PS4, Line 7: UDP
> typo? UPD
yes. typo. thx
File src/soc/intel/meteorlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/81332/comment/5fadc123_51cf43b0 :
PS2, Line 639: s_cfg->ThcAssignment[0] = THC_NONE;
> Using `#if` and `#endif` should be a last-resort measure as it prevents code from being build-tested […]
We have run into several cases that the design/support is added to new SOC, and some existing ones are removed. With if (CONFIG(build flag))/else statement, it requires both conditional code block to be present to compile. For instance, one of MTL example is GPMR. there is no PCH in MTL and GPMR moved to IOC. And there is no longer DMI interface. Therefore, the existing code for DMI such as PID_DMI no longer valid.
Intel SOC common code src/soc/intel/common/block/gpmr/gpmr.c
Initially:
uint32_t gpmr_read32(uint16_t offset)
{
return pcr_read32(PID_DMI, offset);
}
Currently:
uint32_t gpmr_read32(uint16_t offset)
{
if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) -> used in MTL and later.
return ioc_reg_write32(offset, val); -> no such function in SOC prior to MTL.
else
return pcr_write32(PID_DMI, offset, val); -> No such PCR access and DMI PID in MTL and later.
}
But need to be changed to:
uint32_t gpmr_read32(uint16_t offset)
{
#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)
return ioc_reg_write32(offset, val);
#else
return pcr_write32(PID_DMI, offset, val);
#endif
}
The same thing applies to Intel driver code and the SOC code but have difference in various SKUs. One example I can think of is MTL UFS support.
Another hesitation to me of using if (CONFIG(build flag))/else statement is that it produces always true or false conditional logic. It does not make sense to me from the code maintenance aspect even though the complier will optimal it. I understand that using #if/#else/#endif makes code not structural but it does job of adding and removing design changes going forward, while leaving the older projects more intact. But, I do agree that #if/#else/#end should be avoided in other cases.
Going back to the initial comment on these ThCAssignment assigned to THC_NONE. These is merely initialized to not use and have thc_configuration to determine the value, along with is_devfn_enabled().
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Change subject: soc/intel/meteorlake: Update Touch Controller UPD params
......................................................................
soc/intel/meteorlake: Update Touch Controller UPD params
The UPDs ThcAssignment, ThcMode, and ThcWakeOnTouch are specified via
THC driver in the device tree. Therefore, SOC needs to get the driver
config. A weak function drivers_intel_touch_config() is added such that
the mainboard can implement the function to provide the config from the
device tree. The CONFIG_SOC_INTEL_TOUCH is needed to add THC support for
Meteorlake SOC.
BUG=b:307775082
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I19edbcad705e889166d7d340b2caa74ab3bf15a1
---
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/meteorlake/chip.c
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/fsp_params.c
4 files changed, 92 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/81332/5
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82106?usp=email )
Change subject: mb/amd/birman: add function to update MPIO config in devicetree
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
i've verified that the mainboard init is run before the soc init on some other board
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Change subject: mb/google/brya/var/xol: Add EC_IN_RW_OD config into early_gpio_table
......................................................................
Patch Set 2: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82113?usp=email )
Change subject: soc/intel/cmn/graphics: Make DDI-A 4 lanes configurable
......................................................................
soc/intel/cmn/graphics: Make DDI-A 4 lanes configurable
As described in Intel document 336464 (8th gen S series datasheet volume
1), the CPU's 4 eDP lanes can be bifurcated, so that DDI-A (eDP) ends up
with 2 lanes, and DDI-E (DP, typically used for VGA) has the remaining 2
lanes. This lets mainboards provide a VGA output without sacrificing one
of the main 4-lane DDIs. Newer platforms seem to be lacking this.
However, the way this is structured in coreboot does not allow boards to
choose whether bifurcation should be enabled. Most boards in the tree do
not use DDI-E (it doesn't exist on mobile platforms), but there are some
boards (e.g. hp/280_g2) that use DDI-E and a DP-to-VGA converter chip to
provide a VGA output.
Replace `SOC_INTEL_CONFIGURE_DDI_A_4_LANES` with two new Kconfig options
to allow boards to decide. Use `SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION` to
specify whether a platform supports DDI-A bifurcation at all (do nothing
otherwise, maintaining the original code's behaviour). If bifurcation is
supported, the `SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION` is used to clear
or set the `DDI_A_4_LANES` bit in the `DDI_BUF_CTL_A` register.
Change-Id: I516538db77509209d371f3f49c920476e06b052f
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82113
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/common/block/graphics/Kconfig
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/skylake/Kconfig
4 files changed, 31 insertions(+), 10 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 7548e46..3aa06f4 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -64,7 +64,7 @@
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET
- select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
+ select SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig
index b5776b0..eaa429e 100644
--- a/src/soc/intel/common/block/graphics/Kconfig
+++ b/src/soc/intel/common/block/graphics/Kconfig
@@ -8,10 +8,20 @@
if SOC_INTEL_COMMON_BLOCK_GRAPHICS
-config SOC_INTEL_CONFIGURE_DDI_A_4_LANES
+config SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION
bool
help
- Selected by platforms that require DDI-A bifurcation setup.
+ Skylake, Kaby Lake and Coffee Lake desktop CPUs support eDP
+ bifurcation, i.e. 4 eDP lanes get split between DDI-A (eDP)
+ and DDI-E (DP, used for VGA). Selected from SoC Kconfig, if
+ applicable.
+
+config SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION
+ bool
+ depends on SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION
+ help
+ Selected by mainboards that use DDI-E, which is most commonly
+ used to drive a DP-to-VGA adapter to provide a VGA connector.
config SOC_INTEL_DISABLE_IGD
bool "Disable Integrated GFX Controller (0:2:0)"
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index c38b30f..1a0d64d 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -124,6 +124,21 @@
return graphics_get_framebuffer_address() && get_external_display_status();
}
+static void configure_ddi_a_bifurcation(void)
+{
+ u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
+ /* Only program if the buffer is not enabled yet. */
+ if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE)
+ return;
+
+ if (CONFIG(SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION))
+ ddi_buf_ctl &= ~DDI_A_4_LANES;
+ else
+ ddi_buf_ctl |= DDI_A_4_LANES;
+
+ graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
+}
+
static void gma_init(struct device *const dev)
{
intel_gma_init_igd_opregion();
@@ -135,12 +150,8 @@
if (!CONFIG(RUN_FSP_GOP))
graphics_soc_panel_init(dev);
- if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) {
- const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
- /* Only program if the buffer is not enabled yet. */
- if (!(ddi_buf_ctl & DDI_BUF_CTL_ENABLE))
- graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl | DDI_A_4_LANES);
- }
+ if (CONFIG(SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION) && !acpi_is_wakeup_s3())
+ configure_ddi_a_bifurcation();
/*
* GFX PEIM module inside FSP binary is taking care of graphics
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 0d38804..3ec84ab 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -62,7 +62,7 @@
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
- select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
+ select SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER
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Change subject: drivers/intel/touch: Add driver for Intel Touch Controller and Devices
......................................................................
drivers/intel/touch: Add driver for Intel Touch Controller and Devices
This driver is for Intel Touch Host controller (THC). THC supports a
host controller interface to the touch IC for high bandwidth touch data
transfer from SPI based touch ICs. This driver supports WACOM, ELAN,
and generic touch sensor devices.
ref: Meteor Lake UH type4 EDS vol1 640228
This driver generates the following ACPI objects:
- _DSM
- _CRS
- Power resource with _STA, _ON, and _OFF
- _RST
BUG=b:307775082
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I52dfcd187c92141cb8fc47f4143b90d243439d4e
---
A src/drivers/intel/touch/Kconfig
A src/drivers/intel/touch/Makefile.mk
A src/drivers/intel/touch/chip.h
A src/drivers/intel/touch/elan.h
A src/drivers/intel/touch/touch.c
A src/drivers/intel/touch/wacom.h
6 files changed, 974 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/81331/6
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82112?usp=email )
Change subject: mb/hp/280_g2: Fix comment in `gma-mainboard.ads`
......................................................................
mb/hp/280_g2: Fix comment in `gma-mainboard.ads`
The DVI connector on this board is DVI-D (digital only), not DVI-I.
Change-Id: I74c1257efb67cfdff2ae04a42c163dd320c850a4
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82112
Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/mainboard/hp/280_g2/gma-mainboard.ads
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Nico Huber: Looks good to me, approved
Nicholas Chin: Looks good to me, approved
diff --git a/src/mainboard/hp/280_g2/gma-mainboard.ads b/src/mainboard/hp/280_g2/gma-mainboard.ads
index 735fe26..0628211 100644
--- a/src/mainboard/hp/280_g2/gma-mainboard.ads
+++ b/src/mainboard/hp/280_g2/gma-mainboard.ads
@@ -9,7 +9,7 @@
private package GMA.Mainboard is
ports : constant Port_List :=
- (HDMI3, -- DVI-I
+ (HDMI3, -- DVI-D
eDP, -- VGA
others => Disabled);
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I74c1257efb67cfdff2ae04a42c163dd320c850a4
Gerrit-Change-Number: 82112
Gerrit-PatchSet: 2
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
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Gerrit-MessageType: merged