coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/corsola/var/wugtrio: Add initialize USB port 0
by Yu-Ping Wu (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Wentao Qin, Xuxin Xiong, Yang Wu, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email ) Change subject: mb/google/corsola/var/wugtrio: Add initialize USB port 0 ...................................................................... Patch Set 11: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82089/comment/de0221f0_4c7681fc : PS11, Line 7: /var/wugtrio Actually, this patch uses fw_config to decide the initialization, and isn't directly related to a particular variant (wugtrio). Therefore please take `/var/wugtrio` out. https://review.coreboot.org/c/coreboot/+/82089/comment/a3537da3_d1d17c89 : PS11, Line 10: option 27th in fwconfig bit 27 in fw_config -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 11 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 00:34:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Tune I2C5 timing parameters
by SH Kim (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82100?usp=email ) Change subject: mb/google/brya/var/xol: Tune I2C5 timing parameters ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82100/comment/317db5c5_04db4866 : PS1, Line 9: touchpad spec > Sorry, it's I2C bus spec. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82100?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I386b2765410fd10b8cd711f54478fb52428de5a3 Gerrit-Change-Number: 82100 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 30 Apr 2024 00:17:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/rex: Add Intel Touch for controller 1 for Rex
by Cliff Huang (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Subrata Banik, Tarun. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81333?usp=email ) Change subject: mb/google/rex: Add Intel Touch for controller 1 for Rex ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81333/comment/cc9a75ad_ddb3123c : PS4, Line 13: Major rework is required for Rex P1 and P2. > Why? What is the problem with the current implementation? THC was not part of feature in Rex. The THC GPIO pads are not routed the touch device and some of these THC GPIO pads is configured for different devices. In EVT, we changes some of pad routing such that we only need to stuff/un-stuff registers to switch to THC device connection. https://review.coreboot.org/c/coreboot/+/81333/comment/50d2cbc1_d83a067f : PS4, Line 9: GPIO pad configuration for THC1 according to CBI fw_config. : ACPI entries in SSDT for ELAN according to CBI fw_config. : : THC0 must be enabled when THC1 is enabled. : Major rework is required for Rex P1 and P2. minor Rework is needed for : EVT. Rex with THC rework won't be able to support UWB and FPCMU. : The touch device must be converted to SPI interface. : When THC is enabled and the THC rework is in place, the UWB and FPMCU : are not supported and need to be disable from the CBI. : THC0 will also be provided with ACPI entries when THC1 is enabled. : THC1 GPIO pins will be configured for THC according to the CBI : TOUCHSCREEN fw_config field. : The resistor on the THC-SPI MISO pin should be 100 Ohm. > For me this reads very heard, as you break the line after every sentence, and often it’s also just a […] ok. let me make changes. File src/mainboard/google/rex/variants/rex0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/81333/comment/97906fa8_faa333d5 : PS2, Line 33: THC NOTE for P1 and P2:reworked > Please add a space after the colon. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id89b5b46d67b90491410d3d08c1a3ae9549b4da5 Gerrit-Change-Number: 81333 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Henry Barnor <hbarnor(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 00:17:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Tune I2C5 timing parameters
by SH Kim (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82100?usp=email ) Change subject: mb/google/brya/var/xol: Tune I2C5 timing parameters ...................................................................... Patch Set 2: (4 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/82100/comment/4ef23873_ee26eac7 : PS1, Line 7: Update I2C5 timing parameter > Maybe more specific: Tune I2C5 timings for touchpad spec It's just for I2C bus spec, I think we don't need specify for general tuning. https://review.coreboot.org/c/coreboot/+/82100/comment/041c6060_cff1f5ef : PS1, Line 9: touchpad spec > Please add the name and revision. Sorry, it's I2C bus spec. https://review.coreboot.org/c/coreboot/+/82100/comment/d6006c55_4c8fc55b : PS1, Line 10: > What were the values before, and what does the spec require? Done File src/mainboard/google/brya/variants/xol/overridetree.cb: https://review.coreboot.org/c/coreboot/+/82100/comment/37db5291_78c43a0a : PS1, Line 136: .data_hold_time_ns = 50, > What is the default? Got further tuning value. Thanks for the review. -- To view, visit https://review.coreboot.org/c/coreboot/+/82100?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I386b2765410fd10b8cd711f54478fb52428de5a3 Gerrit-Change-Number: 82100 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 30 Apr 2024 00:17:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/rex: Add Intel Touch for controller 1 for Rex
by Cliff Huang (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Cliff Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81333?usp=email to look at the new patch set (#6). Change subject: mb/google/rex: Add Intel Touch for controller 1 for Rex ...................................................................... mb/google/rex: Add Intel Touch for controller 1 for Rex This patch enables THC1 support for Rex according to the corresponding CBI fw_config. The change includes the GPIO pad configuration and adding ACPI entries in SSDT for ELAN touch device. THC0 is also enabled when THC1 is enabled due to the design constraint. NOTE for Rework info: - Major rework is required when using THC1 with Rex P1 and P2. Minor rework is needed for EVT. - Rex with THC rework won't be able to support UWB and FPCMU as the original board does. And their CBI fw_config shouled be disabled to avoid conflict with THC1. - The resistor on the THC1 THC-SPI MISO pin should be 100 Ohm. NOTE for downstream device: - The ELAN touch device interface must be converted from I2C to SPI prior to use. BUG=b:307775082 TEST=set CBI TOUCHSREEN fw_config to TOUCHSCREEN_THC, FP fw_config to FP_ABSENT, and UWB fw_config to UWB_ABSENT. boot Rex to OS and run lspci to check THC device and check that THC device driver initialization successfully. /sys/class/hidraw/hidraw0/device/input/ should have several inputs enumerated. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Id89b5b46d67b90491410d3d08c1a3ae9549b4da5 --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/variants/rex0/fw_config.c M src/mainboard/google/rex/variants/rex0/overridetree.cb 3 files changed, 163 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/81333/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id89b5b46d67b90491410d3d08c1a3ae9549b4da5 Gerrit-Change-Number: 81333 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Henry Barnor <hbarnor(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google/rex: Add Intel Touch for controller 1 for Rex
by Cliff Huang (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Cliff Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81333?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rex: Add Intel Touch for controller 1 for Rex ...................................................................... mb/google/rex: Add Intel Touch for controller 1 for Rex This patch enables THC1 support for Rex according to the corresponding CBI fw_config. The change includes the GPIO pad configuration and adding ACPI entries in SSDT for ELAN touch device. THC0 is also enabled when THC1 is enabled due to the design constraint. NOTE for Rework info: - Major rework is required when using THC1 with Rex P1 and P2. Minor rework is needed for EVT. - Rex with THC rework won't be able to support UWB and FPCMU as the original board does. And their CBI fw_config shouled be disabled to avoid conflict with THC1. - The resistor on the THC1 THC-SPI MISO pin should be 100 Ohm. NOTE for downstream device: - The ELAN touch device interface must be converted from I2C to SPI prior to use. BUG=b:307775082 TEST=set CBI TOUCHSREEN fw_config to TOUCHSCREEN_THC, FP fw_config to FP_ABSENT, and UWB fw_config to UWB_ABSENT. boot Rex to OS and run lspci to check THC device and check that THC device driver initialization successfully. /sys/class/hidraw/hidraw0/device/input/ should have several inputs enumerated. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Id89b5b46d67b90491410d3d08c1a3ae9549b4da5 --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/variants/rex0/fw_config.c M src/mainboard/google/rex/variants/rex0/overridetree.cb 3 files changed, 163 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/81333/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id89b5b46d67b90491410d3d08c1a3ae9549b4da5 Gerrit-Change-Number: 81333 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Henry Barnor <hbarnor(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Angel Pons (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Alicja Michalska, Felix Singer, Maxim, Michał Kopeć, Michał Żygowski, Nicholas Chin, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80853?usp=email ) Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... Patch Set 8: (7 comments) File src/mainboard/erying/tgl/Kconfig: https://review.coreboot.org/c/coreboot/+/80853/comment/0f8e964a_d5dddbdd : PS8, Line 24: default "erying-tgl" > "INTEL HM570". […] Hmmm, I would use `Polestar G613 Pro` then File src/mainboard/erying/tgl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80853/comment/4a39aefb_9909bda6 : PS8, Line 25: register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" > I'm not sure if ASPM works properly when CLKREQ# isn't set up. […] It should be fine. File src/mainboard/erying/tgl/ramstage.c: https://review.coreboot.org/c/coreboot/+/80853/comment/0a766542_55ed655f : PS8, Line 23: params->CpuPcieRpPeerToPeerMode[0] = 1; > AFAIK, that's needed for PCI-E Resizable BAR (ReBAR), which is pretty much mandatory for modern GPUs […] The only boards that set this are `msi/ms7d25` and `msi/ms7e06`, with no explanation as to why https://review.coreboot.org/c/coreboot/+/80853/comment/f9d3d0c7_6b3aeacb : PS8, Line 27: params->CpuPcieRpTransmitterHalfSwing[0] = 0; > It was configured the same way in vendor's firmware. […] Interesting https://review.coreboot.org/c/coreboot/+/80853/comment/f5e67070_8674bc49 : PS8, Line 41: params->PchDmiAspmCtrl = 0; > Yes. If I enable DMI ASPM, M.2 slot connected through the chipset goes haywire. […] Whew, that's bad. I'm starting to suspect that high-speed I/O on this board is simply not well designed. https://review.coreboot.org/c/coreboot/+/80853/comment/87ea8175_42d04d56 : PS8, Line 68: : params->CpuPcieRpFunctionSwap = 1; : params->PcieRpFunctionSwap = 0; > It was configured the same way in vendor's firmware. It shouldn't matter, though. coreboot can handle function swapping. https://review.coreboot.org/c/coreboot/+/80853/comment/69b029ba_95b0d40a : PS8, Line 18: : // PEG0 - Gen4 NVME : params->CpuPcieRpSlotImplemented[0] = 1; : params->CpuPcieRpAdvancedErrorReporting[0] = 1; : params->CpuPcieRpMaxPayload[0] = 2; : params->CpuPcieRpPeerToPeerMode[0] = 1; : params->CpuPcieRpPtmEnabled[0] = 1; : params->CpuPcieRpLtrEnable[0] = 1; : params->CpuPcieRpPmSci[0] = 1; : params->CpuPcieRpTransmitterHalfSwing[0] = 0; : : // PEG1 - PCI-E x16 : params->CpuPcieRpSlotImplemented[1] = 1; : params->CpuPcieRpAdvancedErrorReporting[1] = 1; : params->CpuPcieRpMaxPayload[1] = 2; : params->CpuPcieRpPeerToPeerMode[1] = 1; : params->CpuPcieRpPtmEnabled[1] = 1; : params->CpuPcieRpLtrEnable[1] = 1; : params->CpuPcieRpPmSci[1] = 1; : params->CpuPcieRpTransmitterHalfSwing[1] = 0; : : // Power management - ASPM is broken even on vendor FW : params->PchLegacyIoLowLatency = 1; : params->PchDmiAspmCtrl = 0; : : // PCH RootPorts : params->PcieRpMaxPayload[4] = 2; // M.2 Gen3 : params->PcieRpPmSci[4] = 1; : // params->PcieRpEnableCpm[4] = 0; : // params->PcieRpL1Substates[4] = 0; : // params->PcieRpAspm[4] = 0; : : params->PcieRpMaxPayload[8] = 1; : params->PcieRpPmSci[8] = 1;// M.2 NGFF : // params->PcieRpEnableCpm[8] = 0; : // params->PcieRpL1Substates[8] = 0; : // params->PcieRpAspm[8] = 0; : : params->PcieRpMaxPayload[10] = 1; // RTL8111 NIC : params->PcieRpPmSci[10] = 1; : // params->PcieRpEnableCpm[10] = 0; : // params->PcieRpL1Substates[10] = 0; : // params->PcieRpAspm[10] = 0; : : params->PcieRpMaxPayload[11] = 1; // PCI-E x1 Gen3 : params->PcieRpPmSci[11] = 1; : // params->PcieRpEnableCpm[11] = 0; : // params->PcieRpL1Substates[11] = 0; : // params->PcieRpAspm[11] = 0; : : // FSP settings : params->CpuPcieRpFunctionSwap = 1; : params->PcieRpFunctionSwap = 0; : params->ITbtPcieTunnelingForUsb4 = 0; : params->PchUsbOverCurrentEnable = 0; : params->RC1pFreqEnable = 1; : params->PavpEnable = 1; : params->CdynmaxClampEnable = 0; : params->PchEspiHostC10ReportEnable = 1; > I know, I wanted to keep devicetree as "clean" as possible, so people who aren't very familiar with […] I'm confused because most boards I've seen don't need to configure so many FSP settings. As for devicetree settings, if they exist then please use them. -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 8 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 23:56:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Alicja Michalska (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Angel Pons, Felix Singer, Maxim, Michał Kopeć, Michał Żygowski, Nicholas Chin, Paul Menzel. Alicja Michalska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80853?usp=email ) Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... Patch Set 8: (32 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80853/comment/ed2187e7_d7b23892 : PS8, Line 23: PCI-E passtrough > I thought passthrough requires VT-d? Just mention both: […] Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/6d94200d_26b1a7a7 : PS8, Line 23: broken > "Broken" as in not enabled in vendor firmware? Broken, as it either causes VM to hang, or the entire host 😊 https://review.coreboot.org/c/coreboot/+/80853/comment/d584e28c_1af202e9 : PS8, Line 30: - One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet) > If you enable all USB ports, does it work? Haven't tried that, but that will be trivial to fix. I simply didn't have 2.0 header next to COM port populated while mapping them, so I just need to boot stock firmware, attach a USB device and map it in devicetree. https://review.coreboot.org/c/coreboot/+/80853/comment/22e2c461_7b94b80d : PS8, Line 31: - Automatic fan control (IT8613E can't read CPU_TIN at the moment) > That likely requires enabling PECI on the Super I/O. That was my suspicion as well, but it doesn't seem to be the case. https://review.coreboot.org/c/coreboot/+/80853/comment/e4cfd725_678f2e65 : PS8, Line 33: Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as > I'd suggest adding `--ifd -i bios` to avoid interfering with the ME. Agreed, good idea 😊 https://review.coreboot.org/c/coreboot/+/80853/comment/cb2feedc_e62b3045 : PS8, Line 37: consumtion > typo: consum**p**tion Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/ca508e97_9af8ac22 : PS8, Line 39: Likewise, I can't wrap my head around PCI-E AERs I'm getting if I boot : the machine without `pcie_aspm=off` parameter: : - BadTLP : - BadDLLP : - Timeout : - Rollover > On which PCIe root ports? […] RP5, PEG0, PEG1. Yes, it's enabled in stock firmware: https://github.com/ellyq/erying-logs/blob/main/tgl/stock-uefi-settings/pcie… https://review.coreboot.org/c/coreboot/+/80853/comment/c95fce47_7039dd8d : PS8, Line 49: Starting to suspect Intel's FSP might be buggy, as I haven't had those > I know for a fact that FSP has bugs, but I don't think this is what's causing these issues. Acknowledged File src/mainboard/erying/tgl/Kconfig: https://review.coreboot.org/c/coreboot/+/80853/comment/ececc8c9_3043e0b1 : PS8, Line 24: default "erying-tgl" > What does SMBIOS on stock firmware say? "INTEL HM570". I wanted to avoid using that SMBIOS name, as it's obviously not manufactured by intel. Vendor-provided firmware is very janky. https://review.coreboot.org/c/coreboot/+/80853/comment/b1ded9ad_3d378eb1 : PS8, Line 29: config PCIEXP_ASPM : default n : : config PCIEXP_CLK_PM : default n : : config PCIEXP_L1_SUB_STATE : default n > I'm not sure if FSP honours these. […] It does enable/disable ASPM based on Kconfig setting. I left it there explicitly until I get ASPM working to make sure it won't be selected by default. File src/mainboard/erying/tgl/Kconfig.name: https://review.coreboot.org/c/coreboot/+/80853/comment/415b546b_ee9eb759 : PS8, Line 4: bool "erying-tgl" > This is a very generic name, given the specific model listed in the commit message (`Polestar G613 P […] There are no mITX versions of TGL platform, so it would be safe to leave it as-it. Starting with ADL they started releasing mATX and mITX boards (mATX with IT8613E SIO and mITX with Nuvoton), so those will need to be split into variants. I know for a fact that MrChromebox had bought a MTL mITX board and is working on coreboot port 😜 TGL was self-explanatory, although I guess full vendor name looks a bit nicer. File src/mainboard/erying/tgl/bootblock.c: https://review.coreboot.org/c/coreboot/+/80853/comment/8bb3d312_80af3aba : PS8, Line 13: ite_reg_write(GPIO_DEV, 0x29, 0xc1); /* 3VSB - RAM loses power in S3 anyway */ > There's an `ite_set_3vsbsw()` function that sets a different register (0x2a). […] Just noticed this myself yesterday, will definitely give it a try. File src/mainboard/erying/tgl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80853/comment/84f67744_10be377f : PS7, Line 125: device ref pch_espi on > I would just use one `genX_dec` register to forward 0xa00 .. […] Agreed. Will need to test this, haven't yet had the time to do so. File src/mainboard/erying/tgl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80853/comment/5cfcddd8_099965e1 : PS8, Line 19: register "HybridStorageMode" = "1" > Are you sure this is needed? It shouldn't matter with "H" SKU. I've tested Optane 800P and 900P (U.2) with it being on and off - doesn't seem to make any difference. https://review.coreboot.org/c/coreboot/+/80853/comment/7e373f08_a11d6be9 : PS8, Line 51: OC0 > `OC_SKIP` as it seems you don't use OC mapping. Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/f5ceb129_a378c5ad : PS8, Line 75: : register "SataPortsEnable[0]" = "1" : register "SataPortsEnable[1]" = "1" : register "SataPortsEnable[2]" = "1" : register "SataPortsEnable[3]" = "1" : register "SataSalpSupport" = "1" : register "SataPortsDevSlp[0]" = "1" : register "SataPortsDevSlp[1]" = "1" : register "SataPortsDevSlp[2]" = "1" : register "SataPortsDevSlp[3]" = "1" > nit: You can make this a bit less verbose: […] Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/6d707982_436b7e57 : PS8, Line 90: register "PcieRpAdvancedErrorReporting[4]" = "1" > You can disable AER here. Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/a603817d_7c83a6c5 : PS8, Line 118: register "SerialIoUartMode[PchSerialIoIndexUART0]" = "PchSerialIoPci" > Is this actually used? Kconfig selects `DRIVERS_UART_8250IO` which is primarily used for Super I/O U […] Probably not :P https://review.coreboot.org/c/coreboot/+/80853/comment/0260700b_056d6e23 : PS8, Line 144: register "TMPIN1.mode" = "THERMAL_DIODE" : register "TMPIN2.mode" = "THERMAL_DIODE" : : register "FAN2.mode" = "FAN_SMART_AUTOMATIC" # CPU_FAN : register "FAN3.mode" = "FAN_SMART_AUTOMATIC" # SYS_FAN : : register "FAN2.smart.tmpin" = "1" : register "FAN2.smart.tmp_off" = "35" : register "FAN2.smart.tmp_start" = "42" : register "FAN2.smart.tmp_full" = "72" : register "FAN2.smart.tmp_delta" = "2" : register "FAN2.smart.pwm_start" = "26" : register "FAN2.smart.slope" = "24" : : register "FAN3.smart.tmpin" = "1" : register "FAN3.smart.tmp_off" = "35" : register "FAN3.smart.tmp_start" = "42" : register "FAN3.smart.tmp_full" = "72" : register "FAN3.smart.tmp_delta" = "2" : register "FAN3.smart.pwm_start" = "26" : register "FAN3.smart.slope" = "24" > Indent with one extra tab? Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/0058a4ae_4ebe67f9 : PS8, Line 171: irq 0x29 = 0xc0 : irq 0x2c = 0x41 : irq 0x2d = 0x02 > You're setting some of these in C code already Acknowledged File src/mainboard/erying/tgl/dsdt.asl: https://review.coreboot.org/c/coreboot/+/80853/comment/f1a809d9_b79d1563 : PS8, Line 27: Scope (\_SB.PCI0.LPCB) : { : } > Dead code? I left it there in case I needed to work on ACPI for EC, seems like I forgot to remove it. Thanks! File src/mainboard/erying/tgl/ramstage.c: https://review.coreboot.org/c/coreboot/+/80853/comment/c9e96dbe_7fdd7ff3 : PS8, Line 21: params->CpuPcieRpAdvancedErrorReporting[0] = 1; > You can disable AER here. Sure, but then AERs will still happen - we simply won't know about it. https://review.coreboot.org/c/coreboot/+/80853/comment/ab536501_d6c87d30 : PS8, Line 23: params->CpuPcieRpPeerToPeerMode[0] = 1; > Why? AFAIK, that's needed for PCI-E Resizable BAR (ReBAR), which is pretty much mandatory for modern GPUs (and yes, I know, it's not necessary to set it on M.2 slot). https://review.coreboot.org/c/coreboot/+/80853/comment/3d07717d_726d176a : PS8, Line 27: params->CpuPcieRpTransmitterHalfSwing[0] = 0; > Why? It was configured the same way in vendor's firmware. I'm trying to leave as much settings on-par with stock as possible for now. https://review.coreboot.org/c/coreboot/+/80853/comment/976a67ac_2ae6144e : PS8, Line 40: params->PchLegacyIoLowLatency = 1; > Why? Done https://review.coreboot.org/c/coreboot/+/80853/comment/528cb060_6f4d6618 : PS8, Line 41: params->PchDmiAspmCtrl = 0; > Why? That's DMI ASPM, it doesn't affect PCIe ASPM. Yes. If I enable DMI ASPM, M.2 slot connected through the chipset goes haywire. Lots of errors, crashes while trying to boot into Linux, and speed drops to 200MB/s. Disabling DMI ASPM was necessary to make the platform stable (same with PchLegacyIoLowLatency). https://review.coreboot.org/c/coreboot/+/80853/comment/e36b1f7f_d2b92a16 : PS8, Line 44: params->PcieRpMaxPayload[4] = 2; // M.2 Gen3 > Why set this at all? […] Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/3db89783_346ba1f8 : PS8, Line 68: : params->CpuPcieRpFunctionSwap = 1; : params->PcieRpFunctionSwap = 0; > Why? It was configured the same way in vendor's firmware. https://review.coreboot.org/c/coreboot/+/80853/comment/958b0e43_3a436775 : PS8, Line 71: params->ITbtPcieTunnelingForUsb4 = 0; > Does this do anything? Now that I think about it, probably no. This board has USB4 controller enabled and I had a lot of issues with USB3 completely freezing the platform so I've been trying various settings. https://review.coreboot.org/c/coreboot/+/80853/comment/9cae9b3c_3ff8f34e : PS8, Line 72: params->PchUsbOverCurrentEnable = 0; > Why? Just don't assign overcurrent pins to USB ports in the devicetree. It was left there for debugging and I forgot about it. I had platform freezes related to USB3 controller and couldn't figure out why for a while. https://review.coreboot.org/c/coreboot/+/80853/comment/71fce86c_68cb0738 : PS8, Line 74: params->PavpEnable = 1; > Should be set via a Kconfig already. Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/27120067_5f25bb81 : PS8, Line 18: : // PEG0 - Gen4 NVME : params->CpuPcieRpSlotImplemented[0] = 1; : params->CpuPcieRpAdvancedErrorReporting[0] = 1; : params->CpuPcieRpMaxPayload[0] = 2; : params->CpuPcieRpPeerToPeerMode[0] = 1; : params->CpuPcieRpPtmEnabled[0] = 1; : params->CpuPcieRpLtrEnable[0] = 1; : params->CpuPcieRpPmSci[0] = 1; : params->CpuPcieRpTransmitterHalfSwing[0] = 0; : : // PEG1 - PCI-E x16 : params->CpuPcieRpSlotImplemented[1] = 1; : params->CpuPcieRpAdvancedErrorReporting[1] = 1; : params->CpuPcieRpMaxPayload[1] = 2; : params->CpuPcieRpPeerToPeerMode[1] = 1; : params->CpuPcieRpPtmEnabled[1] = 1; : params->CpuPcieRpLtrEnable[1] = 1; : params->CpuPcieRpPmSci[1] = 1; : params->CpuPcieRpTransmitterHalfSwing[1] = 0; : : // Power management - ASPM is broken even on vendor FW : params->PchLegacyIoLowLatency = 1; : params->PchDmiAspmCtrl = 0; : : // PCH RootPorts : params->PcieRpMaxPayload[4] = 2; // M.2 Gen3 : params->PcieRpPmSci[4] = 1; : // params->PcieRpEnableCpm[4] = 0; : // params->PcieRpL1Substates[4] = 0; : // params->PcieRpAspm[4] = 0; : : params->PcieRpMaxPayload[8] = 1; : params->PcieRpPmSci[8] = 1;// M.2 NGFF : // params->PcieRpEnableCpm[8] = 0; : // params->PcieRpL1Substates[8] = 0; : // params->PcieRpAspm[8] = 0; : : params->PcieRpMaxPayload[10] = 1; // RTL8111 NIC : params->PcieRpPmSci[10] = 1; : // params->PcieRpEnableCpm[10] = 0; : // params->PcieRpL1Substates[10] = 0; : // params->PcieRpAspm[10] = 0; : : params->PcieRpMaxPayload[11] = 1; // PCI-E x1 Gen3 : params->PcieRpPmSci[11] = 1; : // params->PcieRpEnableCpm[11] = 0; : // params->PcieRpL1Substates[11] = 0; : // params->PcieRpAspm[11] = 0; : : // FSP settings : params->CpuPcieRpFunctionSwap = 1; : params->PcieRpFunctionSwap = 0; : params->ITbtPcieTunnelingForUsb4 = 0; : params->PchUsbOverCurrentEnable = 0; : params->RC1pFreqEnable = 1; : params->PavpEnable = 1; : params->CdynmaxClampEnable = 0; : params->PchEspiHostC10ReportEnable = 1; > A bunch of these should be set by default in FSP already, and others can be configured in the device […] I know, I wanted to keep devicetree as "clean" as possible, so people who aren't very familiar with the project can open it and modify settings (such as Power Limits) without feeling intimidated. -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 8 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 23:39:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Maxim <max.senia.poliak(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: vc/intel/fsp/mtl: Add Intel Touch Controller UPD in Partial Header
by Angel Pons (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Cliff Huang, Paul Menzel, Shaunak Saha, srinivas.kulkarni(a)intel.com. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81674?usp=email ) Change subject: vc/intel/fsp/mtl: Add Intel Touch Controller UPD in Partial Header ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81674?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a18b83fbb2d7760bd58027a4203919489b01580 Gerrit-Change-Number: 81674 Gerrit-PatchSet: 5 Gerrit-Owner: srinivas.kulkarni(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: srinivas.kulkarni(a)intel.com Gerrit-Comment-Date: Mon, 29 Apr 2024 22:59:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: [WIP] soc/amd/phoenix/chip.h: add TOODs
by Felix Held (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82107?usp=email ) Change subject: [WIP] soc/amd/phoenix/chip.h: add TOODs ...................................................................... [WIP] soc/amd/phoenix/chip.h: add TOODs Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3e820f3132cac517dbcbd0e8da1064f666ed1229 --- M src/soc/amd/phoenix/chip.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/82107/1 diff --git a/src/soc/amd/phoenix/chip.h b/src/soc/amd/phoenix/chip.h index e3cadc2..3d166ec 100644 --- a/src/soc/amd/phoenix/chip.h +++ b/src/soc/amd/phoenix/chip.h @@ -108,6 +108,9 @@ #if CONFIG(PLATFORM_USES_FSP2_0) uint8_t usb_phy_custom; struct usb_phy_config usb_phy; +#else + /* TODO: add USB PHY config */ + /* TODO: add DDI config */ #endif }; -- To view, visit https://review.coreboot.org/c/coreboot/+/82107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e820f3132cac517dbcbd0e8da1064f666ed1229 Gerrit-Change-Number: 82107 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2024