coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: mb/google/brox:Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
by Krishna P Bhat D (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Karthik Ramasubramanian, Krishna P Bhat D, Shelley Chen. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82078?usp=email ) Change subject: mb/google/brox:Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/82078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f62943f87d8fb6eb494c0aca3ef08c33cd05ffd Gerrit-Change-Number: 82078 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Pavan Holla <pholla(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 05:31:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: libpayload: Save EAX and EBX for multiboot payloads
by Subrata Banik (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Arthur Heymans, Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82040?usp=email ) Change subject: libpayload: Save EAX and EBX for multiboot payloads ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82040/comment/8a21bbf2_c74f728c : PS1, Line 7: for > only for? Acknowledged File payloads/libpayload/arch/x86/main.c: https://review.coreboot.org/c/coreboot/+/82040/comment/0481b633_fef40618 : PS1, Line 33: #if CONFIG(LP_MULTIBOOT) : unsigned long loader_eax; /**< The value of EAX passed from the loader */ : unsigned long loader_ebx; /**< The value of EBX passed from the loader */ : #endif > As those are not referenced in this file, maybe move them to multiboot. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/82040?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I98c2cd00206ee48eb0fc67edd9533032bcf3e5eb Gerrit-Change-Number: 82040 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 30 Apr 2024 05:23:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: libpayload: Save EAX and EBX only for multiboot payloads
by Subrata Banik (Code Review) 30 Apr '24

30 Apr '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82111?usp=email ) Change subject: libpayload: Save EAX and EBX only for multiboot payloads ...................................................................... libpayload: Save EAX and EBX only for multiboot payloads When CONFIG_LP_MULTIBOOT is enabled, save the values of EAX and EBX passed from the bootloader. This information can be useful for multiboot payloads feature alone. Change-Id: I98c2cd00206ee48eb0fc67edd9533032bcf3e5eb Change-Id: Ibdb4e42073b90870661767e6168742a3ace714a9 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M payloads/libpayload/arch/x86/head.S M payloads/libpayload/arch/x86/main.c M payloads/libpayload/arch/x86/multiboot.c 3 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/82111/1 diff --git a/payloads/libpayload/arch/x86/head.S b/payloads/libpayload/arch/x86/head.S index 1e0e4a0..2bac700 100644 --- a/payloads/libpayload/arch/x86/head.S +++ b/payloads/libpayload/arch/x86/head.S @@ -63,9 +63,11 @@ /* No interrupts, please. */ cli +#if CONFIG(LP_MULTIBOOT) /* Store EAX and EBX */ movl %eax, loader_eax movl %ebx, loader_ebx +#endif /* save pointer to coreboot tables */ movl 4(%esp), %eax diff --git a/payloads/libpayload/arch/x86/main.c b/payloads/libpayload/arch/x86/main.c index 288f474..a7c6b01 100644 --- a/payloads/libpayload/arch/x86/main.c +++ b/payloads/libpayload/arch/x86/main.c @@ -30,9 +30,6 @@ #include <libpayload.h> #include <arch/apic.h> -unsigned long loader_eax; /**< The value of EAX passed from the loader */ -unsigned long loader_ebx; /**< The value of EBX passed from the loader */ - int main_argc; /**< The argc value to pass to main() */ /** The argv value to pass to main() */ diff --git a/payloads/libpayload/arch/x86/multiboot.c b/payloads/libpayload/arch/x86/multiboot.c index 26dc4f8..ed78862 100644 --- a/payloads/libpayload/arch/x86/multiboot.c +++ b/payloads/libpayload/arch/x86/multiboot.c @@ -30,8 +30,8 @@ #include <libpayload.h> #include <multiboot_tables.h> -extern unsigned long loader_eax; -extern unsigned long loader_ebx; +unsigned long loader_eax; /* The value of EAX passed from the loader */ +unsigned long loader_ebx; /* The value of EBX passed from the loader */ static int mb_add_memrange(struct sysinfo_t *info, unsigned long long base, unsigned long long size, unsigned int type) -- To view, visit https://review.coreboot.org/c/coreboot/+/82111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdb4e42073b90870661767e6168742a3ace714a9 Gerrit-Change-Number: 82111 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: libpayload: Save EAX and EBX for multiboot payloads
by Subrata Banik (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82040?usp=email ) Change subject: libpayload: Save EAX and EBX for multiboot payloads ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82040/comment/48a6ef23_a72f648d : PS1, Line 12: > Why are they removed for non-multiboot things? As you may have noticed, this CL is already V+1 after removing those variables from `non-multiboot`. This indicates that those variables are not being used in the case of `non-multiboot`. As a result, do we require any further justification to remove those unnecessary variables for `non-multiboot`? -- To view, visit https://review.coreboot.org/c/coreboot/+/82040?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I98c2cd00206ee48eb0fc67edd9533032bcf3e5eb Gerrit-Change-Number: 82040 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 30 Apr 2024 05:03:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Determine TBT controllers exist by VID/DID
by Subrata Banik (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kane Chen, Kane Chen, Kapil Porwal, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81842?usp=email ) Change subject: soc/intel/meteorlake: Determine TBT controllers exist by VID/DID ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I54f2ea99cd1ec73dd0b71a6ba738aa927b0ae80f Gerrit-Change-Number: 81842 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 04:56:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Default to 64-bits for FSP 2.4
by Subrata Banik (Code Review) 30 Apr '24

30 Apr '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80323?usp=email ) ( 33 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/intel/fsp2_0: Default to 64-bits for FSP 2.4 ...................................................................... drivers/intel/fsp2_0: Default to 64-bits for FSP 2.4 Sets`PLATFORM_USES_FSP2_X86_32' to `n' by default if FSP 2.4 is enabled as 64-bits FSP should be norm moving forward. BUG=b:329034258 TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec98 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80323 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Reviewed-by: Usha P <usha.p(a)intel.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/Kconfig 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Usha P: Looks good to me, approved Krishna P Bhat D: Looks good to me, approved Subrata Banik: Looks good to me, approved Ashish Kumar Mishra: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 754b04a..9ea1526 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -55,10 +55,12 @@ config PLATFORM_USES_FSP2_X86_32 bool + default n if PLATFORM_USES_FSP2_4 default y help - The FSP 2.0 runs in x86_32 protected mode. - Once there's a x86_64 FSP this needs to default to n. + Specify if the FSP binaries are 32-bits (yes) or 64-bits + (no). By default, 64-bit should be used starting with FSP + specification 2.4 config HAVE_INTEL_FSP_REPO bool -- To view, visit https://review.coreboot.org/c/coreboot/+/80323?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec98 Gerrit-Change-Number: 80323 Gerrit-PatchSet: 35 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Add dedicated caller function for ap procedure ...
by Subrata Banik (Code Review) 30 Apr '24

30 Apr '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81663?usp=email ) ( 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/intel/fsp2_0: Add dedicated caller function for ap procedure calls ...................................................................... drivers/intel/fsp2_0: Add dedicated caller function for ap procedure calls Add FSP 2 Multi Processor Platform Initialization module a function indirection to ensure that efi_ap_procedure functions are called with the appropriate C calling convention. BUG=b:329034258 TEST=Verified both x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: I64e65b2941207375d5e27c84aa26061e7e72a7f6 Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81663 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c 1 file changed, 32 insertions(+), 5 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index a891ba0..41fccd6 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -12,6 +12,18 @@ #define BSP_CPU_SLOT 0 +struct efi_ap_procedure_caller_params { + efi_ap_procedure procedure; + void *argument; +}; + +static void efi_ap_procedure_caller(void *arg) +{ + struct efi_ap_procedure_caller_params *params = + (struct efi_ap_procedure_caller_params *)arg; + params->procedure(params->argument); +} + efi_return_status_t mp_get_number_of_processors(efi_uintn_t *number_of_processors, efi_uintn_t *number_of_enabled_processors) { @@ -58,14 +70,19 @@ efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure, bool run_serial, efi_uintn_t timeout_usec, void *argument) { + struct efi_ap_procedure_caller_params params = { + .procedure = procedure, + .argument = argument + }; + if (!cpu_info()) return FSP_DEVICE_ERROR; if (procedure == NULL) return FSP_INVALID_PARAMETER; - if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, !run_serial) != - CB_SUCCESS) { + if (mp_run_on_all_aps((void *)efi_ap_procedure_caller, &params, + timeout_usec, !run_serial) != CB_SUCCESS) { printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); return FSP_NOT_STARTED; } @@ -76,6 +93,11 @@ efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure, efi_uintn_t timeout_usec, void *argument) { + struct efi_ap_procedure_caller_params params = { + .procedure = procedure, + .argument = argument + }; + if (!cpu_info()) return FSP_DEVICE_ERROR; @@ -99,8 +121,8 @@ * due to lack of acquiring a spin lock while accessing common data structure in * multiprocessor environment. */ - if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, false) != - CB_SUCCESS) { + if (mp_run_on_all_aps((void *)efi_ap_procedure_caller, + &params, timeout_usec, false) != CB_SUCCESS) { printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); return FSP_NOT_STARTED; } @@ -111,6 +133,11 @@ efi_return_status_t mp_startup_this_ap(efi_ap_procedure procedure, efi_uintn_t processor_number, efi_uintn_t timeout_usec, void *argument) { + struct efi_ap_procedure_caller_params params = { + .procedure = procedure, + .argument = argument + }; + if (!cpu_info()) return FSP_DEVICE_ERROR; @@ -123,7 +150,7 @@ if (procedure == NULL) return FSP_INVALID_PARAMETER; - if (mp_run_on_aps((void *)procedure, argument, + if (mp_run_on_aps((void *)efi_ap_procedure_caller, &params, processor_number, timeout_usec) != CB_SUCCESS) { printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); return FSP_NOT_STARTED; -- To view, visit https://review.coreboot.org/c/coreboot/+/81663?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64e65b2941207375d5e27c84aa26061e7e72a7f6 Gerrit-Change-Number: 81663 Gerrit-PatchSet: 13 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Remove x64-specific assertion from fsp_header
by Subrata Banik (Code Review) 30 Apr '24

30 Apr '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81662?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/intel/fsp2_0: Remove x64-specific assertion from fsp_header ...................................................................... drivers/intel/fsp2_0: Remove x64-specific assertion from fsp_header Same fsp_header struture is being used for x64 and x32 modes and hence dropping the x64 assertion. BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: I6013af342670e6377a3fe7641d7d9b52c9b6f57c Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81662 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Usha P <usha.p(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/intel/fsp2_0/include/fsp/info_header.h 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified Usha P: Looks good to me, approved Subrata Banik: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index f495822..a553436 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -12,7 +12,6 @@ #define FSP_HDR_ATTRIB_FSPS 3 #define FSP_IMAGE_ID_LENGTH 8 -#if CONFIG(PLATFORM_USES_FSP2_X86_32) struct fsp_header { uint32_t signature; //FSPH uint32_t header_length; @@ -40,9 +39,6 @@ uint32_t fsp_multi_phase_mem_init_entry_offset; uint32_t res5; } __packed; -#else -#error You need to implement this struct for x86_64 FSP -#endif enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); -- To view, visit https://review.coreboot.org/c/coreboot/+/81662?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6013af342670e6377a3fe7641d7d9b52c9b6f57c Gerrit-Change-Number: 81662 Gerrit-PatchSet: 10 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
by Subrata Banik (Code Review) 30 Apr '24

30 Apr '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81661?usp=email ) Change subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned ...................................................................... drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned - Stack alignment: 1. FSP functions must be called with the stack 16-bytes aligned in x86_64 mode.This is already setup properly with the default value of the `mpreferred-stack-boundary' compiler option (4). 2. The FSP heap buffer supplied by coreboot through the `StackBase' UPD must be 16-bytes aligned. This alignment is consistent for both x86_64 and x86_32 modes to simplify the implementation. BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81661 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Krishna P Bhat D: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 31ae213..7e9676c 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -34,7 +34,7 @@ /* Leave for the SoC/Mainboard to implement if necessary. */ } -static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); +static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(16); /* * Helper function to store the MRC cache version into CBMEM -- To view, visit https://review.coreboot.org/c/coreboot/+/81661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Gerrit-Change-Number: 81661 Gerrit-PatchSet: 16 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for SPI RW
by Subrata Banik (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Arthur Heymans, Ashish Kumar Mishra, Patrick Rudolph, Paul Menzel, Saurabh Mishra. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: block/fast_spi: Use read32p/write32p for SPI RW ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82079/comment/c4c83880_413f7d34 : PS5, Line 14: TEST=Build and boot mtl 64-bit and verified MRC cache working. can you please highlight if you have tested this CL with both existing 32-bit and future 64-bit platform as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 5 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 30 Apr 2024 04:45:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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