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Change subject: mb/google/nissa: Create a riven variant
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/82132/comment/edc032e0_3b9915ca :
PS2, Line 445: BOARD_GOOGLE_RIVEN
is this Trulo based on Nirul based ?
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Change subject: soc/intel/xeon_sp/spr: Improve CPU codes
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/spr/cpu.c:
https://review.coreboot.org/c/coreboot/+/82097/comment/8192a6ac_54b06e76 :
PS2, Line 273: BIOS_WARNING
> Why is it an improvement? Shouldn't there be always microcodes in CBFS? Does it even boot without?
This is a point raised during review by Paul. If without CBFS ucode, the CPU will still boot using the default provisioned one, but it is highly recommended to do BIOS (CBFS) carried ucode update since it could contains SoC vendor delivered fixes (e.g. security, et al).
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Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa: Create a riven variant
......................................................................
mb/google/nissa: Create a riven variant
Create the riven variant of nissa reference board by copying the
template files to a new directory named for the variant.
The riven variant is a twinlake platform.
BUG=b:337169542
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_RIVEN
Change-Id: I1be2346d87c891cc0e5fbda094e1f6e0dd60df1b
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/riven/include/variant/ec.h
A src/mainboard/google/brya/variants/riven/include/variant/gpio.h
A src/mainboard/google/brya/variants/riven/memory/Makefile.mk
A src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/riven/overridetree.cb
8 files changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/82132/2
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David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82132?usp=email )
Change subject: mb/google/nissa: Create a riven variant
......................................................................
mb/google/nissa: Create a riven variant
Create the riven variant of nissa reference board by copying the
template files to a new directory named for the variant.
The riven variant is a twinlake platform.
BUG=b:337169542
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_RIVEN
Change-Id: I1be2346d87c891cc0e5fbda094e1f6e0dd60df1b
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/riven/include/variant/ec.h
A src/mainboard/google/brya/variants/riven/include/variant/gpio.h
A src/mainboard/google/brya/variants/riven/memory/Makefile.mk
A src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/riven/overridetree.cb
8 files changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/82132/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 1565f13..594a5a5 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -442,6 +442,10 @@
select GOOGLE_DSM_PARAM_FILE_NAME if VPD
select SOC_INTEL_COMMON_BLOCK_IPU
+config BOARD_GOOGLE_RIVEN
+ select BOARD_GOOGLE_BASEBOARD_NISSA
+ select SOC_INTEL_TWINLAKE
+
config BOARD_GOOGLE_SKOLAS
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENERIC_NAU8315
@@ -644,6 +648,7 @@
default 0x0 if BOARD_GOOGLE_QUANDISO
default 0x1 if BOARD_GOOGLE_REDRIX
default 0x3 if BOARD_GOOGLE_REDRIX4ES
+ default 0x0 if BOARD_GOOGLE_RIVEN
default 0x1 if BOARD_GOOGLE_SKOLAS
default 0x1 if BOARD_GOOGLE_SKOLAS4ES
default 0x1 if BOARD_GOOGLE_TAEKO
@@ -732,6 +737,7 @@
default "Quandiso" if BOARD_GOOGLE_QUANDISO
default "Redrix" if BOARD_GOOGLE_REDRIX
default "Redrix4ES" if BOARD_GOOGLE_REDRIX4ES
+ default "Riven" if BOARD_GOOGLE_RIVEN
default "Skolas" if BOARD_GOOGLE_SKOLAS
default "Skolas4ES" if BOARD_GOOGLE_SKOLAS4ES
default "Sundance" if BOARD_GOOGLE_SUNDANCE
@@ -795,6 +801,7 @@
default "quandiso" if BOARD_GOOGLE_QUANDISO
default "redrix" if BOARD_GOOGLE_REDRIX
default "redrix4es" if BOARD_GOOGLE_REDRIX4ES
+ default "riven" if BOARD_GOOGLE_RIVEN
default "skolas" if BOARD_GOOGLE_SKOLAS
default "skolas4es" if BOARD_GOOGLE_SKOLAS4ES
default "sundance" if BOARD_GOOGLE_SUNDANCE
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index fe8fcc9..52f2c9f 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -122,6 +122,9 @@
config BOARD_GOOGLE_REDRIX4ES
bool "-> Redrix4ES"
+config BOARD_GOOGLE_RIVEN
+ bool "-> Riven"
+
config BOARD_GOOGLE_SKOLAS
bool "-> Skolas"
diff --git a/src/mainboard/google/brya/variants/riven/include/variant/ec.h b/src/mainboard/google/brya/variants/riven/include/variant/ec.h
new file mode 100644
index 0000000..7a2a6ff
--- /dev/null
+++ b/src/mainboard/google/brya/variants/riven/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/riven/include/variant/gpio.h b/src/mainboard/google/brya/variants/riven/include/variant/gpio.h
new file mode 100644
index 0000000..c4fe342
--- /dev/null
+++ b/src/mainboard/google/brya/variants/riven/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/riven/memory/Makefile.mk b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk
new file mode 100644
index 0000000..eace2e4
--- /dev/null
+++ b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder
diff --git a/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt
new file mode 100644
index 0000000..fa24790
--- /dev/null
+++ b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name ID to assign
diff --git a/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
new file mode 100644
index 0000000..2499005
--- /dev/null
+++ b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
new file mode 100644
index 0000000..4f2c04a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+ device domain 0 on
+ end
+
+end
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Change subject: soc/intel/xeon_sp/spr: Improve CPU codes
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/spr/cpu.c:
https://review.coreboot.org/c/coreboot/+/82097/comment/7c899ff3_2f9178dc :
PS2, Line 273: BIOS_WARNING
Why is it an improvement? Shouldn't there be always microcodes in CBFS? Does it even boot without?
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Change subject: soc/intel/xeon_sp: Remove xeonsp_acpi_create_madt_lapics
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/xeon_sp: Remove xeonsp_acpi_create_madt_lapics
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82110/comment/9dc5efb5_1b630bda :
PS1, Line 9: Remove
Remove unused xeonsp_acpi_create_madt_lapics.
https://review.coreboot.org/c/coreboot/+/82110/comment/25c63f77_399afdc3 :
PS1, Line 10: code
No explanation required, since you just drop unused code.
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Change subject: soc/intel/mtlrvp: use different names for mtlrvp variants
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Do you see any abnormal reboot issue w/ this CL due to crash in BT stack after booting to OS.
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Hello Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Code-Review+1 by Arthur Heymans, Verified+1 by build bot (Jenkins)
Change subject: libpayload: Save EAX and EBX only for multiboot payloads
......................................................................
libpayload: Save EAX and EBX only for multiboot payloads
When CONFIG_LP_MULTIBOOT is enabled, save the values of EAX and EBX
passed from the bootloader. This information can be useful for
multiboot payloads feature alone.
Change-Id: I98c2cd00206ee48eb0fc67edd9533032bcf3e5eb
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M payloads/libpayload/arch/x86/head.S
M payloads/libpayload/arch/x86/main.c
M payloads/libpayload/arch/x86/multiboot.c
3 files changed, 4 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/82040/2
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Change subject: common/block/tcss: Add config for PDC<->PMC mux configuration
......................................................................
Set Ready For Review
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