coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

1 participants
3292 discussions

[M] Change in coreboot[main]: mb/google/brya/var/pujjoga: Add GPIO table
by Leo Chou (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik. Leo Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82044?usp=email ) Change subject: mb/google/brya/var/pujjoga: Add GPIO table ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/82044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f633cf99f56d5f855015de805e16c1205c9bc99 Gerrit-Change-Number: 82044 Gerrit-PatchSet: 3 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 07:29:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/pujjoga: Generate SPD ID for 5 supported memory p...
by Roger Wang (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82135?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/pujjoga: Generate SPD ID for 5 supported memory parts ...................................................................... mb/google/nissa/var/pujjoga: Generate SPD ID for 5 supported memory parts Add pujjoga supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 2. Hynix H9JCNNNBK3MLYR-N6E, H58G56BK7BX068 3. Micron MT62F1G32D2DS-026 WT:B BUG=b:337990338 TEST=Use part_id_gen to generate related settings Change-Id: I39d44fd278474a7375ad1d2d904d14b9463ba86d Signed-off-by: roger2.wang <roger2.wang(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk M src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt 3 files changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/82135/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82135?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39d44fd278474a7375ad1d2d904d14b9463ba86d Gerrit-Change-Number: 82135 Gerrit-PatchSet: 2 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/pujjoga: Generate SPD ID for 4 supported memory p...
by Roger Wang (Code Review) 30 Apr '24

30 Apr '24

Roger Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82135?usp=email ) Change subject: mb/google/nissa/var/pujjoga: Generate SPD ID for 4 supported memory parts ...................................................................... mb/google/nissa/var/pujjoga: Generate SPD ID for 4 supported memory parts Add pujjoga supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 2. Hynix H9JCNNNBK3MLYR-N6E, H58G56BK7BX068 3. Micron MT62F1G32D2DS-026 WT:B BUG=b:337990338 TEST=Use part_id_gen to generate related settings Change-Id: I39d44fd278474a7375ad1d2d904d14b9463ba86d Signed-off-by: roger2.wang <roger2.wang(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk M src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt 3 files changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/82135/1 diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk index eace2e4..c6e0a1c 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk @@ -1,5 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjoga/memory src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = H58G56BK7BX068, K3KL8L80CM-MGCT, MT62F1G32D2DS-026 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 2(0b0010) Parts = K3KL6L60GM-MGCT diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt index fa24790..adec69c 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt @@ -1 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjoga/memory src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt + DRAM Part Name ID to assign +H58G56BK7BX068 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3KL6L60GM-MGCT 2 (0010) +K3KL8L80CM-MGCT 0 (0000) +MT62F1G32D2DS-026 WT:B 0 (0000) diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt index 2499005..b962c72 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt @@ -9,3 +9,8 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +H58G56BK7BX068 +H9JCNNNBK3MLYR-N6E +K3KL6L60GM-MGCT +K3KL8L80CM-MGCT +MT62F1G32D2DS-026 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/82135?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39d44fd278474a7375ad1d2d904d14b9463ba86d Gerrit-Change-Number: 82135 Gerrit-PatchSet: 1 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add _OSC ASL generation utils for IIO stacks
by Shuo Liu (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82034?usp=email ) Change subject: soc/intel/xeon_sp: Add _OSC ASL generation utils for IIO stacks ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: I tentatively made https://review.coreboot.org/c/coreboot/+/82133 to close some opens (e.g. name managements, arg counts, et al). Look forward to your review :) -- To view, visit https://review.coreboot.org/c/coreboot/+/82034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd3bfa2428725fe593754436d5ed75a3a11b4cdc Gerrit-Change-Number: 82034 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 07:13:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: common/block/tcss: Add config for PDC<->PMC mux configuration
by Deepti Deshatty (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Karthik Ramasubramanian, Krishna P Bhat D, Shelley Chen. Deepti Deshatty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82077?usp=email ) Change subject: common/block/tcss: Add config for PDC<->PMC mux configuration ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82077/comment/3c8a9d8e_18cf0e7c : PS1, Line 16: USB3 plugged during G3, is detected after system boots from G3. > How about when USB3 plugged during S0 and S0ix? yes this is verified. -- To view, visit https://review.coreboot.org/c/coreboot/+/82077?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieeb503393418cdad43384be39ac49c93ba91e4db Gerrit-Change-Number: 82077 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-CC: Pavan Holla <pholla(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 07:12:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: ec/google/chromeec: Fill typec ssdt based on TCSS mux config
by Krishna P Bhat D (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Caveh Jalali, Forest Mittelberg. Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82134?usp=email ) Change subject: ec/google/chromeec: Fill typec ssdt based on TCSS mux config ...................................................................... ec/google/chromeec: Fill typec ssdt based on TCSS mux config In platforms that use PDC<->PMC direct connection to perform mux configuration, PDC directly communicates the type-c port info to PMC. Therefore, kernel does not need to talk to EC and PMC for mux configuration. cros_ec_typec driver in kernel provides support for accessing the Type-C information from Chrome OS EC. Now with TCSS using PDC<->OMC mux config, this driver is not required to be loaded in kernel to get typec port connector information. So do not create a USB Type-C control ACPI device. BUG=b:332383540 TEST=Build and boot to OS on brox. Check SSDT before and after this patch for USB Type-C device ID. Change-Id: I0ffe8a1b444be9d330d71e9c967b5afa85b262b3 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/ec/google/chromeec/ec_acpi.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/82134/1 diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 61d1e5c..67e5325 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -285,7 +285,9 @@ if (CONFIG(DRIVERS_INTEL_DPTF)) ec_fill_dptf_helpers(ec, dev); - fill_ssdt_typec_device(dev); + if (!CONFIG(SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION)) + fill_ssdt_typec_device(dev); + fill_ssdt_ps2_keyboard(dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/82134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ffe8a1b444be9d330d71e9c967b5afa85b262b3 Gerrit-Change-Number: 82134 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: mb/google/brox:Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
by Krishna P Bhat D (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Karthik Ramasubramanian, Krishna P Bhat D, Shelley Chen. Hello Karthik Ramasubramanian, Shelley Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82078?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/brox:Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION ...................................................................... mb/google/brox:Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION Brox uses PDC<->PMC direct connection for USBC mux configuration. Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION to enable it. This patch also adds additional dependency on ENABLE_TCSS_USB_DETECTION to be selected only when PDC<->PMC direct connection and CHROMEOS is not used. BUG=b:332383540 TEST=USB3 plugged during G3, is detected after system boots from G3. Cq-Depend: chromium:5484387 Cq-Depend: chrome-internal:7106592 Change-Id: I0f62943f87d8fb6eb494c0aca3ef08c33cd05ffd Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/brox/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/82078/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f62943f87d8fb6eb494c0aca3ef08c33cd05ffd Gerrit-Change-Number: 82078 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Pavan Holla <pholla(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp: Use pre-processor to define ASL handler names
by Shuo Liu (Code Review) 30 Apr '24

30 Apr '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82133?usp=email ) Change subject: soc/intel/xeon_sp: Use pre-processor to define ASL handler names ...................................................................... soc/intel/xeon_sp: Use pre-processor to define ASL handler names ASL handler name is 4-byte length ACPI name in the scope of \_SB which is not quite human readable easy to be mixed with other methods under \_SB. Use pre-processor to define human readable handler names so that they are well managed in \_SB scope. As to the parameter count of the ASL handler, which is limited to 8 by ACPI specification. It is encouraged to use up the Arg0-7 first. If the need argument exceeds 8, the last Arg (Arg7) could be passed as a package of more parameters, which could be extracted into unused local variables in the ASL handler codes. Here is example, ASL caller: acpigen_write_return_namestr(ASL_HANDLER_PATH(AH_XXX)); /* passing the 1st-7th arg */ ... /* the 8th arg is a package, e.g. len = 3 */ acpigen_write_package(3); acpigen_write_integer(...); acpigen_write_integer(...); acpigen_write_integer(...); acpigen_write_package_end(); ASL callee: Local0 = DeRefOf(Arg7[0]) Local1 = DeRefOf(Arg7[1]) Local2 = DeRefOf(Arg7[2]) TEST=Build and boot on intel/archercity CRB Change-Id: I4134b275143d4f52622b864ed202252b2a150dae Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/include/soc/asl_handler.h 3 files changed, 23 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/82133/1 diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index b513d25..7f04588 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -3,6 +3,7 @@ #include <acpi/acpigen.h> #include <assert.h> #include <intelblocks/acpi.h> +#include <soc/asl_handler.h> #include <soc/chip_common.h> #include <soc/pci_devs.h> #include <soc/util.h> @@ -127,7 +128,7 @@ { acpigen_write_method("_OSC", 4); - acpigen_write_return_namestr("\\_SB.POSC"); + acpigen_write_return_namestr(ASL_HANDLER_PATH(AH_PCIE_OSC)); acpigen_emit_byte(ARG0_OP); acpigen_emit_byte(ARG1_OP); acpigen_emit_byte(ARG2_OP); diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl index c943dd5..7cd8848 100644 --- a/src/soc/intel/xeon_sp/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/iiostack.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <soc/asl_handler.h> + #define PCI_HOST_BRIDGE_OSC_UUID "33db4d5b-1ff7-401c-9657-7441c03dd766" #define CXL_HOST_BRIDGE_OSC_UUID "68f2d50b-c469-4d8a-bd3d-941a103fd3fc" @@ -16,7 +18,7 @@ Scope (\_SB) { /* - * \_SB.POSC - OSC handler for PCIe _OSC calls + * AH_PCIE_OSC - ASL handler for PCIe _OSC calls * * Reference: * 6.2.11 in https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/06_Device_Configuration/Devic… @@ -30,9 +32,9 @@ * Arg1 - Map to _OSC Arg1. An Integer containing a Revision ID of the buffer format * Arg2 - Map to _OSC Arg2. An Integer containing a count of entries in Arg3 * Arg3 - Map to _OSC Arg3. A Buffer containing a list of DWORD capabilities - * Arg4 - GrantedPCIeFeatures - * Arg5 - IsCxlDomain - * Arg6 - GrantedCxlFeatures + * Arg4 - Extra parameter. GrantedPCIeFeatures + * Arg5 - Extra parameter. IsCxlDomain + * Arg6 - Extra parameter. GrantedCxlFeatures * * _OSC ASL Return Value: * A Buffer containing a list of capabilities @@ -59,9 +61,8 @@ * OTRC - Dword Local7 0x10 CXL Features that OS requests for control */ - Method (POSC, 7, NotSerialized) + Method (AH_PCIE_OSC, 7, NotSerialized) { - #define OscArg0 Arg0 #define OscArg1 Arg1 #define OscArg2 Arg2 diff --git a/src/soc/intel/xeon_sp/include/soc/asl_handler.h b/src/soc/intel/xeon_sp/include/soc/asl_handler.h new file mode 100644 index 0000000..ec90830 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/asl_handler.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ASL_HANDLER_H_ +#define _SOC_ASL_HANDLER_H_ + +#define _TO_STR(name) #name +#define TO_STR(name) _TO_STR(name) +#define _ASL_HANDLER_PATH(scope, name) TO_STR(scope.name) +#define ASL_HANDLER_PATH(name) _ASL_HANDLER_PATH(\\_SB, name) + +/* ASL handler name list */ +#define AH_PCIE_OSC H000 + +#endif /* _SOC_ASL_HANDLER_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/82133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4134b275143d4f52622b864ed202252b2a150dae Gerrit-Change-Number: 82133 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp: Remove unused xeonsp_acpi_create_madt_lapics
by Shuo Liu (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82110?usp=email to look at the new patch set (#2). Change subject: soc/intel/xeon_sp: Remove unused xeonsp_acpi_create_madt_lapics ...................................................................... soc/intel/xeon_sp: Remove unused xeonsp_acpi_create_madt_lapics TEST=Build and boot on intel/archercity CRB Change-Id: I06e5ff635c37253b1c8f151b62f696ff7e5e22ef Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/spr/soc_acpi.c 2 files changed, 0 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/82110/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06e5ff635c37253b1c8f151b62f696ff7e5e22ef Gerrit-Change-Number: 82110 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE
by Elyes Haouas (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Christian Walter, Dinesh Gehlot, Felix Singer, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Subrata Banik, Tim Crawford. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82115?usp=email ) Change subject: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: One question please: We have USE_DDR4 and USE_DDR5, so why you don't use those kconfig symbols and then use SPD size already defined at "include/device/dram/ddr{4,5}.h" ? -- To view, visit https://review.coreboot.org/c/coreboot/+/82115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Gerrit-Change-Number: 82115 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 06:40:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2024