coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

1 participants
3292 discussions

[M] Change in libgfxinit[cros]: gma pipe_setup: Update for TGL & ADL
by Dinesh Gehlot (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to do a code review. Please visit https://review.coreboot.org/c/libgfxinit/+/82138?usp=email to review the following change. Change subject: gma pipe_setup: Update for TGL & ADL ...................................................................... gma pipe_setup: Update for TGL & ADL Tiger Lake requires some differences in plane programming over prior generations, including new chicken bits, wider watermarks, MBUS DBOX programming and a few bits moved around. Alder Lake brings some more chicken bits and requires arb-slot programming. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I93329c0a012da83abc379d6782fabe257dc180f3 --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-pipe_setup.adb M common/hw-gfx-gma-pipe_setup.ads M common/hw-gfx-gma-transcoder.adb 4 files changed, 151 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/38/82138/1 diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index dd6c2f8..b7af801 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -214,6 +214,16 @@ ----------- Transcoder ------- Need_Early_Transcoder_Setup : <genbool> := Tigerlake_On; + Need_Pipe_Arb_Slots : <tglbool> := Alderlake_On; + + ----------- Planes ----------- + Has_Mbus_Dbox_Credits : <genbool> := Tigerlake_On; + Has_Wide_Watermarks : <genbool> := Tigerlake_On; + Has_Plane_Color_Control : <genbool> := Tigerlake_On; + Has_New_Mbus_Dbox_Credits : <tglbool> := (Alderlake_On and Is_LP); + + ----------- Pipe ------------- + Need_Underrun_Rec_Disable : <tglbool> := Alderlake_On; --------- Panel power: ------- Has_PP_Write_Protection : <genbool> := Up_To_Ironlake; diff --git a/common/hw-gfx-gma-pipe_setup.adb b/common/hw-gfx-gma-pipe_setup.adb index 82f5222..6edcff1 100644 --- a/common/hw-gfx-gma-pipe_setup.adb +++ b/common/hw-gfx-gma-pipe_setup.adb @@ -43,6 +43,8 @@ DSPCNTR_DISABLE_TRICKLE_FEED or DSPCNTR_TILED_SURFACE_X_TILED; + PLANE_COLOR_CTL_PLANE_GAMMA_DISABLE : constant := 1 * 2 ** 13; + PLANE_CTL_PLANE_ENABLE : constant := 1 * 2 ** 31; PLANE_CTL_SRC_PIX_FMT_RGB_32B_8888 : constant := 4 * 2 ** 24; PLANE_CTL_PLANE_GAMMA_DISABLE : constant := 1 * 2 ** 13; @@ -67,7 +69,11 @@ PLANE_WM_ENABLE : constant := 1 * 2 ** 31; PLANE_WM_LINES_SHIFT : constant := 14; PLANE_WM_LINES_MASK : constant := 16#001f# * 2 ** 14; - PLANE_WM_BLOCKS_MASK : constant := 16#03ff# * 2 ** 0; + PLANE_WM_BLOCKS_MASK : constant := + (if Config.Has_Wide_Watermarks then 16#7ff# else 16#3ff#); + + PIPEMISC_HDR_MODE_PRECISION : constant := 1 * 2 ** 23; + PIPEMISC_PIXEL_ROUNDING_TRUNC : constant := 1 * 2 ** 8; VGA_SR_INDEX : constant := 16#03c4#; VGA_SR_DATA : constant := 16#03c5#; @@ -89,6 +95,9 @@ (Cursor_64x64 => 16#27#, Cursor_128x128 => 16#22#, Cursor_256x256 => 16#23#)); + subtype ARB_Slots is Natural range 0 .. 7; + function MCURSOR_ARB_SLOTS (N : ARB_Slots) return Word32 is + (Shift_Left (Word32 (N), 28)); function CUR_POS_Y (Y : Int32) return Word32 is ((if Y >= 0 then 0 else 1 * 2 ** 31) or Shift_Left (Word32 (abs Y), 16)) @@ -201,13 +210,6 @@ (Controller : Controller_Type; FB : HW.GFX.Framebuffer_Type) with - Global => (In_Out => Registers.Register_State), - Depends => - (Registers.Register_State - =>+ - (Registers.Register_State, - Controller, - FB)), Pre => FB.Height + FB.Start_Y <= FB.V_Stride is -- FIXME: setup correct format, based on framebuffer RGB format @@ -221,6 +223,18 @@ Stride, Offset : Word32; Width : constant Width_Type := Rotated_Width (FB); Height : constant Width_Type := Rotated_Height (FB); + + function PLANE_CTL_ARB_SLOTS (N : Word32) return Word32 is + (if Config.Need_Pipe_Arb_Slots then Shift_Left (N, 28) else 0); + + Plane_Ctl : constant Word32 := + PLANE_CTL_TILED_SURFACE (FB.Tiling) or + PLANE_CTL_PLANE_ROTATION (FB.Rotation) or + PLANE_CTL_SRC_PIX_FMT_RGB_32B_8888 or + PLANE_CTL_ARB_SLOTS (1) or + (if not Config.Has_Plane_Color_Control + then PLANE_CTL_PLANE_GAMMA_DISABLE + else 0); begin if Rotation_90 (FB) then Stride := Word32 (FB_Pitch (FB.V_Stride, FB)); @@ -231,13 +245,14 @@ Offset := Shift_Left (Word32 (FB.Start_Y), 16) or Word32 (FB.Start_X); end if; - Registers.Write - (Register => Controller.PLANE_CTL, - Value => PLANE_CTL_PLANE_ENABLE or - PLANE_CTL_SRC_PIX_FMT_RGB_32B_8888 or - PLANE_CTL_PLANE_GAMMA_DISABLE or - PLANE_CTL_TILED_SURFACE (FB.Tiling) or - PLANE_CTL_PLANE_ROTATION (FB.Rotation)); + + if Config.Has_Plane_Color_Control then + Registers.Write + (Register => Controller.PLANE_COLOR_CTL, + Value => PLANE_COLOR_CTL_PLANE_GAMMA_DISABLE); + end if; + Registers.Write (Controller.PLANE_AUX_DIST, 0); + Registers.Write (Controller.PLANE_CTL, Plane_Ctl); Registers.Write (Controller.PLANE_OFFSET, Offset); Registers.Write (Controller.PLANE_SIZE, Encode (Width, Height)); Registers.Write (Controller.PLANE_STRIDE, Stride); @@ -294,13 +309,87 @@ use type Word8; Reg8 : Word8; + + type BW_Credit is new Natural range 0 .. 3; + function MBUS_DBOX_BW_CREDIT (C : BW_Credit) return Word32 is + (Shift_Left (Word32 (C), 14)); + + type B_Credit is new Natural range 0 .. 31; + function MBUS_DBOX_B_CREDIT (C : B_Credit) return Word32 is + (Shift_Left (Word32 (C), 8)); + + type A_Credit is new Natural range 0 .. 15; + function MBUS_DBOX_A_CREDIT (C : A_Credit) return Word32 is + (Word32 (C)); + + type B2B_Trans_Max is new Natural range 0 .. 31; + function MBUS_DBOX_B2B_TRANSACTIONS_MAX (B : B2B_Trans_Max) return Word32 is + (Shift_Left (Word32 (B), 20)); + + type B2B_Trans_Delay is new Natural range 0 .. 7; + function MBUS_DBOX_B2B_TRANSACTIONS_DELAY (B : B2B_Trans_Delay) return Word32 is + (Shift_Left (Word32 (B), 17)); + MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN : constant := 1 * 2 ** 16; + + procedure Program_Mbus_Dbox_Credits is + Tmp : Word32; + begin + Tmp := MBUS_DBOX_B2B_TRANSACTIONS_MAX (16) or + MBUS_DBOX_B2B_TRANSACTIONS_DELAY (1) or + MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN; + + if Config.Has_New_Mbus_Dbox_Credits then + Tmp := Tmp or MBUS_DBOX_BW_CREDIT (2) or + MBUS_DBOX_B_CREDIT (8) or + MBUS_DBOX_A_CREDIT (6); + else + Tmp := Tmp or MBUS_DBOX_BW_CREDIT (2) or + MBUS_DBOX_B_CREDIT (12) or + MBUS_DBOX_A_CREDIT (2); + end if; + + Registers.Write + (Register => Controller.MBUS_DBOX_CTL, + Value => Tmp); + end Program_Mbus_Dbox_Credits; + + -- Display WA # 1605353570: icl + -- Set the pixel rounding bit to 1 for allowing + -- passthrough of Frame buffer pixels unmodified + -- across pipe + PIXEL_ROUNDING_TRUNC_FB_PASSTHRU : constant := 1 * 2 ** 15; + + -- Display WA #1153: icl + -- enable hardware to bypass the alpha math + -- and rounding for per-pixel values 00 and 0xff + PER_PIXEL_ALPHA_BYPASS_EN : constant := 1 * 2 ** 7; + + -- ADL_P requires that we disable underrun recovery when + -- downscaling (or using the scaler for YUV420 pipe output), + -- using DSC, or using PSR2. + -- i915 always disables underrun recovery for gen 13+. + UNDERRUN_RECOVERY_DISABLE : constant := 1 * 2 ** 30; begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + if Config.Has_Type_C_Ports then + Registers.Set_Mask + (Register => Controller.PIPE_CHICKEN, + Mask => PER_PIXEL_ALPHA_BYPASS_EN or + PIXEL_ROUNDING_TRUNC_FB_PASSTHRU or + (if Config.Need_Underrun_Rec_Disable + then UNDERRUN_RECOVERY_DISABLE + else 0)); + end if; + if Config.Has_Plane_Control then Setup_Watermarks (Controller); end if; + if Config.Has_Mbus_Dbox_Credits then + Program_Mbus_Dbox_Credits; + end if; + if Framebuffer.Offset = VGA_PLANE_FRAMEBUFFER_OFFSET then if Config.VGA_Plane_Workaround then Registers.Unset_And_Set_Mask @@ -336,7 +425,10 @@ if Config.Has_Pipeconf_Misc then Registers.Write (Register => Controller.PIPEMISC, - Value => Transcoder.BPC_Conf (Dither_BPC, Dither)); + Value => Transcoder.BPC_Conf (Dither_BPC, Dither) or + -- FIXME: Should we set these at all? + (if Config.Has_Plane_Color_Control then + (PIPEMISC_PIXEL_ROUNDING_TRUNC or PIPEMISC_HDR_MODE_PRECISION) else 0)); end if; end Setup_Display; @@ -352,8 +444,10 @@ -- so keep it first Registers.Write (Register => Cursors (Pipe).CTL, - Value => CUR_CTL_PIPE_SELECT (Pipe) or - CUR_CTL_MODE (Cursor.Mode, Cursor.Size)); + Value => CUR_CTL_MODE (Cursor.Mode, Cursor.Size) or + (if Config.Need_Pipe_Arb_Slots + then MCURSOR_ARB_SLOTS (1) + else CUR_CTL_PIPE_SELECT (Pipe))); Place_Cursor (Pipe, FB, Cursor); end Update_Cursor; diff --git a/common/hw-gfx-gma-pipe_setup.ads b/common/hw-gfx-gma-pipe_setup.ads index 7270cb2..20a1dd4 100644 --- a/common/hw-gfx-gma-pipe_setup.ads +++ b/common/hw-gfx-gma-pipe_setup.ads @@ -100,6 +100,10 @@ PLANE_WM : PLANE_WM_Type; CUR_BUF_CFG : Registers.Registers_Index; CUR_WM : PLANE_WM_Type; + MBUS_DBOX_CTL : Registers.Registers_Index; + PIPE_CHICKEN : Registers.Registers_Index; + PLANE_COLOR_CTL : Registers.Registers_Index; + PLANE_AUX_DIST : Registers.Registers_Index; end record; type Controller_Array is array (Pipe_Index) of Controller_Type; @@ -149,7 +153,11 @@ Registers.CUR_WM_A_4, Registers.CUR_WM_A_5, Registers.CUR_WM_A_6, - Registers.CUR_WM_A_7)), + Registers.CUR_WM_A_7), + MBUS_DBOX_CTL => Registers.PIPE_MBUS_DBOX_CTL_A, + PIPE_CHICKEN => Registers.PIPEA_CHICKEN, + PLANE_COLOR_CTL => Registers.PLANE_COLOR_CTL_1_A, + PLANE_AUX_DIST => Registers.PLANE_AUX_DIST_1_A), Secondary => Controller_Type' (Pipe => Secondary, PIPESRC => Registers.PIPEBSRC, @@ -194,7 +202,11 @@ Registers.CUR_WM_B_4, Registers.CUR_WM_B_5, Registers.CUR_WM_B_6, - Registers.CUR_WM_B_7)), + Registers.CUR_WM_B_7), + MBUS_DBOX_CTL => Registers.PIPE_MBUS_DBOX_CTL_B, + PIPE_CHICKEN => Registers.PIPEB_CHICKEN, + PLANE_COLOR_CTL => Registers.PLANE_COLOR_CTL_1_B, + PLANE_AUX_DIST => Registers.PLANE_AUX_DIST_1_B), Tertiary => Controller_Type' (Pipe => Tertiary, PIPESRC => Registers.PIPECSRC, @@ -239,7 +251,11 @@ Registers.CUR_WM_C_4, Registers.CUR_WM_C_5, Registers.CUR_WM_C_6, - Registers.CUR_WM_C_7))); + Registers.CUR_WM_C_7), + MBUS_DBOX_CTL => Registers.PIPE_MBUS_DBOX_CTL_C, + PIPE_CHICKEN => Registers.PIPEC_CHICKEN, + PLANE_COLOR_CTL => Registers.PLANE_COLOR_CTL_1_C, + PLANE_AUX_DIST => Registers.PLANE_AUX_DIST_1_C)); type Cursor_Regs is record CTL : Registers.Registers_Index; diff --git a/common/hw-gfx-gma-transcoder.adb b/common/hw-gfx-gma-transcoder.adb index 9e85b75..40c2cad 100644 --- a/common/hw-gfx-gma-transcoder.adb +++ b/common/hw-gfx-gma-transcoder.adb @@ -328,8 +328,10 @@ Dither : Boolean; Scale : Boolean) is + use type HW.GFX.GMA.Registers.Registers_Invalid_Index; Trans : Transcoder_Regs renames Transcoders (Get_Idx (Pipe, Port_Cfg.Port)); + PIPE_ARB_USE_PROG_SLOTS : constant := 1 * 2 ** 13; begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); if not Config.Need_Early_Transcoder_Setup then @@ -342,6 +344,14 @@ Mask => DDI_FUNC_CTL_ENABLE); end if; + if Config.Need_Pipe_Arb_Slots and then + Trans.PIPE_ARB_CTL /= Registers.Invalid_Register + then + Registers.Set_Mask + (Register => Trans.PIPE_ARB_CTL, + Mask => PIPE_ARB_USE_PROG_SLOTS); + end if; + Registers.Write (Register => Trans.CONF, Value => TRANS_CONF_ENABLE or -- To view, visit https://review.coreboot.org/c/libgfxinit/+/82138?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: cros Gerrit-Change-Id: I93329c0a012da83abc379d6782fabe257dc180f3 Gerrit-Change-Number: 82138 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in libgfxinit[cros]: gma display_probing: Make new TGL ports available
by Dinesh Gehlot (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Nico Huber. Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/libgfxinit/+/82137?usp=email to review the following change. Change subject: gma display_probing: Make new TGL ports available ...................................................................... gma display_probing: Make new TGL ports available Change-Id: I9d96673f931be0086536044694ecd127ba2a823d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/hw-gfx-gma-display_probing.adb M common/hw-gfx-gma-display_probing.ads 2 files changed, 26 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/37/82137/1 diff --git a/common/hw-gfx-gma-display_probing.adb b/common/hw-gfx-gma-display_probing.adb index 67f8ddf..fa2a4f7 100644 --- a/common/hw-gfx-gma-display_probing.adb +++ b/common/hw-gfx-gma-display_probing.adb @@ -75,12 +75,26 @@ declare DP_Port : constant GMA.DP_Port := - (case Port is - when eDP => DP_A, - when DP1 => DP_B, - when DP2 => DP_C, - when DP3 => DP_D, - when others => GMA.DP_Port'First); + (if Config.Has_Type_C_Ports then + (case Port is + when eDP => DP_A, -- FIXME: should be configurable which is used for eDP + when DP1 => DP_A, + when DP2 => DP_B, + when DP3 => DP_C, + when USBC1_DP => DP_D, + when USBC2_DP => DP_E, + when USBC3_DP => DP_F, + when USBC4_DP => DP_G, + when USBC5_DP => DP_H, + when USBC6_DP => DP_I, + when others => GMA.DP_Port'First) + else + (case Port is + when eDP => DP_A, + when DP1 => DP_B, + when DP2 => DP_C, + when DP3 => DP_D, + when others => GMA.DP_Port'First)); begin DP_Aux_Ch.I2C_Read (Port => DP_Port, diff --git a/common/hw-gfx-gma-display_probing.ads b/common/hw-gfx-gma-display_probing.ads index 5dcdbd4..7479fdd 100644 --- a/common/hw-gfx-gma-display_probing.ads +++ b/common/hw-gfx-gma-display_probing.ads @@ -17,10 +17,14 @@ package HW.GFX.GMA.Display_Probing is - type Port_List_Range is range 0 .. 8; + type Port_List_Range is range 0 .. 20; type Port_List is array (Port_List_Range) of Port_Type; All_Ports : constant Port_List := - (DP1, DP2, DP3, HDMI1, HDMI2, HDMI3, Analog, LVDS, eDP); + (DP1, DP2, DP3, + HDMI1, HDMI2, HDMI3, + USBC1_DP, USBC2_DP, USBC3_DP, USBC4_DP, USBC5_DP, USBC6_DP, + USBC1_HDMI, USBC2_HDMI, USBC3_HDMI, USBC4_HDMI, USBC5_HDMI, USBC6_HDMI, + Analog, LVDS, eDP); procedure Read_EDID (Raw_EDID : out EDID.Raw_EDID_Data; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/82137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: cros Gerrit-Change-Id: I9d96673f931be0086536044694ecd127ba2a823d Gerrit-Change-Number: 82137 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: mb/google/nissa: Create a riven variant
by David Wu (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82132?usp=email ) Change subject: mb/google/nissa: Create a riven variant ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/82132/comment/ee409550_cb073fdc : PS2, Line 445: BOARD_GOOGLE_RIVEN > is this Trulo based on Nirul based ? The riven variant is a reference to tivviks and nivviks. Sorry, I don't know what Nirul is, could you tell me more about it? Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/82132?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1be2346d87c891cc0e5fbda094e1f6e0dd60df1b Gerrit-Change-Number: 82132 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 30 Apr 2024 08:44:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for SPI RW
by Ashish Kumar Mishra (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Paul Menzel, Saurabh Mishra, Subrata Banik. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email ) Change subject: block/fast_spi: Use read32p/write32p for SPI RW ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82079/comment/4f9f6223_165dd33b : PS5, Line 14: TEST=Build and boot mtl 64-bit and verified MRC cache working. > can you please highlight if you have tested this CL with both existing 32-bit and future 64-bit plat […] Sure. This I have tested with RPL(brox/skolas) and future 64 bit platforms as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 5 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 30 Apr 2024 08:39:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/corsola: Add new board variant Squirtle
by Xuxin Xiong (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Hung-Te Lin, Yang Wu, Yidi Lin, Yu-Ping Wu. Xuxin Xiong has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82117?usp=email ) Change subject: mb/google/corsola: Add new board variant Squirtle ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I393738fc470ffc907f125647a46bf81c243708d7 Gerrit-Change-Number: 82117 Gerrit-PatchSet: 2 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 08:39:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp: Remove unused xeonsp_acpi_create_madt_lapics
by Angel Pons (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82110?usp=email ) Change subject: soc/intel/xeon_sp: Remove unused xeonsp_acpi_create_madt_lapics ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06e5ff635c37253b1c8f151b62f696ff7e5e22ef Gerrit-Change-Number: 82110 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 08:34:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE
by Nico Huber (Code Review) 30 Apr '24

30 Apr '24

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82115?usp=email ) Change subject: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE ...................................................................... soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total SPD size of 512 bytes. Set this as the default and remove the setting from mainboard Kconfigs. Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brya/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/shadowmountain/Kconfig M src/mainboard/msi/ms7d25/Kconfig M src/mainboard/msi/ms7e06/Kconfig M src/mainboard/prodrive/atlas/Kconfig M src/mainboard/system76/adl/Kconfig M src/mainboard/system76/rpl/Kconfig M src/soc/intel/alderlake/Kconfig 10 files changed, 3 insertions(+), 27 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 0ec5220..77ba5db 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -131,9 +131,6 @@ config VBOOT select VBOOT_LID_SWITCH -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1565f13..79b54f0 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -817,9 +817,6 @@ select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA select VBOOT_LID_SWITCH -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 1083ce2..5ee091b 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -135,9 +135,6 @@ config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config DIMM_SPD_SIZE - default 512 - choice prompt "ON BOARD EC" default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_RPL_EXT_EC diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig index 17c0014..f01479b 100644 --- a/src/mainboard/intel/shadowmountain/Kconfig +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -42,9 +42,6 @@ select HAS_RECOVERY_MRC_CACHE select VBOOT_EARLY_EC_SYNC -config DIMM_SPD_SIZE - default 512 - config DEVICETREE default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/msi/ms7d25/Kconfig b/src/mainboard/msi/ms7d25/Kconfig index 3fb6f40..ab9fa2b 100644 --- a/src/mainboard/msi/ms7d25/Kconfig +++ b/src/mainboard/msi/ms7d25/Kconfig @@ -41,9 +41,6 @@ string default "2.0" if BOARD_MSI_Z690_A_PRO_WIFI_DDR5 -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/msi/ms7e06/Kconfig b/src/mainboard/msi/ms7e06/Kconfig index c46effc..cfa6447 100644 --- a/src/mainboard/msi/ms7e06/Kconfig +++ b/src/mainboard/msi/ms7e06/Kconfig @@ -34,9 +34,6 @@ config MAINBOARD_FAMILY default "Default string" -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE default 0 diff --git a/src/mainboard/prodrive/atlas/Kconfig b/src/mainboard/prodrive/atlas/Kconfig index 5a3f311..b40e2b7 100644 --- a/src/mainboard/prodrive/atlas/Kconfig +++ b/src/mainboard/prodrive/atlas/Kconfig @@ -47,9 +47,6 @@ string default "Prodrive Technologies B.V." -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig index 5213cfe..3d364f1 100644 --- a/src/mainboard/system76/adl/Kconfig +++ b/src/mainboard/system76/adl/Kconfig @@ -103,9 +103,6 @@ config D3COLD_SUPPORT default n -config DIMM_SPD_SIZE - default 512 - config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig index 2a850ae..60ea71b 100644 --- a/src/mainboard/system76/rpl/Kconfig +++ b/src/mainboard/system76/rpl/Kconfig @@ -125,9 +125,6 @@ config D3COLD_SUPPORT default n -config DIMM_SPD_SIZE - default 512 - config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 5086069..b124b14 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -146,6 +146,9 @@ if SOC_INTEL_ALDERLAKE +config DIMM_SPD_SIZE + default 512 + config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT bool default n if SOC_INTEL_ALDERLAKE_PCH_S -- To view, visit https://review.coreboot.org/c/coreboot/+/82115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Gerrit-Change-Number: 82115 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE
by Nico Huber (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Christian Walter, Dinesh Gehlot, Elyes Haouas, Felix Singer, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Subrata Banik, Tim Crawford. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82115?usp=email ) Change subject: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > One question please: […] For many of these boards, it would double the size. This patch is just a refactoring, though that shouldn't change things. Maybe developers chose the 512B instead of the maximum for a good reason? -- To view, visit https://review.coreboot.org/c/coreboot/+/82115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Gerrit-Change-Number: 82115 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 30 Apr 2024 08:28:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE
by Angel Pons (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Christian Walter, Dinesh Gehlot, Elyes Haouas, Felix Singer, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Subrata Banik, Tim Crawford. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82115?usp=email ) Change subject: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > One question please: […] That won't set the `DIMM_SPD_SIZE` Kconfig's value, though. -- To view, visit https://review.coreboot.org/c/coreboot/+/82115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Gerrit-Change-Number: 82115 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 30 Apr 2024 08:23:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE
by Nico Huber (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Christian Walter, Dinesh Gehlot, Felix Singer, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Subrata Banik, Tim Crawford. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82115?usp=email ) Change subject: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Gerrit-Change-Number: 82115 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 08:22:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2024